1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_CLK_MGR_H__ 27 #define __DAL_CLK_MGR_H__ 28 29 #include "dc.h" 30 #include "dm_pp_smu.h" 31 32 /* Constants */ 33 #define DDR4_DRAM_WIDTH 64 34 #define WM_A 0 35 #define WM_B 1 36 #define WM_C 2 37 #define WM_D 3 38 #define WM_SET_COUNT 4 39 #define WM_1A 2 40 #define WM_1B 3 41 42 #define DCN_MINIMUM_DISPCLK_Khz 100000 43 #define DCN_MINIMUM_DPPCLK_Khz 100000 44 45 struct dcn3_clk_internal { 46 int dummy; 47 // TODO: 48 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 49 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 50 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 51 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 52 uint32_t CLK1_CLK4_CURRENT_CNT; 53 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 54 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 55 56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 60 61 uint32_t CLK4_CLK0_CURRENT_CNT; //fclk 62 }; 63 64 struct dcn35_clk_internal { 65 int dummy; 66 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 67 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 68 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 69 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 70 uint32_t CLK1_CLK4_CURRENT_CNT; //dtbclk 71 //uint32_t CLK1_CLK5_CURRENT_CNT; //dpiaclk 72 //uint32_t CLK1_CLK6_CURRENT_CNT; //srdbgclk 73 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 74 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 75 76 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 77 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 78 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 79 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 80 uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass 81 }; 82 83 struct dcn301_clk_internal { 84 int dummy; 85 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 86 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 87 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 88 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 89 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 90 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 91 92 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 93 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 94 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 95 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 96 }; 97 98 /* Will these bw structures be ASIC specific? */ 99 100 #define MAX_NUM_DPM_LVL 8 101 #define WM_SET_COUNT 4 102 103 enum clk_type { 104 CLK_TYPE_DCFCLK, 105 CLK_TYPE_FCLK, 106 CLK_TYPE_MCLK, 107 CLK_TYPE_SOCCLK, 108 CLK_TYPE_DTBCLK, 109 CLK_TYPE_DISPCLK, 110 CLK_TYPE_DPPCLK, 111 CLK_TYPE_DSCCLK, 112 CLK_TYPE_COUNT 113 }; 114 115 struct clk_limit_table_entry { 116 unsigned int voltage; /* milivolts withh 2 fractional bits */ 117 unsigned int dcfclk_mhz; 118 unsigned int fclk_mhz; 119 unsigned int memclk_mhz; 120 unsigned int socclk_mhz; 121 unsigned int dtbclk_mhz; 122 unsigned int dispclk_mhz; 123 unsigned int dppclk_mhz; 124 unsigned int phyclk_mhz; 125 unsigned int phyclk_d18_mhz; 126 unsigned int wck_ratio; 127 }; 128 129 struct clk_limit_num_entries { 130 unsigned int num_dcfclk_levels; 131 unsigned int num_fclk_levels; 132 unsigned int num_memclk_levels; 133 unsigned int num_socclk_levels; 134 unsigned int num_dtbclk_levels; 135 unsigned int num_dispclk_levels; 136 unsigned int num_dppclk_levels; 137 unsigned int num_phyclk_levels; 138 unsigned int num_phyclk_d18_levels; 139 }; 140 141 /* This table is contiguous */ 142 struct clk_limit_table { 143 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL]; 144 struct clk_limit_num_entries num_entries_per_clk; 145 unsigned int num_entries; /* highest populated dpm level for back compatibility */ 146 }; 147 148 struct wm_range_table_entry { 149 unsigned int wm_inst; 150 unsigned int wm_type; 151 double pstate_latency_us; 152 double sr_exit_time_us; 153 double sr_enter_plus_exit_time_us; 154 bool valid; 155 }; 156 157 struct nv_wm_range_entry { 158 bool valid; 159 160 struct { 161 uint8_t wm_type; 162 uint16_t min_dcfclk; 163 uint16_t max_dcfclk; 164 uint16_t min_uclk; 165 uint16_t max_uclk; 166 } pmfw_breakdown; 167 168 struct { 169 double pstate_latency_us; 170 double sr_exit_time_us; 171 double sr_enter_plus_exit_time_us; 172 double fclk_change_latency_us; 173 } dml_input; 174 }; 175 176 struct clk_log_info { 177 bool enabled; 178 char *pBuf; 179 unsigned int bufSize; 180 unsigned int *sum_chars_printed; 181 }; 182 183 struct clk_state_registers_and_bypass { 184 uint32_t dcfclk; 185 uint32_t dcf_deep_sleep_divider; 186 uint32_t dcf_deep_sleep_allow; 187 uint32_t dprefclk; 188 uint32_t dispclk; 189 uint32_t dppclk; 190 uint32_t dtbclk; 191 uint32_t fclk; 192 193 uint32_t dppclk_bypass; 194 uint32_t dcfclk_bypass; 195 uint32_t dprefclk_bypass; 196 uint32_t dispclk_bypass; 197 }; 198 199 struct rv1_clk_internal { 200 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 201 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 202 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 203 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 204 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 205 206 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass 207 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass 208 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass 209 }; 210 211 struct rn_clk_internal { 212 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 213 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 214 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 215 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 216 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 217 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 218 219 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 220 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 221 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 222 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 223 224 }; 225 226 /* For dtn logging and debugging */ 227 struct clk_state_registers { 228 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 229 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 230 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 231 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 232 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 233 }; 234 235 /* TODO: combine this with the above */ 236 struct clk_bypass { 237 uint32_t dcfclk_bypass; 238 uint32_t dispclk_pypass; 239 uint32_t dprefclk_bypass; 240 }; 241 /* 242 * This table is not contiguous, can have holes, each 243 * entry correspond to one set of WM. For example if 244 * we have 2 DPM and LPDDR, we will WM set A, B and 245 * D occupied, C will be emptry. 246 */ 247 struct wm_table { 248 union { 249 struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; 250 struct wm_range_table_entry entries[WM_SET_COUNT]; 251 }; 252 }; 253 254 struct dummy_pstate_entry { 255 unsigned int dram_speed_mts; 256 unsigned int dummy_pstate_latency_us; 257 }; 258 259 struct clk_bw_params { 260 unsigned int vram_type; 261 unsigned int num_channels; 262 unsigned int dram_channel_width_bytes; 263 unsigned int dispclk_vco_khz; 264 unsigned int dc_mode_softmax_memclk; 265 unsigned int max_memclk_mhz; 266 struct clk_limit_table clk_table; 267 struct wm_table wm_table; 268 struct dummy_pstate_entry dummy_pstate_table[4]; 269 struct clk_limit_table_entry dc_mode_limit; 270 }; 271 /* Public interfaces */ 272 273 struct clk_states { 274 uint32_t dprefclk_khz; 275 }; 276 277 struct clk_mgr_funcs { 278 /* 279 * This function should set new clocks based on the input "safe_to_lower". 280 * If safe_to_lower == false, then only clocks which are to be increased 281 * should changed. 282 * If safe_to_lower == true, then only clocks which are to be decreased 283 * should be changed. 284 */ 285 void (*update_clocks)(struct clk_mgr *clk_mgr, 286 struct dc_state *context, 287 bool safe_to_lower); 288 289 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); 290 int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr); 291 292 void (*set_low_power_state)(struct clk_mgr *clk_mgr); 293 void (*exit_low_power_state)(struct clk_mgr *clk_mgr); 294 bool (*is_ips_supported)(struct clk_mgr *clk_mgr); 295 296 void (*init_clocks)(struct clk_mgr *clk_mgr); 297 298 void (*dump_clk_registers)(struct clk_state_registers_and_bypass *regs_and_bypass, 299 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info); 300 301 void (*enable_pme_wa) (struct clk_mgr *clk_mgr); 302 void (*get_clock)(struct clk_mgr *clk_mgr, 303 struct dc_state *context, 304 enum dc_clock_type clock_type, 305 struct dc_clock_config *clock_cfg); 306 307 bool (*are_clock_states_equal) (struct dc_clocks *a, 308 struct dc_clocks *b); 309 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); 310 311 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 312 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link); 313 /* 314 * Send message to PMFW to set hard min memclk frequency 315 * When current_mode = false, set DPM0 316 * When current_mode = true, set required clock for current mode 317 */ 318 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode); 319 320 int (*get_hard_min_memclk)(struct clk_mgr *clk_mgr); 321 int (*get_hard_min_fclk)(struct clk_mgr *clk_mgr); 322 323 /* Send message to PMFW to set hard max memclk frequency to highest DPM */ 324 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); 325 326 /* Custom set a memclk freq range*/ 327 void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 328 void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 329 330 /* Get current memclk states from PMFW, update relevant structures */ 331 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); 332 333 /* Get SMU present */ 334 bool (*is_smu_present)(struct clk_mgr *clk_mgr); 335 336 int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base); 337 338 bool (*is_dc_mode_present)(struct clk_mgr *clk_mgr); 339 340 uint32_t (*set_smartmux_switch)(struct clk_mgr *clk_mgr, uint32_t pins_to_set); 341 342 unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type); 343 }; 344 345 struct clk_mgr { 346 struct dc_context *ctx; 347 struct clk_mgr_funcs *funcs; 348 struct dc_clocks clks; 349 bool psr_allow_active_cache; 350 bool force_smu_not_present; 351 bool dc_mode_softmax_enabled; 352 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes 353 int dp_dto_source_clock_in_khz; // Used to program DP DTO with ss adjustment on DCN314 354 int dentist_vco_freq_khz; 355 struct clk_state_registers_and_bypass boot_snapshot; 356 struct clk_bw_params *bw_params; 357 struct pp_smu_wm_range_sets ranges; 358 }; 359 360 /* forward declarations */ 361 struct dccg; 362 363 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); 364 365 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); 366 367 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 368 369 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 370 371 #endif /* __DAL_CLK_MGR_H__ */ 372