1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/of.h>
16 #include <linux/of_gpio.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pm_wakeirq.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/reset.h>
27
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/core.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
35
36 #include "cqhci.h"
37
38 #define MAX_BD_NUM 1024
39 #define MSDC_NR_CLOCKS 3
40
41 /*--------------------------------------------------------------------------*/
42 /* Common Definition */
43 /*--------------------------------------------------------------------------*/
44 #define MSDC_BUS_1BITS 0x0
45 #define MSDC_BUS_4BITS 0x1
46 #define MSDC_BUS_8BITS 0x2
47
48 #define MSDC_BURST_64B 0x6
49
50 /*--------------------------------------------------------------------------*/
51 /* Register Offset */
52 /*--------------------------------------------------------------------------*/
53 #define MSDC_CFG 0x0
54 #define MSDC_IOCON 0x04
55 #define MSDC_PS 0x08
56 #define MSDC_INT 0x0c
57 #define MSDC_INTEN 0x10
58 #define MSDC_FIFOCS 0x14
59 #define SDC_CFG 0x30
60 #define SDC_CMD 0x34
61 #define SDC_ARG 0x38
62 #define SDC_STS 0x3c
63 #define SDC_RESP0 0x40
64 #define SDC_RESP1 0x44
65 #define SDC_RESP2 0x48
66 #define SDC_RESP3 0x4c
67 #define SDC_BLK_NUM 0x50
68 #define SDC_ADV_CFG0 0x64
69 #define EMMC_IOCON 0x7c
70 #define SDC_ACMD_RESP 0x80
71 #define DMA_SA_H4BIT 0x8c
72 #define MSDC_DMA_SA 0x90
73 #define MSDC_DMA_CTRL 0x98
74 #define MSDC_DMA_CFG 0x9c
75 #define MSDC_PATCH_BIT 0xb0
76 #define MSDC_PATCH_BIT1 0xb4
77 #define MSDC_PATCH_BIT2 0xb8
78 #define MSDC_PAD_TUNE 0xec
79 #define MSDC_PAD_TUNE0 0xf0
80 #define PAD_DS_TUNE 0x188
81 #define PAD_CMD_TUNE 0x18c
82 #define EMMC51_CFG0 0x204
83 #define EMMC50_CFG0 0x208
84 #define EMMC50_CFG1 0x20c
85 #define EMMC50_CFG3 0x220
86 #define SDC_FIFO_CFG 0x228
87 #define CQHCI_SETTING 0x7fc
88
89 /*--------------------------------------------------------------------------*/
90 /* Top Pad Register Offset */
91 /*--------------------------------------------------------------------------*/
92 #define EMMC_TOP_CONTROL 0x00
93 #define EMMC_TOP_CMD 0x04
94 #define EMMC50_PAD_DS_TUNE 0x0c
95
96 /*--------------------------------------------------------------------------*/
97 /* Register Mask */
98 /*--------------------------------------------------------------------------*/
99
100 /* MSDC_CFG mask */
101 #define MSDC_CFG_MODE BIT(0) /* RW */
102 #define MSDC_CFG_CKPDN BIT(1) /* RW */
103 #define MSDC_CFG_RST BIT(2) /* RW */
104 #define MSDC_CFG_PIO BIT(3) /* RW */
105 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */
106 #define MSDC_CFG_BV18SDT BIT(5) /* RW */
107 #define MSDC_CFG_BV18PSS BIT(6) /* R */
108 #define MSDC_CFG_CKSTB BIT(7) /* R */
109 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */
110 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */
111 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */
112 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */
113 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */
114 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */
115
116 /* MSDC_IOCON mask */
117 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */
118 #define MSDC_IOCON_RSPL BIT(1) /* RW */
119 #define MSDC_IOCON_DSPL BIT(2) /* RW */
120 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */
121 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */
122 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */
123 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */
124 #define MSDC_IOCON_D0SPL BIT(16) /* RW */
125 #define MSDC_IOCON_D1SPL BIT(17) /* RW */
126 #define MSDC_IOCON_D2SPL BIT(18) /* RW */
127 #define MSDC_IOCON_D3SPL BIT(19) /* RW */
128 #define MSDC_IOCON_D4SPL BIT(20) /* RW */
129 #define MSDC_IOCON_D5SPL BIT(21) /* RW */
130 #define MSDC_IOCON_D6SPL BIT(22) /* RW */
131 #define MSDC_IOCON_D7SPL BIT(23) /* RW */
132 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */
133
134 /* MSDC_PS mask */
135 #define MSDC_PS_CDEN BIT(0) /* RW */
136 #define MSDC_PS_CDSTS BIT(1) /* R */
137 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */
138 #define MSDC_PS_DAT GENMASK(23, 16) /* R */
139 #define MSDC_PS_DATA1 BIT(17) /* R */
140 #define MSDC_PS_CMD BIT(24) /* R */
141 #define MSDC_PS_WP BIT(31) /* R */
142
143 /* MSDC_INT mask */
144 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */
145 #define MSDC_INT_CDSC BIT(1) /* W1C */
146 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */
147 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */
148 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */
149 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */
150 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */
151 #define MSDC_INT_CMDRDY BIT(8) /* W1C */
152 #define MSDC_INT_CMDTMO BIT(9) /* W1C */
153 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */
154 #define MSDC_INT_CSTA BIT(11) /* R */
155 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */
156 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */
157 #define MSDC_INT_DATTMO BIT(14) /* W1C */
158 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */
159 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */
160 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */
161 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */
162 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */
163 #define MSDC_INT_CMDQ BIT(28) /* W1C */
164
165 /* MSDC_INTEN mask */
166 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */
167 #define MSDC_INTEN_CDSC BIT(1) /* RW */
168 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */
169 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */
170 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */
171 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */
172 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */
173 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */
174 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */
175 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */
176 #define MSDC_INTEN_CSTA BIT(11) /* RW */
177 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */
178 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */
179 #define MSDC_INTEN_DATTMO BIT(14) /* RW */
180 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */
181 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */
182 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */
183 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */
184 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */
185
186 /* MSDC_FIFOCS mask */
187 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */
188 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */
189 #define MSDC_FIFOCS_CLR BIT(31) /* RW */
190
191 /* SDC_CFG mask */
192 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */
193 #define SDC_CFG_INSWKUP BIT(1) /* RW */
194 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */
195 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */
196 #define SDC_CFG_SDIO BIT(19) /* RW */
197 #define SDC_CFG_SDIOIDE BIT(20) /* RW */
198 #define SDC_CFG_INTATGAP BIT(21) /* RW */
199 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */
200
201 /* SDC_STS mask */
202 #define SDC_STS_SDCBUSY BIT(0) /* RW */
203 #define SDC_STS_CMDBUSY BIT(1) /* RW */
204 #define SDC_STS_SWR_COMPL BIT(31) /* RW */
205
206 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */
207 /* SDC_ADV_CFG0 mask */
208 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */
209
210 /* DMA_SA_H4BIT mask */
211 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */
212
213 /* MSDC_DMA_CTRL mask */
214 #define MSDC_DMA_CTRL_START BIT(0) /* W */
215 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */
216 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */
217 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */
218 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */
219 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */
220
221 /* MSDC_DMA_CFG mask */
222 #define MSDC_DMA_CFG_STS BIT(0) /* R */
223 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */
224 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */
225 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */
226 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */
227
228 /* MSDC_PATCH_BIT mask */
229 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */
230 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
231 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10)
232 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */
233 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */
234 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */
235 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */
236 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */
237 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */
238 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */
239 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */
240 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */
241
242 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */
243 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */
244 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */
245
246 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */
247 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */
248 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */
249 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */
250 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */
251 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */
252
253 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */
254 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */
255 #define MSDC_PAD_TUNE_DATRRDLY2 GENMASK(12, 8) /* RW */
256 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */
257 #define MSDC_PAD_TUNE_CMDRDLY2 GENMASK(20, 16) /* RW */
258 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */
259 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */
260 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */
261 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */
262 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */
263 #define MSDC_PAD_TUNE_RD2_SEL BIT(13) /* RW */
264 #define MSDC_PAD_TUNE_CMD2_SEL BIT(21) /* RW */
265
266 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */
267 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */
268 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */
269 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */
270
271 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */
272
273 /* EMMC51_CFG0 mask */
274 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */
275
276 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */
277 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */
278 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */
279 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */
280
281 /* EMMC50_CFG1 mask */
282 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
283
284 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
285
286 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
287 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
288
289 /* CQHCI_SETTING */
290 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */
291 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */
292
293 /* EMMC_TOP_CONTROL mask */
294 #define PAD_RXDLY_SEL BIT(0) /* RW */
295 #define DELAY_EN BIT(1) /* RW */
296 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */
297 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */
298 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */
299 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */
300 #define DATA_K_VALUE_SEL BIT(14) /* RW */
301 #define SDC_RX_ENH_EN BIT(15) /* TW */
302
303 /* EMMC_TOP_CMD mask */
304 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */
305 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */
306 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */
307 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */
308 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */
309
310 /* EMMC50_PAD_DS_TUNE mask */
311 #define PAD_DS_DLY_SEL BIT(16) /* RW */
312 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */
313 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */
314
315 #define REQ_CMD_EIO BIT(0)
316 #define REQ_CMD_TMO BIT(1)
317 #define REQ_DAT_ERR BIT(2)
318 #define REQ_STOP_EIO BIT(3)
319 #define REQ_STOP_TMO BIT(4)
320 #define REQ_CMD_BUSY BIT(5)
321
322 #define MSDC_PREPARE_FLAG BIT(0)
323 #define MSDC_ASYNC_FLAG BIT(1)
324 #define MSDC_MMAP_FLAG BIT(2)
325
326 #define MTK_MMC_AUTOSUSPEND_DELAY 50
327 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
328 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
329
330 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
331
332 #define TUNING_REG2_FIXED_OFFEST 4
333 #define PAD_DELAY_HALF 32 /* PAD delay cells */
334 #define PAD_DELAY_FULL 64
335 /*--------------------------------------------------------------------------*/
336 /* Descriptor Structure */
337 /*--------------------------------------------------------------------------*/
338 struct mt_gpdma_desc {
339 u32 gpd_info;
340 #define GPDMA_DESC_HWO BIT(0)
341 #define GPDMA_DESC_BDP BIT(1)
342 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8)
343 #define GPDMA_DESC_INT BIT(16)
344 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24)
345 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28)
346 u32 next;
347 u32 ptr;
348 u32 gpd_data_len;
349 #define GPDMA_DESC_BUFLEN GENMASK(15, 0)
350 #define GPDMA_DESC_EXTLEN GENMASK(23, 16)
351 u32 arg;
352 u32 blknum;
353 u32 cmd;
354 };
355
356 struct mt_bdma_desc {
357 u32 bd_info;
358 #define BDMA_DESC_EOL BIT(0)
359 #define BDMA_DESC_CHECKSUM GENMASK(15, 8)
360 #define BDMA_DESC_BLKPAD BIT(17)
361 #define BDMA_DESC_DWPAD BIT(18)
362 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24)
363 #define BDMA_DESC_PTR_H4 GENMASK(31, 28)
364 u32 next;
365 u32 ptr;
366 u32 bd_data_len;
367 #define BDMA_DESC_BUFLEN GENMASK(15, 0)
368 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0)
369 };
370
371 struct msdc_dma {
372 struct scatterlist *sg; /* I/O scatter list */
373 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
374 struct mt_bdma_desc *bd; /* pointer to bd array */
375 dma_addr_t gpd_addr; /* the physical address of gpd array */
376 dma_addr_t bd_addr; /* the physical address of bd array */
377 };
378
379 struct msdc_save_para {
380 u32 msdc_cfg;
381 u32 iocon;
382 u32 sdc_cfg;
383 u32 pad_tune;
384 u32 patch_bit0;
385 u32 patch_bit1;
386 u32 patch_bit2;
387 u32 pad_ds_tune;
388 u32 pad_cmd_tune;
389 u32 emmc50_cfg0;
390 u32 emmc50_cfg3;
391 u32 sdc_fifo_cfg;
392 u32 emmc_top_control;
393 u32 emmc_top_cmd;
394 u32 emmc50_pad_ds_tune;
395 };
396
397 struct mtk_mmc_compatible {
398 u8 clk_div_bits;
399 bool recheck_sdio_irq;
400 bool hs400_tune; /* only used for MT8173 */
401 u32 pad_tune_reg;
402 bool async_fifo;
403 bool data_tune;
404 bool busy_check;
405 bool stop_clk_fix;
406 bool enhance_rx;
407 bool support_64g;
408 bool use_internal_cd;
409 };
410
411 struct msdc_tune_para {
412 u32 iocon;
413 u32 pad_tune;
414 u32 pad_cmd_tune;
415 u32 emmc_top_control;
416 u32 emmc_top_cmd;
417 };
418
419 struct msdc_delay_phase {
420 u8 maxlen;
421 u8 start;
422 u8 final_phase;
423 };
424
425 struct msdc_host {
426 struct device *dev;
427 const struct mtk_mmc_compatible *dev_comp;
428 int cmd_rsp;
429
430 spinlock_t lock;
431 struct mmc_request *mrq;
432 struct mmc_command *cmd;
433 struct mmc_data *data;
434 int error;
435
436 void __iomem *base; /* host base address */
437 void __iomem *top_base; /* host top register base address */
438
439 struct msdc_dma dma; /* dma channel */
440 u64 dma_mask;
441
442 u32 timeout_ns; /* data timeout ns */
443 u32 timeout_clks; /* data timeout clks */
444
445 struct pinctrl *pinctrl;
446 struct pinctrl_state *pins_default;
447 struct pinctrl_state *pins_uhs;
448 struct pinctrl_state *pins_eint;
449 struct delayed_work req_timeout;
450 int irq; /* host interrupt */
451 int eint_irq; /* interrupt from sdio device for waking up system */
452 struct reset_control *reset;
453
454 struct clk *src_clk; /* msdc source clock */
455 struct clk *h_clk; /* msdc h_clk */
456 struct clk *bus_clk; /* bus clock which used to access register */
457 struct clk *src_clk_cg; /* msdc source clock control gate */
458 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
459 struct clk *crypto_clk; /* msdc crypto clock control gate */
460 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
461 u32 mclk; /* mmc subsystem clock frequency */
462 u32 src_clk_freq; /* source clock frequency */
463 unsigned char timing;
464 bool vqmmc_enabled;
465 u32 latch_ck;
466 u32 hs400_ds_delay;
467 u32 hs400_ds_dly3;
468 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
469 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
470 u32 tuning_step;
471 bool hs400_cmd_resp_sel_rising;
472 /* cmd response sample selection for HS400 */
473 bool hs400_mode; /* current eMMC will run at hs400 mode */
474 bool hs400_tuning; /* hs400 mode online tuning */
475 bool internal_cd; /* Use internal card-detect logic */
476 bool cqhci; /* support eMMC hw cmdq */
477 struct msdc_save_para save_para; /* used when gate HCLK */
478 struct msdc_tune_para def_tune_para; /* default tune setting */
479 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
480 struct cqhci_host *cq_host;
481 u32 cq_ssc1_time;
482 };
483
484 static const struct mtk_mmc_compatible mt2701_compat = {
485 .clk_div_bits = 12,
486 .recheck_sdio_irq = true,
487 .hs400_tune = false,
488 .pad_tune_reg = MSDC_PAD_TUNE0,
489 .async_fifo = true,
490 .data_tune = true,
491 .busy_check = false,
492 .stop_clk_fix = false,
493 .enhance_rx = false,
494 .support_64g = false,
495 };
496
497 static const struct mtk_mmc_compatible mt2712_compat = {
498 .clk_div_bits = 12,
499 .recheck_sdio_irq = false,
500 .hs400_tune = false,
501 .pad_tune_reg = MSDC_PAD_TUNE0,
502 .async_fifo = true,
503 .data_tune = true,
504 .busy_check = true,
505 .stop_clk_fix = true,
506 .enhance_rx = true,
507 .support_64g = true,
508 };
509
510 static const struct mtk_mmc_compatible mt6779_compat = {
511 .clk_div_bits = 12,
512 .recheck_sdio_irq = false,
513 .hs400_tune = false,
514 .pad_tune_reg = MSDC_PAD_TUNE0,
515 .async_fifo = true,
516 .data_tune = true,
517 .busy_check = true,
518 .stop_clk_fix = true,
519 .enhance_rx = true,
520 .support_64g = true,
521 };
522
523 static const struct mtk_mmc_compatible mt6795_compat = {
524 .clk_div_bits = 8,
525 .recheck_sdio_irq = false,
526 .hs400_tune = true,
527 .pad_tune_reg = MSDC_PAD_TUNE,
528 .async_fifo = false,
529 .data_tune = false,
530 .busy_check = false,
531 .stop_clk_fix = false,
532 .enhance_rx = false,
533 .support_64g = false,
534 };
535
536 static const struct mtk_mmc_compatible mt7620_compat = {
537 .clk_div_bits = 8,
538 .recheck_sdio_irq = true,
539 .hs400_tune = false,
540 .pad_tune_reg = MSDC_PAD_TUNE,
541 .async_fifo = false,
542 .data_tune = false,
543 .busy_check = false,
544 .stop_clk_fix = false,
545 .enhance_rx = false,
546 .use_internal_cd = true,
547 };
548
549 static const struct mtk_mmc_compatible mt7622_compat = {
550 .clk_div_bits = 12,
551 .recheck_sdio_irq = true,
552 .hs400_tune = false,
553 .pad_tune_reg = MSDC_PAD_TUNE0,
554 .async_fifo = true,
555 .data_tune = true,
556 .busy_check = true,
557 .stop_clk_fix = true,
558 .enhance_rx = true,
559 .support_64g = false,
560 };
561
562 static const struct mtk_mmc_compatible mt7986_compat = {
563 .clk_div_bits = 12,
564 .recheck_sdio_irq = true,
565 .hs400_tune = false,
566 .pad_tune_reg = MSDC_PAD_TUNE0,
567 .async_fifo = true,
568 .data_tune = true,
569 .busy_check = true,
570 .stop_clk_fix = true,
571 .enhance_rx = true,
572 .support_64g = true,
573 };
574
575 static const struct mtk_mmc_compatible mt8135_compat = {
576 .clk_div_bits = 8,
577 .recheck_sdio_irq = true,
578 .hs400_tune = false,
579 .pad_tune_reg = MSDC_PAD_TUNE,
580 .async_fifo = false,
581 .data_tune = false,
582 .busy_check = false,
583 .stop_clk_fix = false,
584 .enhance_rx = false,
585 .support_64g = false,
586 };
587
588 static const struct mtk_mmc_compatible mt8173_compat = {
589 .clk_div_bits = 8,
590 .recheck_sdio_irq = true,
591 .hs400_tune = true,
592 .pad_tune_reg = MSDC_PAD_TUNE,
593 .async_fifo = false,
594 .data_tune = false,
595 .busy_check = false,
596 .stop_clk_fix = false,
597 .enhance_rx = false,
598 .support_64g = false,
599 };
600
601 static const struct mtk_mmc_compatible mt8183_compat = {
602 .clk_div_bits = 12,
603 .recheck_sdio_irq = false,
604 .hs400_tune = false,
605 .pad_tune_reg = MSDC_PAD_TUNE0,
606 .async_fifo = true,
607 .data_tune = true,
608 .busy_check = true,
609 .stop_clk_fix = true,
610 .enhance_rx = true,
611 .support_64g = true,
612 };
613
614 static const struct mtk_mmc_compatible mt8516_compat = {
615 .clk_div_bits = 12,
616 .recheck_sdio_irq = true,
617 .hs400_tune = false,
618 .pad_tune_reg = MSDC_PAD_TUNE0,
619 .async_fifo = true,
620 .data_tune = true,
621 .busy_check = true,
622 .stop_clk_fix = true,
623 };
624
625 static const struct of_device_id msdc_of_ids[] = {
626 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
627 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
628 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
629 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
630 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
631 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
632 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
633 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
634 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
635 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
636 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
637
638 {}
639 };
640 MODULE_DEVICE_TABLE(of, msdc_of_ids);
641
sdr_set_bits(void __iomem * reg,u32 bs)642 static void sdr_set_bits(void __iomem *reg, u32 bs)
643 {
644 u32 val = readl(reg);
645
646 val |= bs;
647 writel(val, reg);
648 }
649
sdr_clr_bits(void __iomem * reg,u32 bs)650 static void sdr_clr_bits(void __iomem *reg, u32 bs)
651 {
652 u32 val = readl(reg);
653
654 val &= ~bs;
655 writel(val, reg);
656 }
657
sdr_set_field(void __iomem * reg,u32 field,u32 val)658 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
659 {
660 unsigned int tv = readl(reg);
661
662 tv &= ~field;
663 tv |= ((val) << (ffs((unsigned int)field) - 1));
664 writel(tv, reg);
665 }
666
sdr_get_field(void __iomem * reg,u32 field,u32 * val)667 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
668 {
669 unsigned int tv = readl(reg);
670
671 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
672 }
673
msdc_reset_hw(struct msdc_host * host)674 static void msdc_reset_hw(struct msdc_host *host)
675 {
676 u32 val;
677
678 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
679 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
680
681 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
682 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
683 !(val & MSDC_FIFOCS_CLR), 0, 0);
684
685 val = readl(host->base + MSDC_INT);
686 writel(val, host->base + MSDC_INT);
687 }
688
689 static void msdc_cmd_next(struct msdc_host *host,
690 struct mmc_request *mrq, struct mmc_command *cmd);
691 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
692
693 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
694 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
695 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
696 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
697 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
698 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
699
msdc_dma_calcs(u8 * buf,u32 len)700 static u8 msdc_dma_calcs(u8 *buf, u32 len)
701 {
702 u32 i, sum = 0;
703
704 for (i = 0; i < len; i++)
705 sum += buf[i];
706 return 0xff - (u8) sum;
707 }
708
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)709 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
710 struct mmc_data *data)
711 {
712 unsigned int j, dma_len;
713 dma_addr_t dma_address;
714 u32 dma_ctrl;
715 struct scatterlist *sg;
716 struct mt_gpdma_desc *gpd;
717 struct mt_bdma_desc *bd;
718
719 sg = data->sg;
720
721 gpd = dma->gpd;
722 bd = dma->bd;
723
724 /* modify gpd */
725 gpd->gpd_info |= GPDMA_DESC_HWO;
726 gpd->gpd_info |= GPDMA_DESC_BDP;
727 /* need to clear first. use these bits to calc checksum */
728 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
729 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
730
731 /* modify bd */
732 for_each_sg(data->sg, sg, data->sg_count, j) {
733 dma_address = sg_dma_address(sg);
734 dma_len = sg_dma_len(sg);
735
736 /* init bd */
737 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
738 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
739 bd[j].ptr = lower_32_bits(dma_address);
740 if (host->dev_comp->support_64g) {
741 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
742 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
743 << 28;
744 }
745
746 if (host->dev_comp->support_64g) {
747 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
748 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
749 } else {
750 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
751 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
752 }
753
754 if (j == data->sg_count - 1) /* the last bd */
755 bd[j].bd_info |= BDMA_DESC_EOL;
756 else
757 bd[j].bd_info &= ~BDMA_DESC_EOL;
758
759 /* checksum need to clear first */
760 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
761 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
762 }
763
764 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
765 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
766 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
767 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
768 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
769 if (host->dev_comp->support_64g)
770 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
771 upper_32_bits(dma->gpd_addr) & 0xf);
772 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
773 }
774
msdc_prepare_data(struct msdc_host * host,struct mmc_data * data)775 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
776 {
777 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
778 data->host_cookie |= MSDC_PREPARE_FLAG;
779 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
780 mmc_get_dma_dir(data));
781 }
782 }
783
msdc_unprepare_data(struct msdc_host * host,struct mmc_data * data)784 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
785 {
786 if (data->host_cookie & MSDC_ASYNC_FLAG)
787 return;
788
789 if (data->host_cookie & MSDC_PREPARE_FLAG) {
790 dma_unmap_sg(host->dev, data->sg, data->sg_len,
791 mmc_get_dma_dir(data));
792 data->host_cookie &= ~MSDC_PREPARE_FLAG;
793 }
794 }
795
msdc_timeout_cal(struct msdc_host * host,u64 ns,u64 clks)796 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
797 {
798 struct mmc_host *mmc = mmc_from_priv(host);
799 u64 timeout, clk_ns;
800 u32 mode = 0;
801
802 if (mmc->actual_clock == 0) {
803 timeout = 0;
804 } else {
805 clk_ns = 1000000000ULL;
806 do_div(clk_ns, mmc->actual_clock);
807 timeout = ns + clk_ns - 1;
808 do_div(timeout, clk_ns);
809 timeout += clks;
810 /* in 1048576 sclk cycle unit */
811 timeout = DIV_ROUND_UP(timeout, BIT(20));
812 if (host->dev_comp->clk_div_bits == 8)
813 sdr_get_field(host->base + MSDC_CFG,
814 MSDC_CFG_CKMOD, &mode);
815 else
816 sdr_get_field(host->base + MSDC_CFG,
817 MSDC_CFG_CKMOD_EXTRA, &mode);
818 /*DDR mode will double the clk cycles for data timeout */
819 timeout = mode >= 2 ? timeout * 2 : timeout;
820 timeout = timeout > 1 ? timeout - 1 : 0;
821 }
822 return timeout;
823 }
824
825 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u64 ns,u64 clks)826 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
827 {
828 u64 timeout;
829
830 host->timeout_ns = ns;
831 host->timeout_clks = clks;
832
833 timeout = msdc_timeout_cal(host, ns, clks);
834 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
835 (u32)(timeout > 255 ? 255 : timeout));
836 }
837
msdc_set_busy_timeout(struct msdc_host * host,u64 ns,u64 clks)838 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
839 {
840 u64 timeout;
841
842 timeout = msdc_timeout_cal(host, ns, clks);
843 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
844 (u32)(timeout > 8191 ? 8191 : timeout));
845 }
846
msdc_gate_clock(struct msdc_host * host)847 static void msdc_gate_clock(struct msdc_host *host)
848 {
849 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
850 clk_disable_unprepare(host->crypto_clk);
851 clk_disable_unprepare(host->src_clk_cg);
852 clk_disable_unprepare(host->src_clk);
853 clk_disable_unprepare(host->bus_clk);
854 clk_disable_unprepare(host->h_clk);
855 }
856
msdc_ungate_clock(struct msdc_host * host)857 static int msdc_ungate_clock(struct msdc_host *host)
858 {
859 u32 val;
860 int ret;
861
862 clk_prepare_enable(host->h_clk);
863 clk_prepare_enable(host->bus_clk);
864 clk_prepare_enable(host->src_clk);
865 clk_prepare_enable(host->src_clk_cg);
866 clk_prepare_enable(host->crypto_clk);
867 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
868 if (ret) {
869 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
870 return ret;
871 }
872
873 return readl_poll_timeout(host->base + MSDC_CFG, val,
874 (val & MSDC_CFG_CKSTB), 1, 20000);
875 }
876
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)877 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
878 {
879 struct mmc_host *mmc = mmc_from_priv(host);
880 u32 mode;
881 u32 flags;
882 u32 div;
883 u32 sclk;
884 u32 tune_reg = host->dev_comp->pad_tune_reg;
885 u32 val;
886
887 if (!hz) {
888 dev_dbg(host->dev, "set mclk to 0\n");
889 host->mclk = 0;
890 mmc->actual_clock = 0;
891 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
892 return;
893 }
894
895 flags = readl(host->base + MSDC_INTEN);
896 sdr_clr_bits(host->base + MSDC_INTEN, flags);
897 if (host->dev_comp->clk_div_bits == 8)
898 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
899 else
900 sdr_clr_bits(host->base + MSDC_CFG,
901 MSDC_CFG_HS400_CK_MODE_EXTRA);
902 if (timing == MMC_TIMING_UHS_DDR50 ||
903 timing == MMC_TIMING_MMC_DDR52 ||
904 timing == MMC_TIMING_MMC_HS400) {
905 if (timing == MMC_TIMING_MMC_HS400)
906 mode = 0x3;
907 else
908 mode = 0x2; /* ddr mode and use divisor */
909
910 if (hz >= (host->src_clk_freq >> 2)) {
911 div = 0; /* mean div = 1/4 */
912 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
913 } else {
914 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
915 sclk = (host->src_clk_freq >> 2) / div;
916 div = (div >> 1);
917 }
918
919 if (timing == MMC_TIMING_MMC_HS400 &&
920 hz >= (host->src_clk_freq >> 1)) {
921 if (host->dev_comp->clk_div_bits == 8)
922 sdr_set_bits(host->base + MSDC_CFG,
923 MSDC_CFG_HS400_CK_MODE);
924 else
925 sdr_set_bits(host->base + MSDC_CFG,
926 MSDC_CFG_HS400_CK_MODE_EXTRA);
927 sclk = host->src_clk_freq >> 1;
928 div = 0; /* div is ignore when bit18 is set */
929 }
930 } else if (hz >= host->src_clk_freq) {
931 mode = 0x1; /* no divisor */
932 div = 0;
933 sclk = host->src_clk_freq;
934 } else {
935 mode = 0x0; /* use divisor */
936 if (hz >= (host->src_clk_freq >> 1)) {
937 div = 0; /* mean div = 1/2 */
938 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
939 } else {
940 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
941 sclk = (host->src_clk_freq >> 2) / div;
942 }
943 }
944 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
945
946 clk_disable_unprepare(host->src_clk_cg);
947 if (host->dev_comp->clk_div_bits == 8)
948 sdr_set_field(host->base + MSDC_CFG,
949 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
950 (mode << 8) | div);
951 else
952 sdr_set_field(host->base + MSDC_CFG,
953 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
954 (mode << 12) | div);
955
956 clk_prepare_enable(host->src_clk_cg);
957 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
958 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
959 mmc->actual_clock = sclk;
960 host->mclk = hz;
961 host->timing = timing;
962 /* need because clk changed. */
963 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
964 sdr_set_bits(host->base + MSDC_INTEN, flags);
965
966 /*
967 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
968 * tune result of hs200/200Mhz is not suitable for 50Mhz
969 */
970 if (mmc->actual_clock <= 52000000) {
971 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
972 if (host->top_base) {
973 writel(host->def_tune_para.emmc_top_control,
974 host->top_base + EMMC_TOP_CONTROL);
975 writel(host->def_tune_para.emmc_top_cmd,
976 host->top_base + EMMC_TOP_CMD);
977 } else {
978 writel(host->def_tune_para.pad_tune,
979 host->base + tune_reg);
980 }
981 } else {
982 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
983 writel(host->saved_tune_para.pad_cmd_tune,
984 host->base + PAD_CMD_TUNE);
985 if (host->top_base) {
986 writel(host->saved_tune_para.emmc_top_control,
987 host->top_base + EMMC_TOP_CONTROL);
988 writel(host->saved_tune_para.emmc_top_cmd,
989 host->top_base + EMMC_TOP_CMD);
990 } else {
991 writel(host->saved_tune_para.pad_tune,
992 host->base + tune_reg);
993 }
994 }
995
996 if (timing == MMC_TIMING_MMC_HS400 &&
997 host->dev_comp->hs400_tune)
998 sdr_set_field(host->base + tune_reg,
999 MSDC_PAD_TUNE_CMDRRDLY,
1000 host->hs400_cmd_int_delay);
1001 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
1002 timing);
1003 }
1004
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_command * cmd)1005 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1006 struct mmc_command *cmd)
1007 {
1008 u32 resp;
1009
1010 switch (mmc_resp_type(cmd)) {
1011 /* Actually, R1, R5, R6, R7 are the same */
1012 case MMC_RSP_R1:
1013 resp = 0x1;
1014 break;
1015 case MMC_RSP_R1B:
1016 resp = 0x7;
1017 break;
1018 case MMC_RSP_R2:
1019 resp = 0x2;
1020 break;
1021 case MMC_RSP_R3:
1022 resp = 0x3;
1023 break;
1024 case MMC_RSP_NONE:
1025 default:
1026 resp = 0x0;
1027 break;
1028 }
1029
1030 return resp;
1031 }
1032
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1033 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1034 struct mmc_request *mrq, struct mmc_command *cmd)
1035 {
1036 struct mmc_host *mmc = mmc_from_priv(host);
1037 /* rawcmd :
1038 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1039 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1040 */
1041 u32 opcode = cmd->opcode;
1042 u32 resp = msdc_cmd_find_resp(host, cmd);
1043 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1044
1045 host->cmd_rsp = resp;
1046
1047 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1048 opcode == MMC_STOP_TRANSMISSION)
1049 rawcmd |= BIT(14);
1050 else if (opcode == SD_SWITCH_VOLTAGE)
1051 rawcmd |= BIT(30);
1052 else if (opcode == SD_APP_SEND_SCR ||
1053 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1054 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1055 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1056 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1057 rawcmd |= BIT(11);
1058
1059 if (cmd->data) {
1060 struct mmc_data *data = cmd->data;
1061
1062 if (mmc_op_multi(opcode)) {
1063 if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1064 !(mrq->sbc->arg & 0xFFFF0000))
1065 rawcmd |= BIT(29); /* AutoCMD23 */
1066 }
1067
1068 rawcmd |= ((data->blksz & 0xFFF) << 16);
1069 if (data->flags & MMC_DATA_WRITE)
1070 rawcmd |= BIT(13);
1071 if (data->blocks > 1)
1072 rawcmd |= BIT(12);
1073 else
1074 rawcmd |= BIT(11);
1075 /* Always use dma mode */
1076 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1077
1078 if (host->timeout_ns != data->timeout_ns ||
1079 host->timeout_clks != data->timeout_clks)
1080 msdc_set_timeout(host, data->timeout_ns,
1081 data->timeout_clks);
1082
1083 writel(data->blocks, host->base + SDC_BLK_NUM);
1084 }
1085 return rawcmd;
1086 }
1087
msdc_start_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)1088 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1089 struct mmc_data *data)
1090 {
1091 bool read;
1092
1093 WARN_ON(host->data);
1094 host->data = data;
1095 read = data->flags & MMC_DATA_READ;
1096
1097 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1098 msdc_dma_setup(host, &host->dma, data);
1099 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1100 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1101 dev_dbg(host->dev, "DMA start\n");
1102 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1103 __func__, cmd->opcode, data->blocks, read);
1104 }
1105
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)1106 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1107 struct mmc_command *cmd)
1108 {
1109 u32 *rsp = cmd->resp;
1110
1111 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1112
1113 if (events & MSDC_INT_ACMDRDY) {
1114 cmd->error = 0;
1115 } else {
1116 msdc_reset_hw(host);
1117 if (events & MSDC_INT_ACMDCRCERR) {
1118 cmd->error = -EILSEQ;
1119 host->error |= REQ_STOP_EIO;
1120 } else if (events & MSDC_INT_ACMDTMO) {
1121 cmd->error = -ETIMEDOUT;
1122 host->error |= REQ_STOP_TMO;
1123 }
1124 dev_err(host->dev,
1125 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1126 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1127 }
1128 return cmd->error;
1129 }
1130
1131 /*
1132 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1133 *
1134 * Host controller may lost interrupt in some special case.
1135 * Add SDIO irq recheck mechanism to make sure all interrupts
1136 * can be processed immediately
1137 */
msdc_recheck_sdio_irq(struct msdc_host * host)1138 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1139 {
1140 struct mmc_host *mmc = mmc_from_priv(host);
1141 u32 reg_int, reg_inten, reg_ps;
1142
1143 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1144 reg_inten = readl(host->base + MSDC_INTEN);
1145 if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1146 reg_int = readl(host->base + MSDC_INT);
1147 reg_ps = readl(host->base + MSDC_PS);
1148 if (!(reg_int & MSDC_INT_SDIOIRQ ||
1149 reg_ps & MSDC_PS_DATA1)) {
1150 __msdc_enable_sdio_irq(host, 0);
1151 sdio_signal_irq(mmc);
1152 }
1153 }
1154 }
1155 }
1156
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd)1157 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1158 {
1159 if (host->error &&
1160 ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) ||
1161 cmd->error == -ETIMEDOUT))
1162 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1163 __func__, cmd->opcode, cmd->arg, host->error);
1164 }
1165
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)1166 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1167 {
1168 unsigned long flags;
1169
1170 /*
1171 * No need check the return value of cancel_delayed_work, as only ONE
1172 * path will go here!
1173 */
1174 cancel_delayed_work(&host->req_timeout);
1175
1176 spin_lock_irqsave(&host->lock, flags);
1177 host->mrq = NULL;
1178 spin_unlock_irqrestore(&host->lock, flags);
1179
1180 msdc_track_cmd_data(host, mrq->cmd);
1181 if (mrq->data)
1182 msdc_unprepare_data(host, mrq->data);
1183 if (host->error)
1184 msdc_reset_hw(host);
1185 mmc_request_done(mmc_from_priv(host), mrq);
1186 if (host->dev_comp->recheck_sdio_irq)
1187 msdc_recheck_sdio_irq(host);
1188 }
1189
1190 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)1191 static bool msdc_cmd_done(struct msdc_host *host, int events,
1192 struct mmc_request *mrq, struct mmc_command *cmd)
1193 {
1194 bool done = false;
1195 bool sbc_error;
1196 unsigned long flags;
1197 u32 *rsp;
1198
1199 if (mrq->sbc && cmd == mrq->cmd &&
1200 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1201 | MSDC_INT_ACMDTMO)))
1202 msdc_auto_cmd_done(host, events, mrq->sbc);
1203
1204 sbc_error = mrq->sbc && mrq->sbc->error;
1205
1206 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1207 | MSDC_INT_RSPCRCERR
1208 | MSDC_INT_CMDTMO)))
1209 return done;
1210
1211 spin_lock_irqsave(&host->lock, flags);
1212 done = !host->cmd;
1213 host->cmd = NULL;
1214 spin_unlock_irqrestore(&host->lock, flags);
1215
1216 if (done)
1217 return true;
1218 rsp = cmd->resp;
1219
1220 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1221
1222 if (cmd->flags & MMC_RSP_PRESENT) {
1223 if (cmd->flags & MMC_RSP_136) {
1224 rsp[0] = readl(host->base + SDC_RESP3);
1225 rsp[1] = readl(host->base + SDC_RESP2);
1226 rsp[2] = readl(host->base + SDC_RESP1);
1227 rsp[3] = readl(host->base + SDC_RESP0);
1228 } else {
1229 rsp[0] = readl(host->base + SDC_RESP0);
1230 }
1231 }
1232
1233 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1234 if (events & MSDC_INT_CMDTMO ||
1235 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1236 /*
1237 * should not clear fifo/interrupt as the tune data
1238 * may have already come when cmd19/cmd21 gets response
1239 * CRC error.
1240 */
1241 msdc_reset_hw(host);
1242 if (events & MSDC_INT_RSPCRCERR) {
1243 cmd->error = -EILSEQ;
1244 host->error |= REQ_CMD_EIO;
1245 } else if (events & MSDC_INT_CMDTMO) {
1246 cmd->error = -ETIMEDOUT;
1247 host->error |= REQ_CMD_TMO;
1248 }
1249 }
1250 if (cmd->error)
1251 dev_dbg(host->dev,
1252 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1253 __func__, cmd->opcode, cmd->arg, rsp[0],
1254 cmd->error);
1255
1256 msdc_cmd_next(host, mrq, cmd);
1257 return true;
1258 }
1259
1260 /* It is the core layer's responsibility to ensure card status
1261 * is correct before issue a request. but host design do below
1262 * checks recommended.
1263 */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1264 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1265 struct mmc_request *mrq, struct mmc_command *cmd)
1266 {
1267 u32 val;
1268 int ret;
1269
1270 /* The max busy time we can endure is 20ms */
1271 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1272 !(val & SDC_STS_CMDBUSY), 1, 20000);
1273 if (ret) {
1274 dev_err(host->dev, "CMD bus busy detected\n");
1275 host->error |= REQ_CMD_BUSY;
1276 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1277 return false;
1278 }
1279
1280 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1281 /* R1B or with data, should check SDCBUSY */
1282 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1283 !(val & SDC_STS_SDCBUSY), 1, 20000);
1284 if (ret) {
1285 dev_err(host->dev, "Controller busy detected\n");
1286 host->error |= REQ_CMD_BUSY;
1287 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1288 return false;
1289 }
1290 }
1291 return true;
1292 }
1293
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1294 static void msdc_start_command(struct msdc_host *host,
1295 struct mmc_request *mrq, struct mmc_command *cmd)
1296 {
1297 u32 rawcmd;
1298 unsigned long flags;
1299
1300 WARN_ON(host->cmd);
1301 host->cmd = cmd;
1302
1303 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1304 if (!msdc_cmd_is_ready(host, mrq, cmd))
1305 return;
1306
1307 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1308 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1309 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1310 msdc_reset_hw(host);
1311 }
1312
1313 cmd->error = 0;
1314 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1315
1316 spin_lock_irqsave(&host->lock, flags);
1317 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1318 spin_unlock_irqrestore(&host->lock, flags);
1319
1320 writel(cmd->arg, host->base + SDC_ARG);
1321 writel(rawcmd, host->base + SDC_CMD);
1322 }
1323
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1324 static void msdc_cmd_next(struct msdc_host *host,
1325 struct mmc_request *mrq, struct mmc_command *cmd)
1326 {
1327 if ((cmd->error &&
1328 !(cmd->error == -EILSEQ &&
1329 (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) ||
1330 (mrq->sbc && mrq->sbc->error))
1331 msdc_request_done(host, mrq);
1332 else if (cmd == mrq->sbc)
1333 msdc_start_command(host, mrq, mrq->cmd);
1334 else if (!cmd->data)
1335 msdc_request_done(host, mrq);
1336 else
1337 msdc_start_data(host, cmd, cmd->data);
1338 }
1339
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1340 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1341 {
1342 struct msdc_host *host = mmc_priv(mmc);
1343
1344 host->error = 0;
1345 WARN_ON(host->mrq);
1346 host->mrq = mrq;
1347
1348 if (mrq->data)
1349 msdc_prepare_data(host, mrq->data);
1350
1351 /* if SBC is required, we have HW option and SW option.
1352 * if HW option is enabled, and SBC does not have "special" flags,
1353 * use HW option, otherwise use SW option
1354 */
1355 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1356 (mrq->sbc->arg & 0xFFFF0000)))
1357 msdc_start_command(host, mrq, mrq->sbc);
1358 else
1359 msdc_start_command(host, mrq, mrq->cmd);
1360 }
1361
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1362 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1363 {
1364 struct msdc_host *host = mmc_priv(mmc);
1365 struct mmc_data *data = mrq->data;
1366
1367 if (!data)
1368 return;
1369
1370 msdc_prepare_data(host, data);
1371 data->host_cookie |= MSDC_ASYNC_FLAG;
1372 }
1373
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1374 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1375 int err)
1376 {
1377 struct msdc_host *host = mmc_priv(mmc);
1378 struct mmc_data *data = mrq->data;
1379
1380 if (!data)
1381 return;
1382
1383 if (data->host_cookie) {
1384 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1385 msdc_unprepare_data(host, data);
1386 }
1387 }
1388
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq)1389 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1390 {
1391 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1392 !mrq->sbc)
1393 msdc_start_command(host, mrq, mrq->stop);
1394 else
1395 msdc_request_done(host, mrq);
1396 }
1397
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)1398 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1399 struct mmc_request *mrq, struct mmc_data *data)
1400 {
1401 struct mmc_command *stop;
1402 unsigned long flags;
1403 bool done;
1404 unsigned int check_data = events &
1405 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1406 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1407 | MSDC_INT_DMA_PROTECT);
1408 u32 val;
1409 int ret;
1410
1411 spin_lock_irqsave(&host->lock, flags);
1412 done = !host->data;
1413 if (check_data)
1414 host->data = NULL;
1415 spin_unlock_irqrestore(&host->lock, flags);
1416
1417 if (done)
1418 return;
1419 stop = data->stop;
1420
1421 if (check_data || (stop && stop->error)) {
1422 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1423 readl(host->base + MSDC_DMA_CFG));
1424 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1425 1);
1426
1427 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1428 !(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1429 if (ret)
1430 dev_dbg(host->dev, "DMA stop timed out\n");
1431
1432 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1433 !(val & MSDC_DMA_CFG_STS), 1, 20000);
1434 if (ret)
1435 dev_dbg(host->dev, "DMA inactive timed out\n");
1436
1437 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1438 dev_dbg(host->dev, "DMA stop\n");
1439
1440 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1441 data->bytes_xfered = data->blocks * data->blksz;
1442 } else {
1443 dev_dbg(host->dev, "interrupt events: %x\n", events);
1444 msdc_reset_hw(host);
1445 host->error |= REQ_DAT_ERR;
1446 data->bytes_xfered = 0;
1447
1448 if (events & MSDC_INT_DATTMO)
1449 data->error = -ETIMEDOUT;
1450 else if (events & MSDC_INT_DATCRCERR)
1451 data->error = -EILSEQ;
1452
1453 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1454 __func__, mrq->cmd->opcode, data->blocks);
1455 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1456 (int)data->error, data->bytes_xfered);
1457 }
1458
1459 msdc_data_xfer_next(host, mrq);
1460 }
1461 }
1462
msdc_set_buswidth(struct msdc_host * host,u32 width)1463 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1464 {
1465 u32 val = readl(host->base + SDC_CFG);
1466
1467 val &= ~SDC_CFG_BUSWIDTH;
1468
1469 switch (width) {
1470 default:
1471 case MMC_BUS_WIDTH_1:
1472 val |= (MSDC_BUS_1BITS << 16);
1473 break;
1474 case MMC_BUS_WIDTH_4:
1475 val |= (MSDC_BUS_4BITS << 16);
1476 break;
1477 case MMC_BUS_WIDTH_8:
1478 val |= (MSDC_BUS_8BITS << 16);
1479 break;
1480 }
1481
1482 writel(val, host->base + SDC_CFG);
1483 dev_dbg(host->dev, "Bus Width = %d", width);
1484 }
1485
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1486 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1487 {
1488 struct msdc_host *host = mmc_priv(mmc);
1489 int ret;
1490
1491 if (!IS_ERR(mmc->supply.vqmmc)) {
1492 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1493 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1494 dev_err(host->dev, "Unsupported signal voltage!\n");
1495 return -EINVAL;
1496 }
1497
1498 ret = mmc_regulator_set_vqmmc(mmc, ios);
1499 if (ret < 0) {
1500 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1501 ret, ios->signal_voltage);
1502 return ret;
1503 }
1504
1505 /* Apply different pinctrl settings for different signal voltage */
1506 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1507 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1508 else
1509 pinctrl_select_state(host->pinctrl, host->pins_default);
1510 }
1511 return 0;
1512 }
1513
msdc_card_busy(struct mmc_host * mmc)1514 static int msdc_card_busy(struct mmc_host *mmc)
1515 {
1516 struct msdc_host *host = mmc_priv(mmc);
1517 u32 status = readl(host->base + MSDC_PS);
1518
1519 /* only check if data0 is low */
1520 return !(status & BIT(16));
1521 }
1522
msdc_request_timeout(struct work_struct * work)1523 static void msdc_request_timeout(struct work_struct *work)
1524 {
1525 struct msdc_host *host = container_of(work, struct msdc_host,
1526 req_timeout.work);
1527
1528 /* simulate HW timeout status */
1529 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1530 if (host->mrq) {
1531 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1532 host->mrq, host->mrq->cmd->opcode);
1533 if (host->cmd) {
1534 dev_err(host->dev, "%s: aborting cmd=%d\n",
1535 __func__, host->cmd->opcode);
1536 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1537 host->cmd);
1538 } else if (host->data) {
1539 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1540 __func__, host->mrq->cmd->opcode,
1541 host->data->blocks);
1542 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1543 host->data);
1544 }
1545 }
1546 }
1547
__msdc_enable_sdio_irq(struct msdc_host * host,int enb)1548 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1549 {
1550 if (enb) {
1551 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1552 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1553 if (host->dev_comp->recheck_sdio_irq)
1554 msdc_recheck_sdio_irq(host);
1555 } else {
1556 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1557 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1558 }
1559 }
1560
msdc_enable_sdio_irq(struct mmc_host * mmc,int enb)1561 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1562 {
1563 struct msdc_host *host = mmc_priv(mmc);
1564 unsigned long flags;
1565 int ret;
1566
1567 spin_lock_irqsave(&host->lock, flags);
1568 __msdc_enable_sdio_irq(host, enb);
1569 spin_unlock_irqrestore(&host->lock, flags);
1570
1571 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1572 if (enb) {
1573 /*
1574 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1575 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1576 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1577 * affect successfully, we change the pinstate to pins_eint firstly.
1578 */
1579 pinctrl_select_state(host->pinctrl, host->pins_eint);
1580 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1581
1582 if (ret) {
1583 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1584 host->pins_eint = NULL;
1585 pm_runtime_get_noresume(host->dev);
1586 } else {
1587 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1588 }
1589
1590 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1591 } else {
1592 dev_pm_clear_wake_irq(host->dev);
1593 }
1594 } else {
1595 if (enb) {
1596 /* Ensure host->pins_eint is NULL */
1597 host->pins_eint = NULL;
1598 pm_runtime_get_noresume(host->dev);
1599 } else {
1600 pm_runtime_put_noidle(host->dev);
1601 }
1602 }
1603 }
1604
msdc_cmdq_irq(struct msdc_host * host,u32 intsts)1605 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1606 {
1607 struct mmc_host *mmc = mmc_from_priv(host);
1608 int cmd_err = 0, dat_err = 0;
1609
1610 if (intsts & MSDC_INT_RSPCRCERR) {
1611 cmd_err = -EILSEQ;
1612 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1613 } else if (intsts & MSDC_INT_CMDTMO) {
1614 cmd_err = -ETIMEDOUT;
1615 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1616 }
1617
1618 if (intsts & MSDC_INT_DATCRCERR) {
1619 dat_err = -EILSEQ;
1620 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1621 } else if (intsts & MSDC_INT_DATTMO) {
1622 dat_err = -ETIMEDOUT;
1623 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1624 }
1625
1626 if (cmd_err || dat_err) {
1627 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x",
1628 cmd_err, dat_err, intsts);
1629 }
1630
1631 return cqhci_irq(mmc, 0, cmd_err, dat_err);
1632 }
1633
msdc_irq(int irq,void * dev_id)1634 static irqreturn_t msdc_irq(int irq, void *dev_id)
1635 {
1636 struct msdc_host *host = (struct msdc_host *) dev_id;
1637 struct mmc_host *mmc = mmc_from_priv(host);
1638
1639 while (true) {
1640 struct mmc_request *mrq;
1641 struct mmc_command *cmd;
1642 struct mmc_data *data;
1643 u32 events, event_mask;
1644
1645 spin_lock(&host->lock);
1646 events = readl(host->base + MSDC_INT);
1647 event_mask = readl(host->base + MSDC_INTEN);
1648 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1649 __msdc_enable_sdio_irq(host, 0);
1650 /* clear interrupts */
1651 writel(events & event_mask, host->base + MSDC_INT);
1652
1653 mrq = host->mrq;
1654 cmd = host->cmd;
1655 data = host->data;
1656 spin_unlock(&host->lock);
1657
1658 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1659 sdio_signal_irq(mmc);
1660
1661 if ((events & event_mask) & MSDC_INT_CDSC) {
1662 if (host->internal_cd)
1663 mmc_detect_change(mmc, msecs_to_jiffies(20));
1664 events &= ~MSDC_INT_CDSC;
1665 }
1666
1667 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1668 break;
1669
1670 if ((mmc->caps2 & MMC_CAP2_CQE) &&
1671 (events & MSDC_INT_CMDQ)) {
1672 msdc_cmdq_irq(host, events);
1673 /* clear interrupts */
1674 writel(events, host->base + MSDC_INT);
1675 return IRQ_HANDLED;
1676 }
1677
1678 if (!mrq) {
1679 dev_err(host->dev,
1680 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1681 __func__, events, event_mask);
1682 WARN_ON(1);
1683 break;
1684 }
1685
1686 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1687
1688 if (cmd)
1689 msdc_cmd_done(host, events, mrq, cmd);
1690 else if (data)
1691 msdc_data_xfer_done(host, events, mrq, data);
1692 }
1693
1694 return IRQ_HANDLED;
1695 }
1696
msdc_init_hw(struct msdc_host * host)1697 static void msdc_init_hw(struct msdc_host *host)
1698 {
1699 u32 val;
1700 u32 tune_reg = host->dev_comp->pad_tune_reg;
1701 struct mmc_host *mmc = mmc_from_priv(host);
1702
1703 if (host->reset) {
1704 reset_control_assert(host->reset);
1705 usleep_range(10, 50);
1706 reset_control_deassert(host->reset);
1707 }
1708
1709 /* Configure to MMC/SD mode, clock free running */
1710 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1711
1712 /* Reset */
1713 msdc_reset_hw(host);
1714
1715 /* Disable and clear all interrupts */
1716 writel(0, host->base + MSDC_INTEN);
1717 val = readl(host->base + MSDC_INT);
1718 writel(val, host->base + MSDC_INT);
1719
1720 /* Configure card detection */
1721 if (host->internal_cd) {
1722 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1723 DEFAULT_DEBOUNCE);
1724 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1725 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1726 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1727 } else {
1728 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1729 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1730 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1731 }
1732
1733 if (host->top_base) {
1734 writel(0, host->top_base + EMMC_TOP_CONTROL);
1735 writel(0, host->top_base + EMMC_TOP_CMD);
1736 } else {
1737 writel(0, host->base + tune_reg);
1738 }
1739 writel(0, host->base + MSDC_IOCON);
1740 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1741 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1742 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1743 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1744 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1745
1746 if (host->dev_comp->stop_clk_fix) {
1747 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1748 MSDC_PATCH_BIT1_STOP_DLY, 3);
1749 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1750 SDC_FIFO_CFG_WRVALIDSEL);
1751 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1752 SDC_FIFO_CFG_RDVALIDSEL);
1753 }
1754
1755 if (host->dev_comp->busy_check)
1756 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1757
1758 if (host->dev_comp->async_fifo) {
1759 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1760 MSDC_PB2_RESPWAIT, 3);
1761 if (host->dev_comp->enhance_rx) {
1762 if (host->top_base)
1763 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1764 SDC_RX_ENH_EN);
1765 else
1766 sdr_set_bits(host->base + SDC_ADV_CFG0,
1767 SDC_RX_ENHANCE_EN);
1768 } else {
1769 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1770 MSDC_PB2_RESPSTSENSEL, 2);
1771 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1772 MSDC_PB2_CRCSTSENSEL, 2);
1773 }
1774 /* use async fifo, then no need tune internal delay */
1775 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1776 MSDC_PATCH_BIT2_CFGRESP);
1777 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1778 MSDC_PATCH_BIT2_CFGCRCSTS);
1779 }
1780
1781 if (host->dev_comp->support_64g)
1782 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1783 MSDC_PB2_SUPPORT_64G);
1784 if (host->dev_comp->data_tune) {
1785 if (host->top_base) {
1786 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1787 PAD_DAT_RD_RXDLY_SEL);
1788 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1789 DATA_K_VALUE_SEL);
1790 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1791 PAD_CMD_RD_RXDLY_SEL);
1792 if (host->tuning_step > PAD_DELAY_HALF) {
1793 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1794 PAD_DAT_RD_RXDLY2_SEL);
1795 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1796 PAD_CMD_RD_RXDLY2_SEL);
1797 }
1798 } else {
1799 sdr_set_bits(host->base + tune_reg,
1800 MSDC_PAD_TUNE_RD_SEL |
1801 MSDC_PAD_TUNE_CMD_SEL);
1802 if (host->tuning_step > PAD_DELAY_HALF)
1803 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
1804 MSDC_PAD_TUNE_RD2_SEL |
1805 MSDC_PAD_TUNE_CMD2_SEL);
1806 }
1807 } else {
1808 /* choose clock tune */
1809 if (host->top_base)
1810 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1811 PAD_RXDLY_SEL);
1812 else
1813 sdr_set_bits(host->base + tune_reg,
1814 MSDC_PAD_TUNE_RXDLYSEL);
1815 }
1816
1817 if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1818 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1819 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1820 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1821 } else {
1822 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1823 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1824
1825 /* Config SDIO device detect interrupt function */
1826 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1827 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1828 }
1829
1830 /* Configure to default data timeout */
1831 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1832
1833 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1834 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1835 if (host->top_base) {
1836 host->def_tune_para.emmc_top_control =
1837 readl(host->top_base + EMMC_TOP_CONTROL);
1838 host->def_tune_para.emmc_top_cmd =
1839 readl(host->top_base + EMMC_TOP_CMD);
1840 host->saved_tune_para.emmc_top_control =
1841 readl(host->top_base + EMMC_TOP_CONTROL);
1842 host->saved_tune_para.emmc_top_cmd =
1843 readl(host->top_base + EMMC_TOP_CMD);
1844 } else {
1845 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1846 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1847 }
1848 dev_dbg(host->dev, "init hardware done!");
1849 }
1850
msdc_deinit_hw(struct msdc_host * host)1851 static void msdc_deinit_hw(struct msdc_host *host)
1852 {
1853 u32 val;
1854
1855 if (host->internal_cd) {
1856 /* Disabled card-detect */
1857 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1858 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1859 }
1860
1861 /* Disable and clear all interrupts */
1862 writel(0, host->base + MSDC_INTEN);
1863
1864 val = readl(host->base + MSDC_INT);
1865 writel(val, host->base + MSDC_INT);
1866 }
1867
1868 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)1869 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1870 {
1871 struct mt_gpdma_desc *gpd = dma->gpd;
1872 struct mt_bdma_desc *bd = dma->bd;
1873 dma_addr_t dma_addr;
1874 int i;
1875
1876 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1877
1878 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1879 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1880 /* gpd->next is must set for desc DMA
1881 * That's why must alloc 2 gpd structure.
1882 */
1883 gpd->next = lower_32_bits(dma_addr);
1884 if (host->dev_comp->support_64g)
1885 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1886
1887 dma_addr = dma->bd_addr;
1888 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1889 if (host->dev_comp->support_64g)
1890 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1891
1892 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1893 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1894 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1895 bd[i].next = lower_32_bits(dma_addr);
1896 if (host->dev_comp->support_64g)
1897 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1898 }
1899 }
1900
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1901 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1902 {
1903 struct msdc_host *host = mmc_priv(mmc);
1904 int ret;
1905
1906 msdc_set_buswidth(host, ios->bus_width);
1907
1908 /* Suspend/Resume will do power off/on */
1909 switch (ios->power_mode) {
1910 case MMC_POWER_UP:
1911 if (!IS_ERR(mmc->supply.vmmc)) {
1912 msdc_init_hw(host);
1913 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1914 ios->vdd);
1915 if (ret) {
1916 dev_err(host->dev, "Failed to set vmmc power!\n");
1917 return;
1918 }
1919 }
1920 break;
1921 case MMC_POWER_ON:
1922 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1923 ret = regulator_enable(mmc->supply.vqmmc);
1924 if (ret)
1925 dev_err(host->dev, "Failed to set vqmmc power!\n");
1926 else
1927 host->vqmmc_enabled = true;
1928 }
1929 break;
1930 case MMC_POWER_OFF:
1931 if (!IS_ERR(mmc->supply.vmmc))
1932 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1933
1934 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1935 regulator_disable(mmc->supply.vqmmc);
1936 host->vqmmc_enabled = false;
1937 }
1938 break;
1939 default:
1940 break;
1941 }
1942
1943 if (host->mclk != ios->clock || host->timing != ios->timing)
1944 msdc_set_mclk(host, ios->timing, ios->clock);
1945 }
1946
test_delay_bit(u64 delay,u32 bit)1947 static u64 test_delay_bit(u64 delay, u32 bit)
1948 {
1949 bit %= PAD_DELAY_FULL;
1950 return delay & BIT_ULL(bit);
1951 }
1952
get_delay_len(u64 delay,u32 start_bit)1953 static int get_delay_len(u64 delay, u32 start_bit)
1954 {
1955 int i;
1956
1957 for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) {
1958 if (test_delay_bit(delay, start_bit + i) == 0)
1959 return i;
1960 }
1961 return PAD_DELAY_FULL - start_bit;
1962 }
1963
get_best_delay(struct msdc_host * host,u64 delay)1964 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay)
1965 {
1966 int start = 0, len = 0;
1967 int start_final = 0, len_final = 0;
1968 u8 final_phase = 0xff;
1969 struct msdc_delay_phase delay_phase = { 0, };
1970
1971 if (delay == 0) {
1972 dev_err(host->dev, "phase error: [map:%016llx]\n", delay);
1973 delay_phase.final_phase = final_phase;
1974 return delay_phase;
1975 }
1976
1977 while (start < PAD_DELAY_FULL) {
1978 len = get_delay_len(delay, start);
1979 if (len_final < len) {
1980 start_final = start;
1981 len_final = len;
1982 }
1983 start += len ? len : 1;
1984 if (!upper_32_bits(delay) && len >= 12 && start_final < 4)
1985 break;
1986 }
1987
1988 /* The rule is that to find the smallest delay cell */
1989 if (start_final == 0)
1990 final_phase = (start_final + len_final / 3) % PAD_DELAY_FULL;
1991 else
1992 final_phase = (start_final + len_final / 2) % PAD_DELAY_FULL;
1993 dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n",
1994 delay, len_final, final_phase);
1995
1996 delay_phase.maxlen = len_final;
1997 delay_phase.start = start_final;
1998 delay_phase.final_phase = final_phase;
1999 return delay_phase;
2000 }
2001
msdc_set_cmd_delay(struct msdc_host * host,u32 value)2002 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
2003 {
2004 u32 tune_reg = host->dev_comp->pad_tune_reg;
2005
2006 if (host->top_base) {
2007 if (value < PAD_DELAY_HALF) {
2008 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value);
2009 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0);
2010 } else {
2011 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
2012 PAD_DELAY_HALF - 1);
2013 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2,
2014 value - PAD_DELAY_HALF);
2015 }
2016 } else {
2017 if (value < PAD_DELAY_HALF) {
2018 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value);
2019 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2020 MSDC_PAD_TUNE_CMDRDLY2, 0);
2021 } else {
2022 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2023 PAD_DELAY_HALF - 1);
2024 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2025 MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF);
2026 }
2027 }
2028 }
2029
msdc_set_data_delay(struct msdc_host * host,u32 value)2030 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
2031 {
2032 u32 tune_reg = host->dev_comp->pad_tune_reg;
2033
2034 if (host->top_base) {
2035 if (value < PAD_DELAY_HALF) {
2036 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2037 PAD_DAT_RD_RXDLY, value);
2038 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2039 PAD_DAT_RD_RXDLY2, 0);
2040 } else {
2041 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2042 PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1);
2043 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2044 PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF);
2045 }
2046 } else {
2047 if (value < PAD_DELAY_HALF) {
2048 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);
2049 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2050 MSDC_PAD_TUNE_DATRRDLY2, 0);
2051 } else {
2052 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2053 PAD_DELAY_HALF - 1);
2054 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2055 MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF);
2056 }
2057 }
2058 }
2059
msdc_tune_response(struct mmc_host * mmc,u32 opcode)2060 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2061 {
2062 struct msdc_host *host = mmc_priv(mmc);
2063 u64 rise_delay = 0, fall_delay = 0;
2064 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2065 struct msdc_delay_phase internal_delay_phase;
2066 u8 final_delay, final_maxlen;
2067 u32 internal_delay = 0;
2068 u32 tune_reg = host->dev_comp->pad_tune_reg;
2069 int cmd_err;
2070 int i, j;
2071
2072 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2073 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2074 sdr_set_field(host->base + tune_reg,
2075 MSDC_PAD_TUNE_CMDRRDLY,
2076 host->hs200_cmd_int_delay);
2077
2078 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2079 for (i = 0; i < host->tuning_step; i++) {
2080 msdc_set_cmd_delay(host, i);
2081 /*
2082 * Using the same parameters, it may sometimes pass the test,
2083 * but sometimes it may fail. To make sure the parameters are
2084 * more stable, we test each set of parameters 3 times.
2085 */
2086 for (j = 0; j < 3; j++) {
2087 mmc_send_tuning(mmc, opcode, &cmd_err);
2088 if (!cmd_err) {
2089 rise_delay |= BIT_ULL(i);
2090 } else {
2091 rise_delay &= ~BIT_ULL(i);
2092 break;
2093 }
2094 }
2095 }
2096 final_rise_delay = get_best_delay(host, rise_delay);
2097 /* if rising edge has enough margin, then do not scan falling edge */
2098 if (final_rise_delay.maxlen >= 12 ||
2099 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2100 goto skip_fall;
2101
2102 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2103 for (i = 0; i < host->tuning_step; i++) {
2104 msdc_set_cmd_delay(host, i);
2105 /*
2106 * Using the same parameters, it may sometimes pass the test,
2107 * but sometimes it may fail. To make sure the parameters are
2108 * more stable, we test each set of parameters 3 times.
2109 */
2110 for (j = 0; j < 3; j++) {
2111 mmc_send_tuning(mmc, opcode, &cmd_err);
2112 if (!cmd_err) {
2113 fall_delay |= BIT_ULL(i);
2114 } else {
2115 fall_delay &= ~BIT_ULL(i);
2116 break;
2117 }
2118 }
2119 }
2120 final_fall_delay = get_best_delay(host, fall_delay);
2121
2122 skip_fall:
2123 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2124 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2125 final_maxlen = final_fall_delay.maxlen;
2126 if (final_maxlen == final_rise_delay.maxlen) {
2127 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2128 final_delay = final_rise_delay.final_phase;
2129 } else {
2130 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2131 final_delay = final_fall_delay.final_phase;
2132 }
2133 msdc_set_cmd_delay(host, final_delay);
2134
2135 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2136 goto skip_internal;
2137
2138 for (i = 0; i < host->tuning_step; i++) {
2139 sdr_set_field(host->base + tune_reg,
2140 MSDC_PAD_TUNE_CMDRRDLY, i);
2141 mmc_send_tuning(mmc, opcode, &cmd_err);
2142 if (!cmd_err)
2143 internal_delay |= BIT_ULL(i);
2144 }
2145 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2146 internal_delay_phase = get_best_delay(host, internal_delay);
2147 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2148 internal_delay_phase.final_phase);
2149 skip_internal:
2150 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2151 return final_delay == 0xff ? -EIO : 0;
2152 }
2153
hs400_tune_response(struct mmc_host * mmc,u32 opcode)2154 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2155 {
2156 struct msdc_host *host = mmc_priv(mmc);
2157 u32 cmd_delay = 0;
2158 struct msdc_delay_phase final_cmd_delay = { 0,};
2159 u8 final_delay;
2160 int cmd_err;
2161 int i, j;
2162
2163 /* select EMMC50 PAD CMD tune */
2164 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2165 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2166
2167 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2168 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2169 sdr_set_field(host->base + MSDC_PAD_TUNE,
2170 MSDC_PAD_TUNE_CMDRRDLY,
2171 host->hs200_cmd_int_delay);
2172
2173 if (host->hs400_cmd_resp_sel_rising)
2174 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2175 else
2176 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2177
2178 for (i = 0; i < PAD_DELAY_HALF; i++) {
2179 sdr_set_field(host->base + PAD_CMD_TUNE,
2180 PAD_CMD_TUNE_RX_DLY3, i);
2181 /*
2182 * Using the same parameters, it may sometimes pass the test,
2183 * but sometimes it may fail. To make sure the parameters are
2184 * more stable, we test each set of parameters 3 times.
2185 */
2186 for (j = 0; j < 3; j++) {
2187 mmc_send_tuning(mmc, opcode, &cmd_err);
2188 if (!cmd_err) {
2189 cmd_delay |= BIT(i);
2190 } else {
2191 cmd_delay &= ~BIT(i);
2192 break;
2193 }
2194 }
2195 }
2196 final_cmd_delay = get_best_delay(host, cmd_delay);
2197 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2198 final_cmd_delay.final_phase);
2199 final_delay = final_cmd_delay.final_phase;
2200
2201 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2202 return final_delay == 0xff ? -EIO : 0;
2203 }
2204
msdc_tune_data(struct mmc_host * mmc,u32 opcode)2205 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2206 {
2207 struct msdc_host *host = mmc_priv(mmc);
2208 u64 rise_delay = 0, fall_delay = 0;
2209 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2210 u8 final_delay, final_maxlen;
2211 int i, ret;
2212
2213 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2214 host->latch_ck);
2215 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2216 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2217 for (i = 0; i < host->tuning_step; i++) {
2218 msdc_set_data_delay(host, i);
2219 ret = mmc_send_tuning(mmc, opcode, NULL);
2220 if (!ret)
2221 rise_delay |= BIT_ULL(i);
2222 }
2223 final_rise_delay = get_best_delay(host, rise_delay);
2224 /* if rising edge has enough margin, then do not scan falling edge */
2225 if (final_rise_delay.maxlen >= 12 ||
2226 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2227 goto skip_fall;
2228
2229 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2230 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2231 for (i = 0; i < host->tuning_step; i++) {
2232 msdc_set_data_delay(host, i);
2233 ret = mmc_send_tuning(mmc, opcode, NULL);
2234 if (!ret)
2235 fall_delay |= BIT_ULL(i);
2236 }
2237 final_fall_delay = get_best_delay(host, fall_delay);
2238
2239 skip_fall:
2240 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2241 if (final_maxlen == final_rise_delay.maxlen) {
2242 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2243 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2244 final_delay = final_rise_delay.final_phase;
2245 } else {
2246 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2247 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2248 final_delay = final_fall_delay.final_phase;
2249 }
2250 msdc_set_data_delay(host, final_delay);
2251
2252 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2253 return final_delay == 0xff ? -EIO : 0;
2254 }
2255
2256 /*
2257 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2258 * together, which can save the tuning time.
2259 */
msdc_tune_together(struct mmc_host * mmc,u32 opcode)2260 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2261 {
2262 struct msdc_host *host = mmc_priv(mmc);
2263 u64 rise_delay = 0, fall_delay = 0;
2264 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2265 u8 final_delay, final_maxlen;
2266 int i, ret;
2267
2268 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2269 host->latch_ck);
2270
2271 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2272 sdr_clr_bits(host->base + MSDC_IOCON,
2273 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2274 for (i = 0; i < host->tuning_step; i++) {
2275 msdc_set_cmd_delay(host, i);
2276 msdc_set_data_delay(host, i);
2277 ret = mmc_send_tuning(mmc, opcode, NULL);
2278 if (!ret)
2279 rise_delay |= BIT_ULL(i);
2280 }
2281 final_rise_delay = get_best_delay(host, rise_delay);
2282 /* if rising edge has enough margin, then do not scan falling edge */
2283 if (final_rise_delay.maxlen >= 12 ||
2284 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2285 goto skip_fall;
2286
2287 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2288 sdr_set_bits(host->base + MSDC_IOCON,
2289 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2290 for (i = 0; i < host->tuning_step; i++) {
2291 msdc_set_cmd_delay(host, i);
2292 msdc_set_data_delay(host, i);
2293 ret = mmc_send_tuning(mmc, opcode, NULL);
2294 if (!ret)
2295 fall_delay |= BIT_ULL(i);
2296 }
2297 final_fall_delay = get_best_delay(host, fall_delay);
2298
2299 skip_fall:
2300 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2301 if (final_maxlen == final_rise_delay.maxlen) {
2302 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2303 sdr_clr_bits(host->base + MSDC_IOCON,
2304 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2305 final_delay = final_rise_delay.final_phase;
2306 } else {
2307 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2308 sdr_set_bits(host->base + MSDC_IOCON,
2309 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2310 final_delay = final_fall_delay.final_phase;
2311 }
2312
2313 msdc_set_cmd_delay(host, final_delay);
2314 msdc_set_data_delay(host, final_delay);
2315
2316 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2317 return final_delay == 0xff ? -EIO : 0;
2318 }
2319
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)2320 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2321 {
2322 struct msdc_host *host = mmc_priv(mmc);
2323 int ret;
2324 u32 tune_reg = host->dev_comp->pad_tune_reg;
2325
2326 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2327 ret = msdc_tune_together(mmc, opcode);
2328 if (host->hs400_mode) {
2329 sdr_clr_bits(host->base + MSDC_IOCON,
2330 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2331 msdc_set_data_delay(host, 0);
2332 }
2333 goto tune_done;
2334 }
2335 if (host->hs400_mode &&
2336 host->dev_comp->hs400_tune)
2337 ret = hs400_tune_response(mmc, opcode);
2338 else
2339 ret = msdc_tune_response(mmc, opcode);
2340 if (ret == -EIO) {
2341 dev_err(host->dev, "Tune response fail!\n");
2342 return ret;
2343 }
2344 if (host->hs400_mode == false) {
2345 ret = msdc_tune_data(mmc, opcode);
2346 if (ret == -EIO)
2347 dev_err(host->dev, "Tune data fail!\n");
2348 }
2349
2350 tune_done:
2351 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2352 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2353 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2354 if (host->top_base) {
2355 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2356 EMMC_TOP_CONTROL);
2357 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2358 EMMC_TOP_CMD);
2359 }
2360 return ret;
2361 }
2362
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2363 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2364 {
2365 struct msdc_host *host = mmc_priv(mmc);
2366 host->hs400_mode = true;
2367
2368 if (host->top_base)
2369 writel(host->hs400_ds_delay,
2370 host->top_base + EMMC50_PAD_DS_TUNE);
2371 else
2372 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2373 /* hs400 mode must set it to 0 */
2374 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2375 /* to improve read performance, set outstanding to 2 */
2376 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2377
2378 return 0;
2379 }
2380
msdc_execute_hs400_tuning(struct mmc_host * mmc,struct mmc_card * card)2381 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2382 {
2383 struct msdc_host *host = mmc_priv(mmc);
2384 struct msdc_delay_phase dly1_delay;
2385 u32 val, result_dly1 = 0;
2386 u8 *ext_csd;
2387 int i, ret;
2388
2389 if (host->top_base) {
2390 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2391 PAD_DS_DLY_SEL);
2392 if (host->hs400_ds_dly3)
2393 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2394 PAD_DS_DLY3, host->hs400_ds_dly3);
2395 } else {
2396 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2397 if (host->hs400_ds_dly3)
2398 sdr_set_field(host->base + PAD_DS_TUNE,
2399 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2400 }
2401
2402 host->hs400_tuning = true;
2403 for (i = 0; i < PAD_DELAY_HALF; i++) {
2404 if (host->top_base)
2405 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2406 PAD_DS_DLY1, i);
2407 else
2408 sdr_set_field(host->base + PAD_DS_TUNE,
2409 PAD_DS_TUNE_DLY1, i);
2410 ret = mmc_get_ext_csd(card, &ext_csd);
2411 if (!ret) {
2412 result_dly1 |= BIT(i);
2413 kfree(ext_csd);
2414 }
2415 }
2416 host->hs400_tuning = false;
2417
2418 dly1_delay = get_best_delay(host, result_dly1);
2419 if (dly1_delay.maxlen == 0) {
2420 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2421 goto fail;
2422 }
2423 if (host->top_base)
2424 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2425 PAD_DS_DLY1, dly1_delay.final_phase);
2426 else
2427 sdr_set_field(host->base + PAD_DS_TUNE,
2428 PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2429
2430 if (host->top_base)
2431 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2432 else
2433 val = readl(host->base + PAD_DS_TUNE);
2434
2435 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2436
2437 return 0;
2438
2439 fail:
2440 dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2441 return -EIO;
2442 }
2443
msdc_hw_reset(struct mmc_host * mmc)2444 static void msdc_hw_reset(struct mmc_host *mmc)
2445 {
2446 struct msdc_host *host = mmc_priv(mmc);
2447
2448 sdr_set_bits(host->base + EMMC_IOCON, 1);
2449 udelay(10); /* 10us is enough */
2450 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2451 }
2452
msdc_ack_sdio_irq(struct mmc_host * mmc)2453 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2454 {
2455 unsigned long flags;
2456 struct msdc_host *host = mmc_priv(mmc);
2457
2458 spin_lock_irqsave(&host->lock, flags);
2459 __msdc_enable_sdio_irq(host, 1);
2460 spin_unlock_irqrestore(&host->lock, flags);
2461 }
2462
msdc_get_cd(struct mmc_host * mmc)2463 static int msdc_get_cd(struct mmc_host *mmc)
2464 {
2465 struct msdc_host *host = mmc_priv(mmc);
2466 int val;
2467
2468 if (mmc->caps & MMC_CAP_NONREMOVABLE)
2469 return 1;
2470
2471 if (!host->internal_cd)
2472 return mmc_gpio_get_cd(mmc);
2473
2474 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2475 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2476 return !!val;
2477 else
2478 return !val;
2479 }
2480
msdc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)2481 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2482 struct mmc_ios *ios)
2483 {
2484 struct msdc_host *host = mmc_priv(mmc);
2485
2486 if (ios->enhanced_strobe) {
2487 msdc_prepare_hs400_tuning(mmc, ios);
2488 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2489 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2490 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2491
2492 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2493 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2494 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2495 } else {
2496 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2497 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2498 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2499
2500 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2501 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2502 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2503 }
2504 }
2505
msdc_cqe_cit_cal(struct msdc_host * host,u64 timer_ns)2506 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2507 {
2508 struct mmc_host *mmc = mmc_from_priv(host);
2509 struct cqhci_host *cq_host = mmc->cqe_private;
2510 u8 itcfmul;
2511 u64 hclk_freq, value;
2512
2513 /*
2514 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2515 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2516 * Send Status Command Idle Timer (CIT) value.
2517 */
2518 hclk_freq = (u64)clk_get_rate(host->h_clk);
2519 itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2520 switch (itcfmul) {
2521 case 0x0:
2522 do_div(hclk_freq, 1000);
2523 break;
2524 case 0x1:
2525 do_div(hclk_freq, 100);
2526 break;
2527 case 0x2:
2528 do_div(hclk_freq, 10);
2529 break;
2530 case 0x3:
2531 break;
2532 case 0x4:
2533 hclk_freq = hclk_freq * 10;
2534 break;
2535 default:
2536 host->cq_ssc1_time = 0x40;
2537 return;
2538 }
2539
2540 value = hclk_freq * timer_ns;
2541 do_div(value, 1000000000);
2542 host->cq_ssc1_time = value;
2543 }
2544
msdc_cqe_enable(struct mmc_host * mmc)2545 static void msdc_cqe_enable(struct mmc_host *mmc)
2546 {
2547 struct msdc_host *host = mmc_priv(mmc);
2548 struct cqhci_host *cq_host = mmc->cqe_private;
2549
2550 /* enable cmdq irq */
2551 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2552 /* enable busy check */
2553 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2554 /* default write data / busy timeout 20s */
2555 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2556 /* default read data timeout 1s */
2557 msdc_set_timeout(host, 1000000000ULL, 0);
2558
2559 /* Set the send status command idle timer */
2560 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2561 }
2562
msdc_cqe_disable(struct mmc_host * mmc,bool recovery)2563 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2564 {
2565 struct msdc_host *host = mmc_priv(mmc);
2566 unsigned int val = 0;
2567
2568 /* disable cmdq irq */
2569 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2570 /* disable busy check */
2571 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2572
2573 val = readl(host->base + MSDC_INT);
2574 writel(val, host->base + MSDC_INT);
2575
2576 if (recovery) {
2577 sdr_set_field(host->base + MSDC_DMA_CTRL,
2578 MSDC_DMA_CTRL_STOP, 1);
2579 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2580 !(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2581 return;
2582 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2583 !(val & MSDC_DMA_CFG_STS), 1, 3000)))
2584 return;
2585 msdc_reset_hw(host);
2586 }
2587 }
2588
msdc_cqe_pre_enable(struct mmc_host * mmc)2589 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2590 {
2591 struct cqhci_host *cq_host = mmc->cqe_private;
2592 u32 reg;
2593
2594 reg = cqhci_readl(cq_host, CQHCI_CFG);
2595 reg |= CQHCI_ENABLE;
2596 cqhci_writel(cq_host, reg, CQHCI_CFG);
2597 }
2598
msdc_cqe_post_disable(struct mmc_host * mmc)2599 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2600 {
2601 struct cqhci_host *cq_host = mmc->cqe_private;
2602 u32 reg;
2603
2604 reg = cqhci_readl(cq_host, CQHCI_CFG);
2605 reg &= ~CQHCI_ENABLE;
2606 cqhci_writel(cq_host, reg, CQHCI_CFG);
2607 }
2608
2609 static const struct mmc_host_ops mt_msdc_ops = {
2610 .post_req = msdc_post_req,
2611 .pre_req = msdc_pre_req,
2612 .request = msdc_ops_request,
2613 .set_ios = msdc_ops_set_ios,
2614 .get_ro = mmc_gpio_get_ro,
2615 .get_cd = msdc_get_cd,
2616 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2617 .enable_sdio_irq = msdc_enable_sdio_irq,
2618 .ack_sdio_irq = msdc_ack_sdio_irq,
2619 .start_signal_voltage_switch = msdc_ops_switch_volt,
2620 .card_busy = msdc_card_busy,
2621 .execute_tuning = msdc_execute_tuning,
2622 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2623 .execute_hs400_tuning = msdc_execute_hs400_tuning,
2624 .card_hw_reset = msdc_hw_reset,
2625 };
2626
2627 static const struct cqhci_host_ops msdc_cmdq_ops = {
2628 .enable = msdc_cqe_enable,
2629 .disable = msdc_cqe_disable,
2630 .pre_enable = msdc_cqe_pre_enable,
2631 .post_disable = msdc_cqe_post_disable,
2632 };
2633
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)2634 static void msdc_of_property_parse(struct platform_device *pdev,
2635 struct msdc_host *host)
2636 {
2637 struct mmc_host *mmc = mmc_from_priv(host);
2638
2639 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2640 &host->latch_ck);
2641
2642 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2643 &host->hs400_ds_delay);
2644
2645 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2646 &host->hs400_ds_dly3);
2647
2648 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2649 &host->hs200_cmd_int_delay);
2650
2651 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2652 &host->hs400_cmd_int_delay);
2653
2654 if (of_property_read_bool(pdev->dev.of_node,
2655 "mediatek,hs400-cmd-resp-sel-rising"))
2656 host->hs400_cmd_resp_sel_rising = true;
2657 else
2658 host->hs400_cmd_resp_sel_rising = false;
2659
2660 if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step",
2661 &host->tuning_step)) {
2662 if (mmc->caps2 & MMC_CAP2_NO_MMC)
2663 host->tuning_step = PAD_DELAY_FULL;
2664 else
2665 host->tuning_step = PAD_DELAY_HALF;
2666 }
2667
2668 if (of_property_read_bool(pdev->dev.of_node,
2669 "supports-cqe"))
2670 host->cqhci = true;
2671 else
2672 host->cqhci = false;
2673 }
2674
msdc_of_clock_parse(struct platform_device * pdev,struct msdc_host * host)2675 static int msdc_of_clock_parse(struct platform_device *pdev,
2676 struct msdc_host *host)
2677 {
2678 int ret;
2679
2680 host->src_clk = devm_clk_get(&pdev->dev, "source");
2681 if (IS_ERR(host->src_clk))
2682 return PTR_ERR(host->src_clk);
2683
2684 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2685 if (IS_ERR(host->h_clk))
2686 return PTR_ERR(host->h_clk);
2687
2688 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2689 if (IS_ERR(host->bus_clk))
2690 host->bus_clk = NULL;
2691
2692 /*source clock control gate is optional clock*/
2693 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2694 if (IS_ERR(host->src_clk_cg))
2695 return PTR_ERR(host->src_clk_cg);
2696
2697 /*
2698 * Fallback for legacy device-trees: src_clk and HCLK use the same
2699 * bit to control gating but they are parented to a different mux,
2700 * hence if our intention is to gate only the source, required
2701 * during a clk mode switch to avoid hw hangs, we need to gate
2702 * its parent (specified as a different clock only on new DTs).
2703 */
2704 if (!host->src_clk_cg) {
2705 host->src_clk_cg = clk_get_parent(host->src_clk);
2706 if (IS_ERR(host->src_clk_cg))
2707 return PTR_ERR(host->src_clk_cg);
2708 }
2709
2710 /* If present, always enable for this clock gate */
2711 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2712 if (IS_ERR(host->sys_clk_cg))
2713 host->sys_clk_cg = NULL;
2714
2715 host->bulk_clks[0].id = "pclk_cg";
2716 host->bulk_clks[1].id = "axi_cg";
2717 host->bulk_clks[2].id = "ahb_cg";
2718 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2719 host->bulk_clks);
2720 if (ret) {
2721 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2722 return ret;
2723 }
2724
2725 return 0;
2726 }
2727
msdc_drv_probe(struct platform_device * pdev)2728 static int msdc_drv_probe(struct platform_device *pdev)
2729 {
2730 struct mmc_host *mmc;
2731 struct msdc_host *host;
2732 struct resource *res;
2733 int ret;
2734
2735 if (!pdev->dev.of_node) {
2736 dev_err(&pdev->dev, "No DT found\n");
2737 return -EINVAL;
2738 }
2739
2740 /* Allocate MMC host for this device */
2741 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2742 if (!mmc)
2743 return -ENOMEM;
2744
2745 host = mmc_priv(mmc);
2746 ret = mmc_of_parse(mmc);
2747 if (ret)
2748 goto host_free;
2749
2750 host->base = devm_platform_ioremap_resource(pdev, 0);
2751 if (IS_ERR(host->base)) {
2752 ret = PTR_ERR(host->base);
2753 goto host_free;
2754 }
2755
2756 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2757 if (res) {
2758 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2759 if (IS_ERR(host->top_base))
2760 host->top_base = NULL;
2761 }
2762
2763 ret = mmc_regulator_get_supply(mmc);
2764 if (ret)
2765 goto host_free;
2766
2767 ret = msdc_of_clock_parse(pdev, host);
2768 if (ret)
2769 goto host_free;
2770
2771 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2772 "hrst");
2773 if (IS_ERR(host->reset)) {
2774 ret = PTR_ERR(host->reset);
2775 goto host_free;
2776 }
2777
2778 /* only eMMC has crypto property */
2779 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
2780 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2781 if (IS_ERR(host->crypto_clk))
2782 host->crypto_clk = NULL;
2783 else
2784 mmc->caps2 |= MMC_CAP2_CRYPTO;
2785 }
2786
2787 host->irq = platform_get_irq(pdev, 0);
2788 if (host->irq < 0) {
2789 ret = host->irq;
2790 goto host_free;
2791 }
2792
2793 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2794 if (IS_ERR(host->pinctrl)) {
2795 ret = PTR_ERR(host->pinctrl);
2796 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2797 goto host_free;
2798 }
2799
2800 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2801 if (IS_ERR(host->pins_default)) {
2802 ret = PTR_ERR(host->pins_default);
2803 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2804 goto host_free;
2805 }
2806
2807 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2808 if (IS_ERR(host->pins_uhs)) {
2809 ret = PTR_ERR(host->pins_uhs);
2810 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2811 goto host_free;
2812 }
2813
2814 /* Support for SDIO eint irq ? */
2815 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2816 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
2817 if (host->eint_irq > 0) {
2818 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2819 if (IS_ERR(host->pins_eint)) {
2820 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2821 host->pins_eint = NULL;
2822 } else {
2823 device_init_wakeup(&pdev->dev, true);
2824 }
2825 }
2826 }
2827
2828 msdc_of_property_parse(pdev, host);
2829
2830 host->dev = &pdev->dev;
2831 host->dev_comp = of_device_get_match_data(&pdev->dev);
2832 host->src_clk_freq = clk_get_rate(host->src_clk);
2833 /* Set host parameters to mmc */
2834 mmc->ops = &mt_msdc_ops;
2835 if (host->dev_comp->clk_div_bits == 8)
2836 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2837 else
2838 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2839
2840 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2841 !mmc_can_gpio_cd(mmc) &&
2842 host->dev_comp->use_internal_cd) {
2843 /*
2844 * Is removable but no GPIO declared, so
2845 * use internal functionality.
2846 */
2847 host->internal_cd = true;
2848 }
2849
2850 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2851 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2852
2853 mmc->caps |= MMC_CAP_CMD23;
2854 if (host->cqhci)
2855 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2856 /* MMC core transfer sizes tunable parameters */
2857 mmc->max_segs = MAX_BD_NUM;
2858 if (host->dev_comp->support_64g)
2859 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2860 else
2861 mmc->max_seg_size = BDMA_DESC_BUFLEN;
2862 mmc->max_blk_size = 2048;
2863 mmc->max_req_size = 512 * 1024;
2864 mmc->max_blk_count = mmc->max_req_size / 512;
2865 if (host->dev_comp->support_64g)
2866 host->dma_mask = DMA_BIT_MASK(36);
2867 else
2868 host->dma_mask = DMA_BIT_MASK(32);
2869 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2870
2871 host->timeout_clks = 3 * 1048576;
2872 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2873 2 * sizeof(struct mt_gpdma_desc),
2874 &host->dma.gpd_addr, GFP_KERNEL);
2875 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2876 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2877 &host->dma.bd_addr, GFP_KERNEL);
2878 if (!host->dma.gpd || !host->dma.bd) {
2879 ret = -ENOMEM;
2880 goto release_mem;
2881 }
2882 msdc_init_gpd_bd(host, &host->dma);
2883 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2884 spin_lock_init(&host->lock);
2885
2886 platform_set_drvdata(pdev, mmc);
2887 ret = msdc_ungate_clock(host);
2888 if (ret) {
2889 dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2890 goto release_mem;
2891 }
2892 msdc_init_hw(host);
2893
2894 if (mmc->caps2 & MMC_CAP2_CQE) {
2895 host->cq_host = devm_kzalloc(mmc->parent,
2896 sizeof(*host->cq_host),
2897 GFP_KERNEL);
2898 if (!host->cq_host) {
2899 ret = -ENOMEM;
2900 goto host_free;
2901 }
2902 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2903 host->cq_host->mmio = host->base + 0x800;
2904 host->cq_host->ops = &msdc_cmdq_ops;
2905 ret = cqhci_init(host->cq_host, mmc, true);
2906 if (ret)
2907 goto host_free;
2908 mmc->max_segs = 128;
2909 /* cqhci 16bit length */
2910 /* 0 size, means 65536 so we don't have to -1 here */
2911 mmc->max_seg_size = 64 * 1024;
2912 /* Reduce CIT to 0x40 that corresponds to 2.35us */
2913 msdc_cqe_cit_cal(host, 2350);
2914 }
2915
2916 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2917 IRQF_TRIGGER_NONE, pdev->name, host);
2918 if (ret)
2919 goto release;
2920
2921 pm_runtime_set_active(host->dev);
2922 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2923 pm_runtime_use_autosuspend(host->dev);
2924 pm_runtime_enable(host->dev);
2925 ret = mmc_add_host(mmc);
2926
2927 if (ret)
2928 goto end;
2929
2930 return 0;
2931 end:
2932 pm_runtime_disable(host->dev);
2933 release:
2934 platform_set_drvdata(pdev, NULL);
2935 msdc_deinit_hw(host);
2936 msdc_gate_clock(host);
2937 release_mem:
2938 if (host->dma.gpd)
2939 dma_free_coherent(&pdev->dev,
2940 2 * sizeof(struct mt_gpdma_desc),
2941 host->dma.gpd, host->dma.gpd_addr);
2942 if (host->dma.bd)
2943 dma_free_coherent(&pdev->dev,
2944 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2945 host->dma.bd, host->dma.bd_addr);
2946 host_free:
2947 mmc_free_host(mmc);
2948
2949 return ret;
2950 }
2951
msdc_drv_remove(struct platform_device * pdev)2952 static void msdc_drv_remove(struct platform_device *pdev)
2953 {
2954 struct mmc_host *mmc;
2955 struct msdc_host *host;
2956
2957 mmc = platform_get_drvdata(pdev);
2958 host = mmc_priv(mmc);
2959
2960 pm_runtime_get_sync(host->dev);
2961
2962 platform_set_drvdata(pdev, NULL);
2963 mmc_remove_host(mmc);
2964 msdc_deinit_hw(host);
2965 msdc_gate_clock(host);
2966
2967 pm_runtime_disable(host->dev);
2968 pm_runtime_put_noidle(host->dev);
2969 dma_free_coherent(&pdev->dev,
2970 2 * sizeof(struct mt_gpdma_desc),
2971 host->dma.gpd, host->dma.gpd_addr);
2972 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2973 host->dma.bd, host->dma.bd_addr);
2974
2975 mmc_free_host(mmc);
2976 }
2977
msdc_save_reg(struct msdc_host * host)2978 static void msdc_save_reg(struct msdc_host *host)
2979 {
2980 u32 tune_reg = host->dev_comp->pad_tune_reg;
2981
2982 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2983 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2984 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2985 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2986 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2987 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2988 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2989 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2990 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2991 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2992 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2993 if (host->top_base) {
2994 host->save_para.emmc_top_control =
2995 readl(host->top_base + EMMC_TOP_CONTROL);
2996 host->save_para.emmc_top_cmd =
2997 readl(host->top_base + EMMC_TOP_CMD);
2998 host->save_para.emmc50_pad_ds_tune =
2999 readl(host->top_base + EMMC50_PAD_DS_TUNE);
3000 } else {
3001 host->save_para.pad_tune = readl(host->base + tune_reg);
3002 }
3003 }
3004
msdc_restore_reg(struct msdc_host * host)3005 static void msdc_restore_reg(struct msdc_host *host)
3006 {
3007 struct mmc_host *mmc = mmc_from_priv(host);
3008 u32 tune_reg = host->dev_comp->pad_tune_reg;
3009
3010 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
3011 writel(host->save_para.iocon, host->base + MSDC_IOCON);
3012 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
3013 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
3014 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
3015 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
3016 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
3017 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
3018 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
3019 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
3020 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
3021 if (host->top_base) {
3022 writel(host->save_para.emmc_top_control,
3023 host->top_base + EMMC_TOP_CONTROL);
3024 writel(host->save_para.emmc_top_cmd,
3025 host->top_base + EMMC_TOP_CMD);
3026 writel(host->save_para.emmc50_pad_ds_tune,
3027 host->top_base + EMMC50_PAD_DS_TUNE);
3028 } else {
3029 writel(host->save_para.pad_tune, host->base + tune_reg);
3030 }
3031
3032 if (sdio_irq_claimed(mmc))
3033 __msdc_enable_sdio_irq(host, 1);
3034 }
3035
msdc_runtime_suspend(struct device * dev)3036 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
3037 {
3038 struct mmc_host *mmc = dev_get_drvdata(dev);
3039 struct msdc_host *host = mmc_priv(mmc);
3040
3041 msdc_save_reg(host);
3042
3043 if (sdio_irq_claimed(mmc)) {
3044 if (host->pins_eint) {
3045 disable_irq(host->irq);
3046 pinctrl_select_state(host->pinctrl, host->pins_eint);
3047 }
3048
3049 __msdc_enable_sdio_irq(host, 0);
3050 }
3051 msdc_gate_clock(host);
3052 return 0;
3053 }
3054
msdc_runtime_resume(struct device * dev)3055 static int __maybe_unused msdc_runtime_resume(struct device *dev)
3056 {
3057 struct mmc_host *mmc = dev_get_drvdata(dev);
3058 struct msdc_host *host = mmc_priv(mmc);
3059 int ret;
3060
3061 ret = msdc_ungate_clock(host);
3062 if (ret)
3063 return ret;
3064
3065 msdc_restore_reg(host);
3066
3067 if (sdio_irq_claimed(mmc) && host->pins_eint) {
3068 pinctrl_select_state(host->pinctrl, host->pins_uhs);
3069 enable_irq(host->irq);
3070 }
3071 return 0;
3072 }
3073
msdc_suspend(struct device * dev)3074 static int __maybe_unused msdc_suspend(struct device *dev)
3075 {
3076 struct mmc_host *mmc = dev_get_drvdata(dev);
3077 struct msdc_host *host = mmc_priv(mmc);
3078 int ret;
3079 u32 val;
3080
3081 if (mmc->caps2 & MMC_CAP2_CQE) {
3082 ret = cqhci_suspend(mmc);
3083 if (ret)
3084 return ret;
3085 val = readl(host->base + MSDC_INT);
3086 writel(val, host->base + MSDC_INT);
3087 }
3088
3089 /*
3090 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3091 * not be marked as 1, pm_runtime_force_resume() will go out directly.
3092 */
3093 if (sdio_irq_claimed(mmc) && host->pins_eint)
3094 pm_runtime_get_noresume(dev);
3095
3096 return pm_runtime_force_suspend(dev);
3097 }
3098
msdc_resume(struct device * dev)3099 static int __maybe_unused msdc_resume(struct device *dev)
3100 {
3101 struct mmc_host *mmc = dev_get_drvdata(dev);
3102 struct msdc_host *host = mmc_priv(mmc);
3103
3104 if (sdio_irq_claimed(mmc) && host->pins_eint)
3105 pm_runtime_put_noidle(dev);
3106
3107 return pm_runtime_force_resume(dev);
3108 }
3109
3110 static const struct dev_pm_ops msdc_dev_pm_ops = {
3111 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3112 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3113 };
3114
3115 static struct platform_driver mt_msdc_driver = {
3116 .probe = msdc_drv_probe,
3117 .remove_new = msdc_drv_remove,
3118 .driver = {
3119 .name = "mtk-msdc",
3120 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3121 .of_match_table = msdc_of_ids,
3122 .pm = &msdc_dev_pm_ops,
3123 },
3124 };
3125
3126 module_platform_driver(mt_msdc_driver);
3127 MODULE_LICENSE("GPL v2");
3128 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
3129