1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _DISCOVERY_H_ 25 #define _DISCOVERY_H_ 26 27 #define PSP_HEADER_SIZE 256 28 #define BINARY_SIGNATURE 0x28211407 29 #define DISCOVERY_TABLE_SIGNATURE 0x53445049 30 #define GC_TABLE_ID 0x4347 31 #define HARVEST_TABLE_SIGNATURE 0x56524148 32 #define VCN_INFO_TABLE_ID 0x004E4356 33 #define MALL_INFO_TABLE_ID 0x4C4C414D 34 #define NPS_INFO_TABLE_ID 0x0053504E 35 36 typedef enum { 37 IP_DISCOVERY = 0, 38 GC, 39 HARVEST_INFO, 40 VCN_INFO, 41 MALL_INFO, 42 NPS_INFO, 43 TOTAL_TABLES = 6 44 } table; 45 46 #pragma pack(1) 47 48 typedef struct table_info 49 { 50 uint16_t offset; /* Byte offset */ 51 uint16_t checksum; /* Byte sum of the table */ 52 uint16_t size; /* Table size */ 53 uint16_t padding; 54 } table_info; 55 56 typedef struct binary_header 57 { 58 /* psp structure should go at the top of this structure */ 59 uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */ 60 uint16_t version_major; 61 uint16_t version_minor; 62 uint16_t binary_checksum; /* Byte sum of the binary after this field */ 63 uint16_t binary_size; /* Binary Size*/ 64 table_info table_list[TOTAL_TABLES]; 65 } binary_header; 66 67 typedef struct binary_header_v2 68 { 69 /* psp structure should go at the top of this structure */ 70 uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */ 71 uint16_t version_major; /* 0x02 */ 72 uint16_t version_minor; 73 uint16_t binary_checksum; /* Byte sum of the binary after this field */ 74 uint16_t binary_size; /* Binary Size*/ 75 uint16_t num_tables; 76 uint16_t padding; 77 table_info table_list[] __counted_by(num_tables); 78 } binary_header_v2; 79 80 typedef struct die_info 81 { 82 uint16_t die_id; 83 uint16_t die_offset; /* Points to the corresponding die_header structure */ 84 } die_info; 85 86 87 typedef struct ip_discovery_header 88 { 89 uint32_t signature; /* Table Signature */ 90 uint16_t version; /* Table Version */ 91 uint16_t size; /* Table Size */ 92 uint32_t id; /* Table ID */ 93 uint16_t num_dies; /* Number of Dies */ 94 die_info die_info[16]; /* list die information for up to 16 dies */ 95 union { 96 uint16_t padding[1]; /* version <= 3 */ 97 struct { /* version == 4 */ 98 uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */ 99 uint8_t reserved : 7; 100 uint8_t reserved2; 101 }; 102 }; 103 } ip_discovery_header; 104 105 typedef struct ip 106 { 107 uint16_t hw_id; /* Hardware ID */ 108 uint8_t number_instance; /* instance of the IP */ 109 uint8_t num_base_address; /* Number of Base Addresses */ 110 uint8_t major; /* HCID Major */ 111 uint8_t minor; /* HCID Minor */ 112 uint8_t revision; /* HCID Revision */ 113 #if defined(__BIG_ENDIAN) 114 uint8_t reserved : 4; /* Placeholder field */ 115 uint8_t harvest : 4; /* Harvest */ 116 #else 117 uint8_t harvest : 4; /* Harvest */ 118 uint8_t reserved : 4; /* Placeholder field */ 119 #endif 120 uint32_t base_address[]; /* variable number of Addresses */ 121 } ip; 122 123 typedef struct ip_v3 124 { 125 uint16_t hw_id; /* Hardware ID */ 126 uint8_t instance_number; /* Instance number for the IP */ 127 uint8_t num_base_address; /* Number of base addresses*/ 128 uint8_t major; /* Hardware ID.major version */ 129 uint8_t minor; /* Hardware ID.minor version */ 130 uint8_t revision; /* Hardware ID.revision version */ 131 #if defined(__BIG_ENDIAN) 132 uint8_t variant : 4; /* HW variant */ 133 uint8_t sub_revision : 4; /* HCID Sub-Revision */ 134 #else 135 uint8_t sub_revision : 4; /* HCID Sub-Revision */ 136 uint8_t variant : 4; /* HW variant */ 137 #endif 138 uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/ 139 } ip_v3; 140 141 typedef struct ip_v4 { 142 uint16_t hw_id; /* Hardware ID */ 143 uint8_t instance_number; /* Instance number for the IP */ 144 uint8_t num_base_address; /* Number of base addresses*/ 145 uint8_t major; /* Hardware ID.major version */ 146 uint8_t minor; /* Hardware ID.minor version */ 147 uint8_t revision; /* Hardware ID.revision version */ 148 #if defined(LITTLEENDIAN_CPU) 149 uint8_t sub_revision : 4; /* HCID Sub-Revision */ 150 uint8_t variant : 4; /* HW variant */ 151 #elif defined(BIGENDIAN_CPU) 152 uint8_t variant : 4; /* HW variant */ 153 uint8_t sub_revision : 4; /* HCID Sub-Revision */ 154 #endif 155 union { 156 DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_base_address field*/ 157 DECLARE_FLEX_ARRAY(uint64_t, base_address_64); /* 64-bit Base Address list. Corresponds to the num_base_address field*/ 158 } __packed; 159 } ip_v4; 160 161 typedef struct die_header 162 { 163 uint16_t die_id; 164 uint16_t num_ips; 165 } die_header; 166 167 typedef struct ip_structure 168 { 169 ip_discovery_header* header; 170 struct die 171 { 172 die_header *die_header; 173 union 174 { 175 ip *ip_list; 176 ip_v3 *ip_v3_list; 177 ip_v4 *ip_v4_list; 178 }; /* IP list. Variable size*/ 179 } die; 180 } ip_structure; 181 182 struct gpu_info_header { 183 uint32_t table_id; /* table ID */ 184 uint16_t version_major; /* table version */ 185 uint16_t version_minor; /* table version */ 186 uint32_t size; /* size of the entire header+data in bytes */ 187 }; 188 189 struct gc_info_v1_0 { 190 struct gpu_info_header header; 191 192 uint32_t gc_num_se; 193 uint32_t gc_num_wgp0_per_sa; 194 uint32_t gc_num_wgp1_per_sa; 195 uint32_t gc_num_rb_per_se; 196 uint32_t gc_num_gl2c; 197 uint32_t gc_num_gprs; 198 uint32_t gc_num_max_gs_thds; 199 uint32_t gc_gs_table_depth; 200 uint32_t gc_gsprim_buff_depth; 201 uint32_t gc_parameter_cache_depth; 202 uint32_t gc_double_offchip_lds_buffer; 203 uint32_t gc_wave_size; 204 uint32_t gc_max_waves_per_simd; 205 uint32_t gc_max_scratch_slots_per_cu; 206 uint32_t gc_lds_size; 207 uint32_t gc_num_sc_per_se; 208 uint32_t gc_num_sa_per_se; 209 uint32_t gc_num_packer_per_sc; 210 uint32_t gc_num_gl2a; 211 }; 212 213 struct gc_info_v1_1 { 214 struct gpu_info_header header; 215 216 uint32_t gc_num_se; 217 uint32_t gc_num_wgp0_per_sa; 218 uint32_t gc_num_wgp1_per_sa; 219 uint32_t gc_num_rb_per_se; 220 uint32_t gc_num_gl2c; 221 uint32_t gc_num_gprs; 222 uint32_t gc_num_max_gs_thds; 223 uint32_t gc_gs_table_depth; 224 uint32_t gc_gsprim_buff_depth; 225 uint32_t gc_parameter_cache_depth; 226 uint32_t gc_double_offchip_lds_buffer; 227 uint32_t gc_wave_size; 228 uint32_t gc_max_waves_per_simd; 229 uint32_t gc_max_scratch_slots_per_cu; 230 uint32_t gc_lds_size; 231 uint32_t gc_num_sc_per_se; 232 uint32_t gc_num_sa_per_se; 233 uint32_t gc_num_packer_per_sc; 234 uint32_t gc_num_gl2a; 235 uint32_t gc_num_tcp_per_sa; 236 uint32_t gc_num_sdp_interface; 237 uint32_t gc_num_tcps; 238 }; 239 240 struct gc_info_v1_2 { 241 struct gpu_info_header header; 242 uint32_t gc_num_se; 243 uint32_t gc_num_wgp0_per_sa; 244 uint32_t gc_num_wgp1_per_sa; 245 uint32_t gc_num_rb_per_se; 246 uint32_t gc_num_gl2c; 247 uint32_t gc_num_gprs; 248 uint32_t gc_num_max_gs_thds; 249 uint32_t gc_gs_table_depth; 250 uint32_t gc_gsprim_buff_depth; 251 uint32_t gc_parameter_cache_depth; 252 uint32_t gc_double_offchip_lds_buffer; 253 uint32_t gc_wave_size; 254 uint32_t gc_max_waves_per_simd; 255 uint32_t gc_max_scratch_slots_per_cu; 256 uint32_t gc_lds_size; 257 uint32_t gc_num_sc_per_se; 258 uint32_t gc_num_sa_per_se; 259 uint32_t gc_num_packer_per_sc; 260 uint32_t gc_num_gl2a; 261 uint32_t gc_num_tcp_per_sa; 262 uint32_t gc_num_sdp_interface; 263 uint32_t gc_num_tcps; 264 uint32_t gc_num_tcp_per_wpg; 265 uint32_t gc_tcp_l1_size; 266 uint32_t gc_num_sqc_per_wgp; 267 uint32_t gc_l1_instruction_cache_size_per_sqc; 268 uint32_t gc_l1_data_cache_size_per_sqc; 269 uint32_t gc_gl1c_per_sa; 270 uint32_t gc_gl1c_size_per_instance; 271 uint32_t gc_gl2c_per_gpu; 272 }; 273 274 struct gc_info_v1_3 { 275 struct gpu_info_header header; 276 uint32_t gc_num_se; 277 uint32_t gc_num_wgp0_per_sa; 278 uint32_t gc_num_wgp1_per_sa; 279 uint32_t gc_num_rb_per_se; 280 uint32_t gc_num_gl2c; 281 uint32_t gc_num_gprs; 282 uint32_t gc_num_max_gs_thds; 283 uint32_t gc_gs_table_depth; 284 uint32_t gc_gsprim_buff_depth; 285 uint32_t gc_parameter_cache_depth; 286 uint32_t gc_double_offchip_lds_buffer; 287 uint32_t gc_wave_size; 288 uint32_t gc_max_waves_per_simd; 289 uint32_t gc_max_scratch_slots_per_cu; 290 uint32_t gc_lds_size; 291 uint32_t gc_num_sc_per_se; 292 uint32_t gc_num_sa_per_se; 293 uint32_t gc_num_packer_per_sc; 294 uint32_t gc_num_gl2a; 295 uint32_t gc_num_tcp_per_sa; 296 uint32_t gc_num_sdp_interface; 297 uint32_t gc_num_tcps; 298 uint32_t gc_num_tcp_per_wpg; 299 uint32_t gc_tcp_l1_size; 300 uint32_t gc_num_sqc_per_wgp; 301 uint32_t gc_l1_instruction_cache_size_per_sqc; 302 uint32_t gc_l1_data_cache_size_per_sqc; 303 uint32_t gc_gl1c_per_sa; 304 uint32_t gc_gl1c_size_per_instance; 305 uint32_t gc_gl2c_per_gpu; 306 uint32_t gc_tcp_size_per_cu; 307 uint32_t gc_tcp_cache_line_size; 308 uint32_t gc_instruction_cache_size_per_sqc; 309 uint32_t gc_instruction_cache_line_size; 310 uint32_t gc_scalar_data_cache_size_per_sqc; 311 uint32_t gc_scalar_data_cache_line_size; 312 uint32_t gc_tcc_size; 313 uint32_t gc_tcc_cache_line_size; 314 }; 315 316 struct gc_info_v2_0 { 317 struct gpu_info_header header; 318 319 uint32_t gc_num_se; 320 uint32_t gc_num_cu_per_sh; 321 uint32_t gc_num_sh_per_se; 322 uint32_t gc_num_rb_per_se; 323 uint32_t gc_num_tccs; 324 uint32_t gc_num_gprs; 325 uint32_t gc_num_max_gs_thds; 326 uint32_t gc_gs_table_depth; 327 uint32_t gc_gsprim_buff_depth; 328 uint32_t gc_parameter_cache_depth; 329 uint32_t gc_double_offchip_lds_buffer; 330 uint32_t gc_wave_size; 331 uint32_t gc_max_waves_per_simd; 332 uint32_t gc_max_scratch_slots_per_cu; 333 uint32_t gc_lds_size; 334 uint32_t gc_num_sc_per_se; 335 uint32_t gc_num_packer_per_sc; 336 }; 337 338 struct gc_info_v2_1 { 339 struct gpu_info_header header; 340 341 uint32_t gc_num_se; 342 uint32_t gc_num_cu_per_sh; 343 uint32_t gc_num_sh_per_se; 344 uint32_t gc_num_rb_per_se; 345 uint32_t gc_num_tccs; 346 uint32_t gc_num_gprs; 347 uint32_t gc_num_max_gs_thds; 348 uint32_t gc_gs_table_depth; 349 uint32_t gc_gsprim_buff_depth; 350 uint32_t gc_parameter_cache_depth; 351 uint32_t gc_double_offchip_lds_buffer; 352 uint32_t gc_wave_size; 353 uint32_t gc_max_waves_per_simd; 354 uint32_t gc_max_scratch_slots_per_cu; 355 uint32_t gc_lds_size; 356 uint32_t gc_num_sc_per_se; 357 uint32_t gc_num_packer_per_sc; 358 /* new for v2_1 */ 359 uint32_t gc_num_tcp_per_sh; 360 uint32_t gc_tcp_size_per_cu; 361 uint32_t gc_num_sdp_interface; 362 uint32_t gc_num_cu_per_sqc; 363 uint32_t gc_instruction_cache_size_per_sqc; 364 uint32_t gc_scalar_data_cache_size_per_sqc; 365 uint32_t gc_tcc_size; 366 }; 367 368 typedef struct harvest_info_header { 369 uint32_t signature; /* Table Signature */ 370 uint32_t version; /* Table Version */ 371 } harvest_info_header; 372 373 typedef struct harvest_info { 374 uint16_t hw_id; /* Hardware ID */ 375 uint8_t number_instance; /* Instance of the IP */ 376 uint8_t reserved; /* Reserved for alignment */ 377 } harvest_info; 378 379 typedef struct harvest_table { 380 harvest_info_header header; 381 harvest_info list[32]; 382 } harvest_table; 383 384 struct mall_info_header { 385 uint32_t table_id; /* table ID */ 386 uint16_t version_major; /* table version */ 387 uint16_t version_minor; /* table version */ 388 uint32_t size_bytes; /* size of the entire header+data in bytes */ 389 }; 390 391 struct mall_info_v1_0 { 392 struct mall_info_header header; 393 uint32_t mall_size_per_m; 394 uint32_t m_s_present; 395 uint32_t m_half_use; 396 uint32_t m_mall_config; 397 uint32_t reserved[5]; 398 }; 399 400 struct mall_info_v2_0 { 401 struct mall_info_header header; 402 uint32_t mall_size_per_umc; 403 uint32_t reserved[8]; 404 }; 405 406 #define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4 407 408 struct vcn_info_header { 409 uint32_t table_id; /* table ID */ 410 uint16_t version_major; /* table version */ 411 uint16_t version_minor; /* table version */ 412 uint32_t size_bytes; /* size of the entire header+data in bytes */ 413 }; 414 415 struct vcn_instance_info_v1_0 416 { 417 uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/ 418 union _fuse_data { 419 struct { 420 uint32_t av1_disabled : 1; 421 uint32_t vp9_disabled : 1; 422 uint32_t hevc_disabled : 1; 423 uint32_t h264_disabled : 1; 424 uint32_t reserved : 28; 425 } bits; 426 uint32_t all_bits; 427 } fuse_data; 428 uint32_t reserved[2]; 429 }; 430 431 struct vcn_info_v1_0 { 432 struct vcn_info_header header; 433 uint32_t num_of_instances; /* number of entries used in instance_info below*/ 434 struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES]; 435 uint32_t reserved[4]; 436 }; 437 438 #define NPS_INFO_TABLE_MAX_NUM_INSTANCES 12 439 440 struct nps_info_header { 441 uint32_t table_id; /* table ID */ 442 uint16_t version_major; /* table version */ 443 uint16_t version_minor; /* table version */ 444 uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */ 445 }; 446 447 struct nps_instance_info_v1_0 { 448 uint64_t base_address; 449 uint64_t limit_address; 450 }; 451 452 struct nps_info_v1_0 { 453 struct nps_info_header header; 454 uint32_t nps_type; 455 uint32_t count; 456 struct nps_instance_info_v1_0 457 instance_info[NPS_INFO_TABLE_MAX_NUM_INSTANCES]; 458 }; 459 460 #pragma pack() 461 462 #endif 463