1 /* 2 * bfin_sport.h - interface to Blackfin SPORTs 3 * 4 * Copyright 2004-2009 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9 #ifndef __BFIN_SPORT_H__ 10 #define __BFIN_SPORT_H__ 11 12 /* Sport mode: it can be set to TDM, i2s or others */ 13 #define NORM_MODE 0x0 14 #define TDM_MODE 0x1 15 #define I2S_MODE 0x2 16 17 /* Data format, normal, a-law or u-law */ 18 #define NORM_FORMAT 0x0 19 #define ALAW_FORMAT 0x2 20 #define ULAW_FORMAT 0x3 21 22 /* Function driver which use sport must initialize the structure */ 23 struct sport_config { 24 /* TDM (multichannels), I2S or other mode */ 25 unsigned int mode:3; 26 27 /* if TDM mode is selected, channels must be set */ 28 int channels; /* Must be in 8 units */ 29 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */ 30 31 /* I2S mode */ 32 unsigned int right_first:1; /* Right stereo channel first */ 33 34 /* In mormal mode, the following item need to be set */ 35 unsigned int lsb_first:1; /* order of transmit or receive data */ 36 unsigned int fsync:1; /* Frame sync required */ 37 unsigned int data_indep:1; /* data independent frame sync generated */ 38 unsigned int act_low:1; /* Active low TFS */ 39 unsigned int late_fsync:1; /* Late frame sync */ 40 unsigned int tckfe:1; 41 unsigned int sec_en:1; /* Secondary side enabled */ 42 43 /* Choose clock source */ 44 unsigned int int_clk:1; /* Internal or external clock */ 45 46 /* If external clock is used, the following fields are ignored */ 47 int serial_clk; 48 int fsync_clk; 49 50 unsigned int data_format:2; /* Normal, u-law or a-law */ 51 52 int word_len; /* How length of the word in bits, 3-32 bits */ 53 int dma_enabled; 54 }; 55 56 /* Userspace interface */ 57 #define SPORT_IOC_MAGIC 'P' 58 #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) 59 60 #ifdef __KERNEL__ 61 62 #include <linux/types.h> 63 64 /* 65 * All Blackfin system MMRs are padded to 32bits even if the register 66 * itself is only 16bits. So use a helper macro to streamline this. 67 */ 68 #define __BFP(m) u16 m; u16 __pad_##m 69 struct sport_register { 70 __BFP(tcr1); 71 __BFP(tcr2); 72 __BFP(tclkdiv); 73 __BFP(tfsdiv); 74 union { 75 u32 tx32; 76 u16 tx16; 77 }; 78 u32 __pad_tx; 79 union { 80 u32 rx32; /* use the anomaly wrapper below */ 81 u16 rx16; 82 }; 83 u32 __pad_rx; 84 __BFP(rcr1); 85 __BFP(rcr2); 86 __BFP(rclkdiv); 87 __BFP(rfsdiv); 88 __BFP(stat); 89 __BFP(chnl); 90 __BFP(mcmc1); 91 __BFP(mcmc2); 92 u32 mtcs0; 93 u32 mtcs1; 94 u32 mtcs2; 95 u32 mtcs3; 96 u32 mrcs0; 97 u32 mrcs1; 98 u32 mrcs2; 99 u32 mrcs3; 100 }; 101 #undef __BFP 102 103 struct bfin_snd_platform_data { 104 const unsigned short *pin_req; 105 }; 106 107 #define bfin_read_sport_rx32(base) \ 108 ({ \ 109 struct sport_register *__mmrs = (void *)base; \ 110 u32 __ret; \ 111 unsigned long flags; \ 112 if (ANOMALY_05000473) \ 113 local_irq_save(flags); \ 114 __ret = __mmrs->rx32; \ 115 if (ANOMALY_05000473) \ 116 local_irq_restore(flags); \ 117 __ret; \ 118 }) 119 120 #endif 121 122 /* SPORT_TCR1 Masks */ 123 #define TSPEN 0x0001 /* TX enable */ 124 #define ITCLK 0x0002 /* Internal TX Clock Select */ 125 #define TDTYPE 0x000C /* TX Data Formatting Select */ 126 #define DTYPE_NORM 0x0000 /* Data Format Normal */ 127 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ 128 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ 129 #define TLSBIT 0x0010 /* TX Bit Order */ 130 #define ITFS 0x0200 /* Internal TX Frame Sync Select */ 131 #define TFSR 0x0400 /* TX Frame Sync Required Select */ 132 #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ 133 #define LTFS 0x1000 /* Low TX Frame Sync Select */ 134 #define LATFS 0x2000 /* Late TX Frame Sync Select */ 135 #define TCKFE 0x4000 /* TX Clock Falling Edge Select */ 136 137 /* SPORT_TCR2 Masks */ 138 #define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */ 139 #define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x) 140 #define EX_SLEN(x) BFIN_EXTRACT(SLEN, x) 141 #define TXSE 0x0100 /* TX Secondary Enable */ 142 #define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ 143 #define TRFST 0x0400 /* TX Right-First Data Order */ 144 145 /* SPORT_RCR1 Masks */ 146 #define RSPEN 0x0001 /* RX enable */ 147 #define IRCLK 0x0002 /* Internal RX Clock Select */ 148 #define RDTYPE 0x000C /* RX Data Formatting Select */ 149 /* DTYPE_* defined above */ 150 #define RLSBIT 0x0010 /* RX Bit Order */ 151 #define IRFS 0x0200 /* Internal RX Frame Sync Select */ 152 #define RFSR 0x0400 /* RX Frame Sync Required Select */ 153 #define LRFS 0x1000 /* Low RX Frame Sync Select */ 154 #define LARFS 0x2000 /* Late RX Frame Sync Select */ 155 #define RCKFE 0x4000 /* RX Clock Falling Edge Select */ 156 157 /* SPORT_RCR2 Masks */ 158 /* SLEN defined above */ 159 #define RXSE 0x0100 /* RX Secondary Enable */ 160 #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ 161 #define RRFST 0x0400 /* Right-First Data Order */ 162 163 /* SPORT_STAT Masks */ 164 #define RXNE 0x0001 /* RX FIFO Not Empty Status */ 165 #define RUVF 0x0002 /* RX Underflow Status */ 166 #define ROVF 0x0004 /* RX Overflow Status */ 167 #define TXF 0x0008 /* TX FIFO Full Status */ 168 #define TUVF 0x0010 /* TX Underflow Status */ 169 #define TOVF 0x0020 /* TX Overflow Status */ 170 #define TXHRE 0x0040 /* TX Hold Register Empty */ 171 172 /* SPORT_MCMC1 Masks */ 173 #define SP_WOFF 0x03FF /* Multichannel Window Offset Field */ 174 #define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x) 175 #define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x) 176 #define SP_WSIZE 0xF000 /* Multichannel Window Size Field */ 177 #define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x) 178 #define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x) 179 180 /* SPORT_MCMC2 Masks */ 181 #define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */ 182 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ 183 #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ 184 #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ 185 #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ 186 #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ 187 #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ 188 #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ 189 #define MFD 0xF000 /* Multichannel Frame Delay */ 190 #define DP_MFD(x) BFIN_DEPOSIT(MFD, x) 191 #define EX_MFD(x) BFIN_EXTRACT(MFD, x) 192 193 #endif 194