1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 */
5 #ifndef _ASM_INST_H
6 #define _ASM_INST_H
7
8 #include <linux/bitops.h>
9 #include <linux/types.h>
10 #include <asm/asm.h>
11 #include <asm/ptrace.h>
12
13 #define INSN_NOP 0x03400000
14 #define INSN_BREAK 0x002a0000
15
16 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
17 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
18 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000
19 #define ADDR_IMMMASK_ORI 0x0000000000000FFF
20 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
21
22 #define ADDR_IMMSHIFT_LU52ID 52
23 #define ADDR_IMMSBIDX_LU52ID 11
24 #define ADDR_IMMSHIFT_LU32ID 32
25 #define ADDR_IMMSBIDX_LU32ID 19
26 #define ADDR_IMMSHIFT_LU12IW 12
27 #define ADDR_IMMSBIDX_LU12IW 19
28 #define ADDR_IMMSHIFT_ORI 0
29 #define ADDR_IMMSBIDX_ORI 63
30 #define ADDR_IMMSHIFT_ADDU16ID 16
31 #define ADDR_IMMSBIDX_ADDU16ID 15
32
33 #define ADDR_IMM(addr, INSN) \
34 (sign_extend64(((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN), ADDR_IMMSBIDX_##INSN))
35
36 enum reg0i15_op {
37 break_op = 0x54,
38 };
39
40 enum reg0i26_op {
41 b_op = 0x14,
42 bl_op = 0x15,
43 };
44
45 enum reg1i20_op {
46 lu12iw_op = 0x0a,
47 lu32id_op = 0x0b,
48 pcaddi_op = 0x0c,
49 pcalau12i_op = 0x0d,
50 pcaddu12i_op = 0x0e,
51 pcaddu18i_op = 0x0f,
52 };
53
54 enum reg1i21_op {
55 beqz_op = 0x10,
56 bnez_op = 0x11,
57 bceqz_op = 0x12, /* bits[9:8] = 0x00 */
58 bcnez_op = 0x12, /* bits[9:8] = 0x01 */
59 };
60
61 enum reg2_op {
62 revb2h_op = 0x0c,
63 revb4h_op = 0x0d,
64 revb2w_op = 0x0e,
65 revbd_op = 0x0f,
66 revh2w_op = 0x10,
67 revhd_op = 0x11,
68 extwh_op = 0x16,
69 extwb_op = 0x17,
70 iocsrrdb_op = 0x19200,
71 iocsrrdh_op = 0x19201,
72 iocsrrdw_op = 0x19202,
73 iocsrrdd_op = 0x19203,
74 iocsrwrb_op = 0x19204,
75 iocsrwrh_op = 0x19205,
76 iocsrwrw_op = 0x19206,
77 iocsrwrd_op = 0x19207,
78 };
79
80 enum reg2i5_op {
81 slliw_op = 0x81,
82 srliw_op = 0x89,
83 sraiw_op = 0x91,
84 };
85
86 enum reg2i6_op {
87 sllid_op = 0x41,
88 srlid_op = 0x45,
89 sraid_op = 0x49,
90 };
91
92 enum reg2i12_op {
93 addiw_op = 0x0a,
94 addid_op = 0x0b,
95 lu52id_op = 0x0c,
96 andi_op = 0x0d,
97 ori_op = 0x0e,
98 xori_op = 0x0f,
99 ldb_op = 0xa0,
100 ldh_op = 0xa1,
101 ldw_op = 0xa2,
102 ldd_op = 0xa3,
103 stb_op = 0xa4,
104 sth_op = 0xa5,
105 stw_op = 0xa6,
106 std_op = 0xa7,
107 ldbu_op = 0xa8,
108 ldhu_op = 0xa9,
109 ldwu_op = 0xaa,
110 flds_op = 0xac,
111 fsts_op = 0xad,
112 fldd_op = 0xae,
113 fstd_op = 0xaf,
114 };
115
116 enum reg2i14_op {
117 llw_op = 0x20,
118 scw_op = 0x21,
119 lld_op = 0x22,
120 scd_op = 0x23,
121 ldptrw_op = 0x24,
122 stptrw_op = 0x25,
123 ldptrd_op = 0x26,
124 stptrd_op = 0x27,
125 };
126
127 enum reg2i16_op {
128 jirl_op = 0x13,
129 beq_op = 0x16,
130 bne_op = 0x17,
131 blt_op = 0x18,
132 bge_op = 0x19,
133 bltu_op = 0x1a,
134 bgeu_op = 0x1b,
135 };
136
137 enum reg2bstrd_op {
138 bstrinsd_op = 0x2,
139 bstrpickd_op = 0x3,
140 };
141
142 enum reg3_op {
143 asrtle_op = 0x02,
144 asrtgt_op = 0x03,
145 addw_op = 0x20,
146 addd_op = 0x21,
147 subw_op = 0x22,
148 subd_op = 0x23,
149 nor_op = 0x28,
150 and_op = 0x29,
151 or_op = 0x2a,
152 xor_op = 0x2b,
153 orn_op = 0x2c,
154 andn_op = 0x2d,
155 sllw_op = 0x2e,
156 srlw_op = 0x2f,
157 sraw_op = 0x30,
158 slld_op = 0x31,
159 srld_op = 0x32,
160 srad_op = 0x33,
161 mulw_op = 0x38,
162 mulhw_op = 0x39,
163 mulhwu_op = 0x3a,
164 muld_op = 0x3b,
165 mulhd_op = 0x3c,
166 mulhdu_op = 0x3d,
167 divw_op = 0x40,
168 modw_op = 0x41,
169 divwu_op = 0x42,
170 modwu_op = 0x43,
171 divd_op = 0x44,
172 modd_op = 0x45,
173 divdu_op = 0x46,
174 moddu_op = 0x47,
175 ldxb_op = 0x7000,
176 ldxh_op = 0x7008,
177 ldxw_op = 0x7010,
178 ldxd_op = 0x7018,
179 stxb_op = 0x7020,
180 stxh_op = 0x7028,
181 stxw_op = 0x7030,
182 stxd_op = 0x7038,
183 ldxbu_op = 0x7040,
184 ldxhu_op = 0x7048,
185 ldxwu_op = 0x7050,
186 fldxs_op = 0x7060,
187 fldxd_op = 0x7068,
188 fstxs_op = 0x7070,
189 fstxd_op = 0x7078,
190 amswapw_op = 0x70c0,
191 amswapd_op = 0x70c1,
192 amaddw_op = 0x70c2,
193 amaddd_op = 0x70c3,
194 amandw_op = 0x70c4,
195 amandd_op = 0x70c5,
196 amorw_op = 0x70c6,
197 amord_op = 0x70c7,
198 amxorw_op = 0x70c8,
199 amxord_op = 0x70c9,
200 ammaxw_op = 0x70ca,
201 ammaxd_op = 0x70cb,
202 amminw_op = 0x70cc,
203 ammind_op = 0x70cd,
204 ammaxwu_op = 0x70ce,
205 ammaxdu_op = 0x70cf,
206 amminwu_op = 0x70d0,
207 ammindu_op = 0x70d1,
208 amswapdbw_op = 0x70d2,
209 amswapdbd_op = 0x70d3,
210 amadddbw_op = 0x70d4,
211 amadddbd_op = 0x70d5,
212 amanddbw_op = 0x70d6,
213 amanddbd_op = 0x70d7,
214 amordbw_op = 0x70d8,
215 amordbd_op = 0x70d9,
216 amxordbw_op = 0x70da,
217 amxordbd_op = 0x70db,
218 ammaxdbw_op = 0x70dc,
219 ammaxdbd_op = 0x70dd,
220 ammindbw_op = 0x70de,
221 ammindbd_op = 0x70df,
222 ammaxdbwu_op = 0x70e0,
223 ammaxdbdu_op = 0x70e1,
224 ammindbwu_op = 0x70e2,
225 ammindbdu_op = 0x70e3,
226 fldgts_op = 0x70e8,
227 fldgtd_op = 0x70e9,
228 fldles_op = 0x70ea,
229 fldled_op = 0x70eb,
230 fstgts_op = 0x70ec,
231 fstgtd_op = 0x70ed,
232 fstles_op = 0x70ee,
233 fstled_op = 0x70ef,
234 ldgtb_op = 0x70f0,
235 ldgth_op = 0x70f1,
236 ldgtw_op = 0x70f2,
237 ldgtd_op = 0x70f3,
238 ldleb_op = 0x70f4,
239 ldleh_op = 0x70f5,
240 ldlew_op = 0x70f6,
241 ldled_op = 0x70f7,
242 stgtb_op = 0x70f8,
243 stgth_op = 0x70f9,
244 stgtw_op = 0x70fa,
245 stgtd_op = 0x70fb,
246 stleb_op = 0x70fc,
247 stleh_op = 0x70fd,
248 stlew_op = 0x70fe,
249 stled_op = 0x70ff,
250 };
251
252 enum reg3sa2_op {
253 alslw_op = 0x02,
254 alslwu_op = 0x03,
255 alsld_op = 0x16,
256 };
257
258 struct reg0i15_format {
259 unsigned int immediate : 15;
260 unsigned int opcode : 17;
261 };
262
263 struct reg0i26_format {
264 unsigned int immediate_h : 10;
265 unsigned int immediate_l : 16;
266 unsigned int opcode : 6;
267 };
268
269 struct reg1i20_format {
270 unsigned int rd : 5;
271 unsigned int immediate : 20;
272 unsigned int opcode : 7;
273 };
274
275 struct reg1i21_format {
276 unsigned int immediate_h : 5;
277 unsigned int rj : 5;
278 unsigned int immediate_l : 16;
279 unsigned int opcode : 6;
280 };
281
282 struct reg2_format {
283 unsigned int rd : 5;
284 unsigned int rj : 5;
285 unsigned int opcode : 22;
286 };
287
288 struct reg2i5_format {
289 unsigned int rd : 5;
290 unsigned int rj : 5;
291 unsigned int immediate : 5;
292 unsigned int opcode : 17;
293 };
294
295 struct reg2i6_format {
296 unsigned int rd : 5;
297 unsigned int rj : 5;
298 unsigned int immediate : 6;
299 unsigned int opcode : 16;
300 };
301
302 struct reg2i12_format {
303 unsigned int rd : 5;
304 unsigned int rj : 5;
305 unsigned int immediate : 12;
306 unsigned int opcode : 10;
307 };
308
309 struct reg2i14_format {
310 unsigned int rd : 5;
311 unsigned int rj : 5;
312 unsigned int immediate : 14;
313 unsigned int opcode : 8;
314 };
315
316 struct reg2i16_format {
317 unsigned int rd : 5;
318 unsigned int rj : 5;
319 unsigned int immediate : 16;
320 unsigned int opcode : 6;
321 };
322
323 struct reg2bstrd_format {
324 unsigned int rd : 5;
325 unsigned int rj : 5;
326 unsigned int lsbd : 6;
327 unsigned int msbd : 6;
328 unsigned int opcode : 10;
329 };
330
331 struct reg2csr_format {
332 unsigned int rd : 5;
333 unsigned int rj : 5;
334 unsigned int csr : 14;
335 unsigned int opcode : 8;
336 };
337
338 struct reg3_format {
339 unsigned int rd : 5;
340 unsigned int rj : 5;
341 unsigned int rk : 5;
342 unsigned int opcode : 17;
343 };
344
345 struct reg3sa2_format {
346 unsigned int rd : 5;
347 unsigned int rj : 5;
348 unsigned int rk : 5;
349 unsigned int immediate : 2;
350 unsigned int opcode : 15;
351 };
352
353 union loongarch_instruction {
354 unsigned int word;
355 struct reg0i15_format reg0i15_format;
356 struct reg0i26_format reg0i26_format;
357 struct reg1i20_format reg1i20_format;
358 struct reg1i21_format reg1i21_format;
359 struct reg2_format reg2_format;
360 struct reg2i5_format reg2i5_format;
361 struct reg2i6_format reg2i6_format;
362 struct reg2i12_format reg2i12_format;
363 struct reg2i14_format reg2i14_format;
364 struct reg2i16_format reg2i16_format;
365 struct reg2bstrd_format reg2bstrd_format;
366 struct reg2csr_format reg2csr_format;
367 struct reg3_format reg3_format;
368 struct reg3sa2_format reg3sa2_format;
369 };
370
371 #define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
372
373 enum loongarch_gpr {
374 LOONGARCH_GPR_ZERO = 0,
375 LOONGARCH_GPR_RA = 1,
376 LOONGARCH_GPR_TP = 2,
377 LOONGARCH_GPR_SP = 3,
378 LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */
379 LOONGARCH_GPR_A1, /* Reused as V1 for return value */
380 LOONGARCH_GPR_A2,
381 LOONGARCH_GPR_A3,
382 LOONGARCH_GPR_A4,
383 LOONGARCH_GPR_A5,
384 LOONGARCH_GPR_A6,
385 LOONGARCH_GPR_A7,
386 LOONGARCH_GPR_T0 = 12,
387 LOONGARCH_GPR_T1,
388 LOONGARCH_GPR_T2,
389 LOONGARCH_GPR_T3,
390 LOONGARCH_GPR_T4,
391 LOONGARCH_GPR_T5,
392 LOONGARCH_GPR_T6,
393 LOONGARCH_GPR_T7,
394 LOONGARCH_GPR_T8,
395 LOONGARCH_GPR_FP = 22,
396 LOONGARCH_GPR_S0 = 23,
397 LOONGARCH_GPR_S1,
398 LOONGARCH_GPR_S2,
399 LOONGARCH_GPR_S3,
400 LOONGARCH_GPR_S4,
401 LOONGARCH_GPR_S5,
402 LOONGARCH_GPR_S6,
403 LOONGARCH_GPR_S7,
404 LOONGARCH_GPR_S8,
405 LOONGARCH_GPR_MAX
406 };
407
408 #define is_imm12_negative(val) is_imm_negative(val, 12)
409
is_imm_negative(unsigned long val,unsigned int bit)410 static inline bool is_imm_negative(unsigned long val, unsigned int bit)
411 {
412 return val & (1UL << (bit - 1));
413 }
414
is_break_ins(union loongarch_instruction * ip)415 static inline bool is_break_ins(union loongarch_instruction *ip)
416 {
417 return ip->reg0i15_format.opcode == break_op;
418 }
419
is_pc_ins(union loongarch_instruction * ip)420 static inline bool is_pc_ins(union loongarch_instruction *ip)
421 {
422 return ip->reg1i20_format.opcode >= pcaddi_op &&
423 ip->reg1i20_format.opcode <= pcaddu18i_op;
424 }
425
is_branch_ins(union loongarch_instruction * ip)426 static inline bool is_branch_ins(union loongarch_instruction *ip)
427 {
428 return ip->reg1i21_format.opcode >= beqz_op &&
429 ip->reg1i21_format.opcode <= bgeu_op;
430 }
431
is_ra_save_ins(union loongarch_instruction * ip)432 static inline bool is_ra_save_ins(union loongarch_instruction *ip)
433 {
434 /* st.d $ra, $sp, offset */
435 return ip->reg2i12_format.opcode == std_op &&
436 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
437 ip->reg2i12_format.rd == LOONGARCH_GPR_RA &&
438 !is_imm12_negative(ip->reg2i12_format.immediate);
439 }
440
is_stack_alloc_ins(union loongarch_instruction * ip)441 static inline bool is_stack_alloc_ins(union loongarch_instruction *ip)
442 {
443 /* addi.d $sp, $sp, -imm */
444 return ip->reg2i12_format.opcode == addid_op &&
445 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
446 ip->reg2i12_format.rd == LOONGARCH_GPR_SP &&
447 is_imm12_negative(ip->reg2i12_format.immediate);
448 }
449
is_self_loop_ins(union loongarch_instruction * ip,struct pt_regs * regs)450 static inline bool is_self_loop_ins(union loongarch_instruction *ip, struct pt_regs *regs)
451 {
452 switch (ip->reg0i26_format.opcode) {
453 case b_op:
454 case bl_op:
455 if (ip->reg0i26_format.immediate_l == 0
456 && ip->reg0i26_format.immediate_h == 0)
457 return true;
458 }
459
460 switch (ip->reg1i21_format.opcode) {
461 case beqz_op:
462 case bnez_op:
463 case bceqz_op:
464 if (ip->reg1i21_format.immediate_l == 0
465 && ip->reg1i21_format.immediate_h == 0)
466 return true;
467 }
468
469 switch (ip->reg2i16_format.opcode) {
470 case beq_op:
471 case bne_op:
472 case blt_op:
473 case bge_op:
474 case bltu_op:
475 case bgeu_op:
476 if (ip->reg2i16_format.immediate == 0)
477 return true;
478 break;
479 case jirl_op:
480 if (regs->regs[ip->reg2i16_format.rj] +
481 ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip)
482 return true;
483 }
484
485 return false;
486 }
487
488 void simu_pc(struct pt_regs *regs, union loongarch_instruction insn);
489 void simu_branch(struct pt_regs *regs, union loongarch_instruction insn);
490
491 bool insns_not_supported(union loongarch_instruction insn);
492 bool insns_need_simulation(union loongarch_instruction insn);
493 void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs);
494
495 int larch_insn_read(void *addr, u32 *insnp);
496 int larch_insn_write(void *addr, u32 insn);
497 int larch_insn_patch_text(void *addr, u32 insn);
498
499 u32 larch_insn_gen_nop(void);
500 u32 larch_insn_gen_b(unsigned long pc, unsigned long dest);
501 u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest);
502
503 u32 larch_insn_gen_break(int imm);
504
505 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk);
506 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
507
508 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
509 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
510 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
511 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
512
signed_imm_check(long val,unsigned int bit)513 static inline bool signed_imm_check(long val, unsigned int bit)
514 {
515 return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1));
516 }
517
unsigned_imm_check(unsigned long val,unsigned int bit)518 static inline bool unsigned_imm_check(unsigned long val, unsigned int bit)
519 {
520 return val < (1UL << bit);
521 }
522
523 #define DEF_EMIT_REG0I15_FORMAT(NAME, OP) \
524 static inline void emit_##NAME(union loongarch_instruction *insn, \
525 int imm) \
526 { \
527 insn->reg0i15_format.opcode = OP; \
528 insn->reg0i15_format.immediate = imm; \
529 }
530
531 DEF_EMIT_REG0I15_FORMAT(break, break_op)
532
533 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \
534 static inline void emit_##NAME(union loongarch_instruction *insn, \
535 int offset) \
536 { \
537 unsigned int immediate_l, immediate_h; \
538 \
539 immediate_l = offset & 0xffff; \
540 offset >>= 16; \
541 immediate_h = offset & 0x3ff; \
542 \
543 insn->reg0i26_format.opcode = OP; \
544 insn->reg0i26_format.immediate_l = immediate_l; \
545 insn->reg0i26_format.immediate_h = immediate_h; \
546 }
547
548 DEF_EMIT_REG0I26_FORMAT(b, b_op)
549 DEF_EMIT_REG0I26_FORMAT(bl, bl_op)
550
551 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \
552 static inline void emit_##NAME(union loongarch_instruction *insn, \
553 enum loongarch_gpr rd, int imm) \
554 { \
555 insn->reg1i20_format.opcode = OP; \
556 insn->reg1i20_format.immediate = imm; \
557 insn->reg1i20_format.rd = rd; \
558 }
559
560 DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op)
561 DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op)
562 DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op)
563
564 #define DEF_EMIT_REG2_FORMAT(NAME, OP) \
565 static inline void emit_##NAME(union loongarch_instruction *insn, \
566 enum loongarch_gpr rd, \
567 enum loongarch_gpr rj) \
568 { \
569 insn->reg2_format.opcode = OP; \
570 insn->reg2_format.rd = rd; \
571 insn->reg2_format.rj = rj; \
572 }
573
574 DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op)
575 DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op)
576 DEF_EMIT_REG2_FORMAT(revbd, revbd_op)
577 DEF_EMIT_REG2_FORMAT(extwh, extwh_op)
578 DEF_EMIT_REG2_FORMAT(extwb, extwb_op)
579
580 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \
581 static inline void emit_##NAME(union loongarch_instruction *insn, \
582 enum loongarch_gpr rd, \
583 enum loongarch_gpr rj, \
584 int imm) \
585 { \
586 insn->reg2i5_format.opcode = OP; \
587 insn->reg2i5_format.immediate = imm; \
588 insn->reg2i5_format.rd = rd; \
589 insn->reg2i5_format.rj = rj; \
590 }
591
592 DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op)
593 DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op)
594 DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op)
595
596 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \
597 static inline void emit_##NAME(union loongarch_instruction *insn, \
598 enum loongarch_gpr rd, \
599 enum loongarch_gpr rj, \
600 int imm) \
601 { \
602 insn->reg2i6_format.opcode = OP; \
603 insn->reg2i6_format.immediate = imm; \
604 insn->reg2i6_format.rd = rd; \
605 insn->reg2i6_format.rj = rj; \
606 }
607
608 DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op)
609 DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op)
610 DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op)
611
612 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \
613 static inline void emit_##NAME(union loongarch_instruction *insn, \
614 enum loongarch_gpr rd, \
615 enum loongarch_gpr rj, \
616 int imm) \
617 { \
618 insn->reg2i12_format.opcode = OP; \
619 insn->reg2i12_format.immediate = imm; \
620 insn->reg2i12_format.rd = rd; \
621 insn->reg2i12_format.rj = rj; \
622 }
623
624 DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op)
625 DEF_EMIT_REG2I12_FORMAT(addid, addid_op)
626 DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op)
627 DEF_EMIT_REG2I12_FORMAT(andi, andi_op)
628 DEF_EMIT_REG2I12_FORMAT(ori, ori_op)
629 DEF_EMIT_REG2I12_FORMAT(xori, xori_op)
630 DEF_EMIT_REG2I12_FORMAT(ldb, ldb_op)
631 DEF_EMIT_REG2I12_FORMAT(ldh, ldh_op)
632 DEF_EMIT_REG2I12_FORMAT(ldw, ldw_op)
633 DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op)
634 DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op)
635 DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op)
636 DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op)
637 DEF_EMIT_REG2I12_FORMAT(stb, stb_op)
638 DEF_EMIT_REG2I12_FORMAT(sth, sth_op)
639 DEF_EMIT_REG2I12_FORMAT(stw, stw_op)
640 DEF_EMIT_REG2I12_FORMAT(std, std_op)
641
642 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \
643 static inline void emit_##NAME(union loongarch_instruction *insn, \
644 enum loongarch_gpr rd, \
645 enum loongarch_gpr rj, \
646 int imm) \
647 { \
648 insn->reg2i14_format.opcode = OP; \
649 insn->reg2i14_format.immediate = imm; \
650 insn->reg2i14_format.rd = rd; \
651 insn->reg2i14_format.rj = rj; \
652 }
653
654 DEF_EMIT_REG2I14_FORMAT(llw, llw_op)
655 DEF_EMIT_REG2I14_FORMAT(scw, scw_op)
656 DEF_EMIT_REG2I14_FORMAT(lld, lld_op)
657 DEF_EMIT_REG2I14_FORMAT(scd, scd_op)
658 DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op)
659 DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op)
660 DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op)
661 DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op)
662
663 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \
664 static inline void emit_##NAME(union loongarch_instruction *insn, \
665 enum loongarch_gpr rj, \
666 enum loongarch_gpr rd, \
667 int offset) \
668 { \
669 insn->reg2i16_format.opcode = OP; \
670 insn->reg2i16_format.immediate = offset; \
671 insn->reg2i16_format.rj = rj; \
672 insn->reg2i16_format.rd = rd; \
673 }
674
675 DEF_EMIT_REG2I16_FORMAT(beq, beq_op)
676 DEF_EMIT_REG2I16_FORMAT(bne, bne_op)
677 DEF_EMIT_REG2I16_FORMAT(blt, blt_op)
678 DEF_EMIT_REG2I16_FORMAT(bge, bge_op)
679 DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op)
680 DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op)
681 DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op)
682
683 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \
684 static inline void emit_##NAME(union loongarch_instruction *insn, \
685 enum loongarch_gpr rd, \
686 enum loongarch_gpr rj, \
687 int msbd, \
688 int lsbd) \
689 { \
690 insn->reg2bstrd_format.opcode = OP; \
691 insn->reg2bstrd_format.msbd = msbd; \
692 insn->reg2bstrd_format.lsbd = lsbd; \
693 insn->reg2bstrd_format.rj = rj; \
694 insn->reg2bstrd_format.rd = rd; \
695 }
696
697 DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op)
698
699 #define DEF_EMIT_REG3_FORMAT(NAME, OP) \
700 static inline void emit_##NAME(union loongarch_instruction *insn, \
701 enum loongarch_gpr rd, \
702 enum loongarch_gpr rj, \
703 enum loongarch_gpr rk) \
704 { \
705 insn->reg3_format.opcode = OP; \
706 insn->reg3_format.rd = rd; \
707 insn->reg3_format.rj = rj; \
708 insn->reg3_format.rk = rk; \
709 }
710
711 DEF_EMIT_REG3_FORMAT(addw, addw_op)
712 DEF_EMIT_REG3_FORMAT(addd, addd_op)
713 DEF_EMIT_REG3_FORMAT(subd, subd_op)
714 DEF_EMIT_REG3_FORMAT(muld, muld_op)
715 DEF_EMIT_REG3_FORMAT(divd, divd_op)
716 DEF_EMIT_REG3_FORMAT(modd, modd_op)
717 DEF_EMIT_REG3_FORMAT(divdu, divdu_op)
718 DEF_EMIT_REG3_FORMAT(moddu, moddu_op)
719 DEF_EMIT_REG3_FORMAT(and, and_op)
720 DEF_EMIT_REG3_FORMAT(or, or_op)
721 DEF_EMIT_REG3_FORMAT(xor, xor_op)
722 DEF_EMIT_REG3_FORMAT(sllw, sllw_op)
723 DEF_EMIT_REG3_FORMAT(slld, slld_op)
724 DEF_EMIT_REG3_FORMAT(srlw, srlw_op)
725 DEF_EMIT_REG3_FORMAT(srld, srld_op)
726 DEF_EMIT_REG3_FORMAT(sraw, sraw_op)
727 DEF_EMIT_REG3_FORMAT(srad, srad_op)
728 DEF_EMIT_REG3_FORMAT(ldxb, ldxb_op)
729 DEF_EMIT_REG3_FORMAT(ldxh, ldxh_op)
730 DEF_EMIT_REG3_FORMAT(ldxw, ldxw_op)
731 DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op)
732 DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op)
733 DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op)
734 DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op)
735 DEF_EMIT_REG3_FORMAT(stxb, stxb_op)
736 DEF_EMIT_REG3_FORMAT(stxh, stxh_op)
737 DEF_EMIT_REG3_FORMAT(stxw, stxw_op)
738 DEF_EMIT_REG3_FORMAT(stxd, stxd_op)
739 DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)
740 DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)
741 DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
742 DEF_EMIT_REG3_FORMAT(amandd, amandd_op)
743 DEF_EMIT_REG3_FORMAT(amorw, amorw_op)
744 DEF_EMIT_REG3_FORMAT(amord, amord_op)
745 DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)
746 DEF_EMIT_REG3_FORMAT(amxord, amxord_op)
747 DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
748 DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
749
750 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \
751 static inline void emit_##NAME(union loongarch_instruction *insn, \
752 enum loongarch_gpr rd, \
753 enum loongarch_gpr rj, \
754 enum loongarch_gpr rk, \
755 int imm) \
756 { \
757 insn->reg3sa2_format.opcode = OP; \
758 insn->reg3sa2_format.immediate = imm; \
759 insn->reg3sa2_format.rd = rd; \
760 insn->reg3sa2_format.rj = rj; \
761 insn->reg3sa2_format.rk = rk; \
762 }
763
764 DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op)
765
766 struct pt_regs;
767
768 void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc);
769 unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign);
770 unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n);
771
772 #endif /* _ASM_INST_H */
773