1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003-2008 Joseph Koshy
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/types.h>
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/pmc.h>
33 #include <sys/syscall.h>
34
35 #include <ctype.h>
36 #include <errno.h>
37 #include <err.h>
38 #include <fcntl.h>
39 #include <pmc.h>
40 #include <stdio.h>
41 #include <stdlib.h>
42 #include <string.h>
43 #include <strings.h>
44 #include <sysexits.h>
45 #include <unistd.h>
46
47 #include "libpmcinternal.h"
48
49 /* Function prototypes */
50 #if defined(__amd64__) || defined(__i386__)
51 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
52 struct pmc_op_pmcallocate *_pmc_config);
53 static int ibs_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
54 struct pmc_op_pmcallocate *_pmc_config);
55 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
57 #endif
58 #if defined(__arm__)
59 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
60 struct pmc_op_pmcallocate *_pmc_config);
61 #endif
62 #if defined(__aarch64__)
63 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
64 struct pmc_op_pmcallocate *_pmc_config);
65 static int cmn600_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
66 struct pmc_op_pmcallocate *_pmc_config);
67 static int dmc620_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
68 struct pmc_op_pmcallocate *_pmc_config);
69 #endif
70 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
71 struct pmc_op_pmcallocate *_pmc_config);
72
73 #if defined(__powerpc__)
74 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec,
75 struct pmc_op_pmcallocate *_pmc_config);
76 #endif /* __powerpc__ */
77
78 #define PMC_CALL(op, params) syscall(pmc_syscall, (op), (params))
79
80 /*
81 * Event aliases provide a way for the user to ask for generic events
82 * like "cache-misses", or "instructions-retired". These aliases are
83 * mapped to the appropriate canonical event descriptions using a
84 * lookup table.
85 */
86 struct pmc_event_alias {
87 const char *pm_alias;
88 const char *pm_spec;
89 };
90
91 static const struct pmc_event_alias *pmc_mdep_event_aliases;
92
93 /*
94 * The pmc_event_descr structure maps symbolic names known to the user
95 * to integer codes used by the PMC KLD.
96 */
97 struct pmc_event_descr {
98 const char *pm_ev_name;
99 enum pmc_event pm_ev_code;
100 };
101
102 /*
103 * The pmc_class_descr structure maps class name prefixes for
104 * event names to event tables and other PMC class data.
105 */
106 struct pmc_class_descr {
107 const char *pm_evc_name;
108 size_t pm_evc_name_size;
109 enum pmc_class pm_evc_class;
110 const struct pmc_event_descr *pm_evc_event_table;
111 size_t pm_evc_event_table_size;
112 int (*pm_evc_allocate_pmc)(enum pmc_event _pe,
113 char *_ctrspec, struct pmc_op_pmcallocate *_pa);
114 };
115
116 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0]))
117 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
118
119 #undef __PMC_EV
120 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
121
122 /*
123 * PMC_CLASSDEP_TABLE(NAME, CLASS)
124 *
125 * Define a table mapping event names and aliases to HWPMC event IDs.
126 */
127 #define PMC_CLASSDEP_TABLE(N, C) \
128 static const struct pmc_event_descr N##_event_table[] = \
129 { \
130 __PMC_EV_##C() \
131 }
132
133 PMC_CLASSDEP_TABLE(iaf, IAF);
134 PMC_CLASSDEP_TABLE(k8, K8);
135 PMC_CLASSDEP_TABLE(ibs, IBS);
136 PMC_CLASSDEP_TABLE(armv7, ARMV7);
137 PMC_CLASSDEP_TABLE(armv8, ARMV8);
138 PMC_CLASSDEP_TABLE(cmn600_pmu, CMN600_PMU);
139 PMC_CLASSDEP_TABLE(dmc620_pmu_cd2, DMC620_PMU_CD2);
140 PMC_CLASSDEP_TABLE(dmc620_pmu_c, DMC620_PMU_C);
141 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
142 PMC_CLASSDEP_TABLE(ppc970, PPC970);
143 PMC_CLASSDEP_TABLE(e500, E500);
144
145 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
146
147 #undef __PMC_EV_ALIAS
148 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
149
150 /*
151 * TODO: Factor out the __PMC_EV_ARMV7/8 list into a single separate table
152 * rather than duplicating for each core.
153 */
154
155 static const struct pmc_event_descr cortex_a8_event_table[] =
156 {
157 __PMC_EV_ALIAS_ARMV7_CORTEX_A8()
158 __PMC_EV_ARMV7()
159 };
160
161 static const struct pmc_event_descr cortex_a9_event_table[] =
162 {
163 __PMC_EV_ALIAS_ARMV7_CORTEX_A9()
164 __PMC_EV_ARMV7()
165 };
166
167 static const struct pmc_event_descr cortex_a53_event_table[] =
168 {
169 __PMC_EV_ALIAS_ARMV8_CORTEX_A53()
170 __PMC_EV_ARMV8()
171 };
172
173 static const struct pmc_event_descr cortex_a57_event_table[] =
174 {
175 __PMC_EV_ALIAS_ARMV8_CORTEX_A57()
176 __PMC_EV_ARMV8()
177 };
178
179 static const struct pmc_event_descr cortex_a76_event_table[] =
180 {
181 __PMC_EV_ALIAS_ARMV8_CORTEX_A76()
182 __PMC_EV_ARMV8()
183 };
184
185 static const struct pmc_event_descr tsc_event_table[] =
186 {
187 __PMC_EV_ALIAS_TSC()
188 };
189
190 #undef PMC_CLASS_TABLE_DESC
191 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \
192 static const struct pmc_class_descr NAME##_class_table_descr = \
193 { \
194 .pm_evc_name = #CLASS "-", \
195 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \
196 .pm_evc_class = PMC_CLASS_##CLASS , \
197 .pm_evc_event_table = EVENTS##_event_table , \
198 .pm_evc_event_table_size = \
199 PMC_EVENT_TABLE_SIZE(EVENTS), \
200 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
201 }
202
203 #if defined(__i386__) || defined(__amd64__)
204 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
205 PMC_CLASS_TABLE_DESC(ibs, IBS, ibs, ibs);
206 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
207 #endif
208 #if defined(__arm__)
209 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7);
210 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7);
211 #endif
212 #if defined(__aarch64__)
213 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64);
214 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64);
215 PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64);
216 PMC_CLASS_TABLE_DESC(cmn600_pmu, CMN600_PMU, cmn600_pmu, cmn600_pmu);
217 PMC_CLASS_TABLE_DESC(dmc620_pmu_cd2, DMC620_PMU_CD2, dmc620_pmu_cd2, dmc620_pmu);
218 PMC_CLASS_TABLE_DESC(dmc620_pmu_c, DMC620_PMU_C, dmc620_pmu_c, dmc620_pmu);
219 #endif
220 #if defined(__powerpc__)
221 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc);
222 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc);
223 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc);
224 #endif
225
226 static struct pmc_class_descr soft_class_table_descr =
227 {
228 .pm_evc_name = "SOFT-",
229 .pm_evc_name_size = sizeof("SOFT-") - 1,
230 .pm_evc_class = PMC_CLASS_SOFT,
231 .pm_evc_event_table = NULL,
232 .pm_evc_event_table_size = 0,
233 .pm_evc_allocate_pmc = soft_allocate_pmc
234 };
235
236 #undef PMC_CLASS_TABLE_DESC
237
238 static const struct pmc_class_descr **pmc_class_table;
239 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass
240
241 /*
242 * Mapping tables, mapping enumeration values to human readable
243 * strings.
244 */
245
246 static const char * pmc_capability_names[] = {
247 #undef __PMC_CAP
248 #define __PMC_CAP(N,V,D) #N ,
249 __PMC_CAPS()
250 };
251
252 struct pmc_class_map {
253 enum pmc_class pm_class;
254 const char *pm_name;
255 };
256
257 static const struct pmc_class_map pmc_class_names[] = {
258 #undef __PMC_CLASS
259 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } ,
260 __PMC_CLASSES()
261 };
262
263 struct pmc_cputype_map {
264 enum pmc_cputype pm_cputype;
265 const char *pm_name;
266 };
267
268 static const struct pmc_cputype_map pmc_cputype_names[] = {
269 #undef __PMC_CPU
270 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
271 __PMC_CPUS()
272 };
273
274 static const char * pmc_disposition_names[] = {
275 #undef __PMC_DISP
276 #define __PMC_DISP(D) #D ,
277 __PMC_DISPOSITIONS()
278 };
279
280 static const char * pmc_mode_names[] = {
281 #undef __PMC_MODE
282 #define __PMC_MODE(M,N) #M ,
283 __PMC_MODES()
284 };
285
286 static const char * pmc_state_names[] = {
287 #undef __PMC_STATE
288 #define __PMC_STATE(S) #S ,
289 __PMC_STATES()
290 };
291
292 /*
293 * Filled in by pmc_init().
294 */
295 static int pmc_syscall = -1;
296 static struct pmc_cpuinfo cpu_info;
297 static struct pmc_op_getdyneventinfo soft_event_info;
298
299 /* Event masks for events */
300 struct pmc_masks {
301 const char *pm_name;
302 const uint64_t pm_value;
303 };
304 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
305 #define NULLMASK { .pm_name = NULL }
306
307 #if defined(__amd64__) || defined(__i386__)
308 static int
pmc_parse_mask(const struct pmc_masks * pmask,char * p,uint64_t * evmask)309 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
310 {
311 const struct pmc_masks *pm;
312 char *q, *r;
313 int c;
314
315 if (pmask == NULL) /* no mask keywords */
316 return (-1);
317 q = strchr(p, '='); /* skip '=' */
318 if (*++q == '\0') /* no more data */
319 return (-1);
320 c = 0; /* count of mask keywords seen */
321 while ((r = strsep(&q, "+")) != NULL) {
322 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
323 pm++)
324 ;
325 if (pm->pm_name == NULL) /* not found */
326 return (-1);
327 *evmask |= pm->pm_value;
328 c++;
329 }
330 return (c);
331 }
332 #endif
333
334 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0)
335 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
336 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
337
338 #if defined(__amd64__) || defined(__i386__)
339 /*
340 * AMD K8 PMCs.
341 *
342 */
343
344 static struct pmc_event_alias k8_aliases[] = {
345 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),
346 EV_ALIAS("branch-mispredicts",
347 "k8-fr-retired-taken-branches-mispredicted"),
348 EV_ALIAS("cycles", "tsc"),
349 EV_ALIAS("dc-misses", "k8-dc-miss"),
350 EV_ALIAS("ic-misses", "k8-ic-miss"),
351 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"),
352 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"),
353 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"),
354 EV_ALIAS(NULL, NULL)
355 };
356
357 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
358
359 /*
360 * Parsing tables
361 */
362
363 /* fp dispatched fpu ops */
364 static const struct pmc_masks k8_mask_fdfo[] = {
365 __K8MASK(add-pipe-excluding-junk-ops, 0),
366 __K8MASK(multiply-pipe-excluding-junk-ops, 1),
367 __K8MASK(store-pipe-excluding-junk-ops, 2),
368 __K8MASK(add-pipe-junk-ops, 3),
369 __K8MASK(multiply-pipe-junk-ops, 4),
370 __K8MASK(store-pipe-junk-ops, 5),
371 NULLMASK
372 };
373
374 /* ls segment register loads */
375 static const struct pmc_masks k8_mask_lsrl[] = {
376 __K8MASK(es, 0),
377 __K8MASK(cs, 1),
378 __K8MASK(ss, 2),
379 __K8MASK(ds, 3),
380 __K8MASK(fs, 4),
381 __K8MASK(gs, 5),
382 __K8MASK(hs, 6),
383 NULLMASK
384 };
385
386 /* ls locked operation */
387 static const struct pmc_masks k8_mask_llo[] = {
388 __K8MASK(locked-instructions, 0),
389 __K8MASK(cycles-in-request, 1),
390 __K8MASK(cycles-to-complete, 2),
391 NULLMASK
392 };
393
394 /* dc refill from {l2,system} and dc copyback */
395 static const struct pmc_masks k8_mask_dc[] = {
396 __K8MASK(invalid, 0),
397 __K8MASK(shared, 1),
398 __K8MASK(exclusive, 2),
399 __K8MASK(owner, 3),
400 __K8MASK(modified, 4),
401 NULLMASK
402 };
403
404 /* dc one bit ecc error */
405 static const struct pmc_masks k8_mask_dobee[] = {
406 __K8MASK(scrubber, 0),
407 __K8MASK(piggyback, 1),
408 NULLMASK
409 };
410
411 /* dc dispatched prefetch instructions */
412 static const struct pmc_masks k8_mask_ddpi[] = {
413 __K8MASK(load, 0),
414 __K8MASK(store, 1),
415 __K8MASK(nta, 2),
416 NULLMASK
417 };
418
419 /* dc dcache accesses by locks */
420 static const struct pmc_masks k8_mask_dabl[] = {
421 __K8MASK(accesses, 0),
422 __K8MASK(misses, 1),
423 NULLMASK
424 };
425
426 /* bu internal l2 request */
427 static const struct pmc_masks k8_mask_bilr[] = {
428 __K8MASK(ic-fill, 0),
429 __K8MASK(dc-fill, 1),
430 __K8MASK(tlb-reload, 2),
431 __K8MASK(tag-snoop, 3),
432 __K8MASK(cancelled, 4),
433 NULLMASK
434 };
435
436 /* bu fill request l2 miss */
437 static const struct pmc_masks k8_mask_bfrlm[] = {
438 __K8MASK(ic-fill, 0),
439 __K8MASK(dc-fill, 1),
440 __K8MASK(tlb-reload, 2),
441 NULLMASK
442 };
443
444 /* bu fill into l2 */
445 static const struct pmc_masks k8_mask_bfil[] = {
446 __K8MASK(dirty-l2-victim, 0),
447 __K8MASK(victim-from-l2, 1),
448 NULLMASK
449 };
450
451 /* fr retired fpu instructions */
452 static const struct pmc_masks k8_mask_frfi[] = {
453 __K8MASK(x87, 0),
454 __K8MASK(mmx-3dnow, 1),
455 __K8MASK(packed-sse-sse2, 2),
456 __K8MASK(scalar-sse-sse2, 3),
457 NULLMASK
458 };
459
460 /* fr retired fastpath double op instructions */
461 static const struct pmc_masks k8_mask_frfdoi[] = {
462 __K8MASK(low-op-pos-0, 0),
463 __K8MASK(low-op-pos-1, 1),
464 __K8MASK(low-op-pos-2, 2),
465 NULLMASK
466 };
467
468 /* fr fpu exceptions */
469 static const struct pmc_masks k8_mask_ffe[] = {
470 __K8MASK(x87-reclass-microfaults, 0),
471 __K8MASK(sse-retype-microfaults, 1),
472 __K8MASK(sse-reclass-microfaults, 2),
473 __K8MASK(sse-and-x87-microtraps, 3),
474 NULLMASK
475 };
476
477 /* nb memory controller page access event */
478 static const struct pmc_masks k8_mask_nmcpae[] = {
479 __K8MASK(page-hit, 0),
480 __K8MASK(page-miss, 1),
481 __K8MASK(page-conflict, 2),
482 NULLMASK
483 };
484
485 /* nb memory controller turnaround */
486 static const struct pmc_masks k8_mask_nmct[] = {
487 __K8MASK(dimm-turnaround, 0),
488 __K8MASK(read-to-write-turnaround, 1),
489 __K8MASK(write-to-read-turnaround, 2),
490 NULLMASK
491 };
492
493 /* nb memory controller bypass saturation */
494 static const struct pmc_masks k8_mask_nmcbs[] = {
495 __K8MASK(memory-controller-hi-pri-bypass, 0),
496 __K8MASK(memory-controller-lo-pri-bypass, 1),
497 __K8MASK(dram-controller-interface-bypass, 2),
498 __K8MASK(dram-controller-queue-bypass, 3),
499 NULLMASK
500 };
501
502 /* nb sized commands */
503 static const struct pmc_masks k8_mask_nsc[] = {
504 __K8MASK(nonpostwrszbyte, 0),
505 __K8MASK(nonpostwrszdword, 1),
506 __K8MASK(postwrszbyte, 2),
507 __K8MASK(postwrszdword, 3),
508 __K8MASK(rdszbyte, 4),
509 __K8MASK(rdszdword, 5),
510 __K8MASK(rdmodwr, 6),
511 NULLMASK
512 };
513
514 /* nb probe result */
515 static const struct pmc_masks k8_mask_npr[] = {
516 __K8MASK(probe-miss, 0),
517 __K8MASK(probe-hit, 1),
518 __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
519 __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
520 NULLMASK
521 };
522
523 /* nb hypertransport bus bandwidth */
524 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
525 __K8MASK(command, 0),
526 __K8MASK(data, 1),
527 __K8MASK(buffer-release, 2),
528 __K8MASK(nop, 3),
529 NULLMASK
530 };
531
532 #undef __K8MASK
533
534 #define K8_KW_COUNT "count"
535 #define K8_KW_EDGE "edge"
536 #define K8_KW_INV "inv"
537 #define K8_KW_MASK "mask"
538 #define K8_KW_OS "os"
539 #define K8_KW_USR "usr"
540
541 static int
k8_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)542 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
543 struct pmc_op_pmcallocate *pmc_config)
544 {
545 char *e, *p, *q;
546 int n;
547 uint32_t count;
548 uint64_t evmask;
549 const struct pmc_masks *pm, *pmask;
550
551 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
552 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
553
554 pmask = NULL;
555 evmask = 0;
556
557 #define __K8SETMASK(M) pmask = k8_mask_##M
558
559 /* setup parsing tables */
560 switch (pe) {
561 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
562 __K8SETMASK(fdfo);
563 break;
564 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
565 __K8SETMASK(lsrl);
566 break;
567 case PMC_EV_K8_LS_LOCKED_OPERATION:
568 __K8SETMASK(llo);
569 break;
570 case PMC_EV_K8_DC_REFILL_FROM_L2:
571 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
572 case PMC_EV_K8_DC_COPYBACK:
573 __K8SETMASK(dc);
574 break;
575 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
576 __K8SETMASK(dobee);
577 break;
578 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
579 __K8SETMASK(ddpi);
580 break;
581 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
582 __K8SETMASK(dabl);
583 break;
584 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
585 __K8SETMASK(bilr);
586 break;
587 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
588 __K8SETMASK(bfrlm);
589 break;
590 case PMC_EV_K8_BU_FILL_INTO_L2:
591 __K8SETMASK(bfil);
592 break;
593 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
594 __K8SETMASK(frfi);
595 break;
596 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
597 __K8SETMASK(frfdoi);
598 break;
599 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
600 __K8SETMASK(ffe);
601 break;
602 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
603 __K8SETMASK(nmcpae);
604 break;
605 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
606 __K8SETMASK(nmct);
607 break;
608 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
609 __K8SETMASK(nmcbs);
610 break;
611 case PMC_EV_K8_NB_SIZED_COMMANDS:
612 __K8SETMASK(nsc);
613 break;
614 case PMC_EV_K8_NB_PROBE_RESULT:
615 __K8SETMASK(npr);
616 break;
617 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
618 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
619 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
620 __K8SETMASK(nhbb);
621 break;
622
623 default:
624 break; /* no options defined */
625 }
626
627 while ((p = strsep(&ctrspec, ",")) != NULL) {
628 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
629 q = strchr(p, '=');
630 if (*++q == '\0') /* skip '=' */
631 return (-1);
632
633 count = strtol(q, &e, 0);
634 if (e == q || *e != '\0')
635 return (-1);
636
637 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
638 pmc_config->pm_md.pm_amd.pm_amd_config |=
639 AMD_PMC_TO_COUNTER(count);
640
641 } else if (KWMATCH(p, K8_KW_EDGE)) {
642 pmc_config->pm_caps |= PMC_CAP_EDGE;
643 } else if (KWMATCH(p, K8_KW_INV)) {
644 pmc_config->pm_caps |= PMC_CAP_INVERT;
645 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
646 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
647 return (-1);
648 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
649 } else if (KWMATCH(p, K8_KW_OS)) {
650 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
651 } else if (KWMATCH(p, K8_KW_USR)) {
652 pmc_config->pm_caps |= PMC_CAP_USER;
653 } else
654 return (-1);
655 }
656
657 /* other post processing */
658 switch (pe) {
659 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
660 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
661 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
662 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
663 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
664 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
665 /* XXX only available in rev B and later */
666 break;
667 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
668 /* XXX only available in rev C and later */
669 break;
670 case PMC_EV_K8_LS_LOCKED_OPERATION:
671 /* XXX CPU Rev A,B evmask is to be zero */
672 if (evmask & (evmask - 1)) /* > 1 bit set */
673 return (-1);
674 if (evmask == 0) {
675 evmask = 0x01; /* Rev C and later: #instrs */
676 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
677 }
678 break;
679 default:
680 if (evmask == 0 && pmask != NULL) {
681 for (pm = pmask; pm->pm_name; pm++)
682 evmask |= pm->pm_value;
683 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
684 }
685 }
686
687 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
688 pmc_config->pm_md.pm_amd.pm_amd_config =
689 AMD_PMC_TO_UNITMASK(evmask);
690
691 return (0);
692 }
693
694 static int
ibs_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)695 ibs_allocate_pmc(enum pmc_event pe, char *ctrspec,
696 struct pmc_op_pmcallocate *pmc_config)
697 {
698 char *e, *p, *q;
699 uint64_t ctl;
700
701 pmc_config->pm_caps |=
702 (PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_PRECISE);
703 pmc_config->pm_md.pm_ibs.ibs_ctl = 0;
704
705 /* setup parsing tables */
706 switch (pe) {
707 case PMC_EV_IBS_FETCH:
708 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_FETCH;
709 break;
710 case PMC_EV_IBS_OP:
711 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_OP;
712 break;
713 default:
714 return (-1);
715 }
716
717 /* parse parameters */
718 while ((p = strsep(&ctrspec, ",")) != NULL) {
719 if (KWPREFIXMATCH(p, "ctl=")) {
720 q = strchr(p, '=');
721 if (*++q == '\0') /* skip '=' */
722 return (-1);
723
724 ctl = strtoull(q, &e, 0);
725 if (e == q || *e != '\0')
726 return (-1);
727
728 pmc_config->pm_md.pm_ibs.ibs_ctl |= ctl;
729 } else {
730 return (-1);
731 }
732 }
733
734 return (0);
735 }
736
737 static int
tsc_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)738 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
739 struct pmc_op_pmcallocate *pmc_config)
740 {
741 if (pe != PMC_EV_TSC_TSC)
742 return (-1);
743
744 /* TSC events must be unqualified. */
745 if (ctrspec && *ctrspec != '\0')
746 return (-1);
747
748 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
749 pmc_config->pm_caps |= PMC_CAP_READ;
750
751 return (0);
752 }
753 #endif
754
755 static struct pmc_event_alias generic_aliases[] = {
756 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"),
757 EV_ALIAS(NULL, NULL)
758 };
759
760 static int
soft_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)761 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
762 struct pmc_op_pmcallocate *pmc_config)
763 {
764 (void)ctrspec;
765 (void)pmc_config;
766
767 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST)
768 return (-1);
769
770 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
771 return (0);
772 }
773
774 #if defined(__arm__)
775 static struct pmc_event_alias cortex_a8_aliases[] = {
776 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
777 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
778 EV_ALIAS("instructions", "INSTR_EXECUTED"),
779 EV_ALIAS(NULL, NULL)
780 };
781
782 static struct pmc_event_alias cortex_a9_aliases[] = {
783 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
784 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
785 EV_ALIAS("instructions", "INSTR_EXECUTED"),
786 EV_ALIAS(NULL, NULL)
787 };
788
789 static int
armv7_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)790 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
791 struct pmc_op_pmcallocate *pmc_config __unused)
792 {
793 switch (pe) {
794 default:
795 break;
796 }
797
798 return (0);
799 }
800 #endif
801
802 #if defined(__aarch64__)
803 static struct pmc_event_alias cortex_a53_aliases[] = {
804 EV_ALIAS(NULL, NULL)
805 };
806 static struct pmc_event_alias cortex_a57_aliases[] = {
807 EV_ALIAS(NULL, NULL)
808 };
809 static struct pmc_event_alias cortex_a76_aliases[] = {
810 EV_ALIAS(NULL, NULL)
811 };
812
813 static int
arm64_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)814 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec,
815 struct pmc_op_pmcallocate *pmc_config)
816 {
817 char *p;
818
819 while ((p = strsep(&ctrspec, ",")) != NULL) {
820 if (KWMATCH(p, "os"))
821 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
822 else if (KWMATCH(p, "usr"))
823 pmc_config->pm_caps |= PMC_CAP_USER;
824 else
825 return (-1);
826 }
827
828 return (0);
829 }
830
831 static int
cmn600_pmu_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)832 cmn600_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec,
833 struct pmc_op_pmcallocate *pmc_config)
834 {
835 uint32_t nodeid, occupancy, xpport, xpchannel;
836 char *e, *p, *q;
837 unsigned int i;
838 char *xpport_names[] = { "East", "West", "North", "South", "devport0",
839 "devport1" };
840 char *xpchannel_names[] = { "REQ", "RSP", "SNP", "DAT" };
841
842 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
843 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
844 pmc_config->pm_md.pm_cmn600.pma_cmn600_config = 0;
845 /*
846 * CMN600 extra fields:
847 * * nodeid - node coordinates x[2-3],y[2-3],p[1],s[2]
848 * width of x and y fields depend on matrix size.
849 * * occupancy - numeric value to select desired filter.
850 * * xpport - East, West, North, South, devport0, devport1 (or 0, 1, ..., 5)
851 * * xpchannel - REQ, RSP, SNP, DAT (or 0, 1, 2, 3)
852 */
853
854 while ((p = strsep(&ctrspec, ",")) != NULL) {
855 if (KWPREFIXMATCH(p, "nodeid=")) {
856 q = strchr(p, '=');
857 if (*++q == '\0') /* skip '=' */
858 return (-1);
859
860 nodeid = strtol(q, &e, 0);
861 if (e == q || *e != '\0')
862 return (-1);
863
864 pmc_config->pm_md.pm_cmn600.pma_cmn600_nodeid |= nodeid;
865
866 } else if (KWPREFIXMATCH(p, "occupancy=")) {
867 q = strchr(p, '=');
868 if (*++q == '\0') /* skip '=' */
869 return (-1);
870
871 occupancy = strtol(q, &e, 0);
872 if (e == q || *e != '\0')
873 return (-1);
874
875 pmc_config->pm_md.pm_cmn600.pma_cmn600_occupancy = occupancy;
876 } else if (KWPREFIXMATCH(p, "xpport=")) {
877 q = strchr(p, '=');
878 if (*++q == '\0') /* skip '=' */
879 return (-1);
880
881 xpport = strtol(q, &e, 0);
882 if (e == q || *e != '\0') {
883 for (i = 0; i < nitems(xpport_names); i++) {
884 if (strcasecmp(xpport_names[i], q) == 0) {
885 xpport = i;
886 break;
887 }
888 }
889 if (i == nitems(xpport_names))
890 return (-1);
891 }
892
893 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpport << 2;
894 } else if (KWPREFIXMATCH(p, "xpchannel=")) {
895 q = strchr(p, '=');
896 if (*++q == '\0') /* skip '=' */
897 return (-1);
898
899 xpchannel = strtol(q, &e, 0);
900 if (e == q || *e != '\0') {
901 for (i = 0; i < nitems(xpchannel_names); i++) {
902 if (strcasecmp(xpchannel_names[i], q) == 0) {
903 xpchannel = i;
904 break;
905 }
906 }
907 if (i == nitems(xpchannel_names))
908 return (-1);
909 }
910
911 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpchannel << 5;
912 } else
913 return (-1);
914 }
915
916 return (0);
917 }
918
919 static int
dmc620_pmu_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)920 dmc620_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec,
921 struct pmc_op_pmcallocate *pmc_config)
922 {
923 char *e, *p, *q;
924 uint64_t match, mask;
925 uint32_t count;
926
927 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
928 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
929 pmc_config->pm_md.pm_dmc620.pm_dmc620_config = 0;
930
931 while ((p = strsep(&ctrspec, ",")) != NULL) {
932 if (KWPREFIXMATCH(p, "count=")) {
933 q = strchr(p, '=');
934 if (*++q == '\0') /* skip '=' */
935 return (-1);
936
937 count = strtol(q, &e, 0);
938 if (e == q || *e != '\0')
939 return (-1);
940
941 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
942 pmc_config->pm_md.pm_dmc620.pm_dmc620_config |= count;
943
944 } else if (KWMATCH(p, "inv")) {
945 pmc_config->pm_caps |= PMC_CAP_INVERT;
946 } else if (KWPREFIXMATCH(p, "match=")) {
947 match = strtol(q, &e, 0);
948 if (e == q || *e != '\0')
949 return (-1);
950
951 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
952 pmc_config->pm_md.pm_dmc620.pm_dmc620_match = match;
953 } else if (KWPREFIXMATCH(p, "mask=")) {
954 q = strchr(p, '=');
955 if (*++q == '\0') /* skip '=' */
956 return (-1);
957
958 mask = strtol(q, &e, 0);
959 if (e == q || *e != '\0')
960 return (-1);
961
962 pmc_config->pm_md.pm_dmc620.pm_dmc620_mask = mask;
963 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
964 } else
965 return (-1);
966 }
967
968 return (0);
969 }
970 #endif
971
972 #if defined(__powerpc__)
973
974 static struct pmc_event_alias ppc7450_aliases[] = {
975 EV_ALIAS("instructions", "INSTR_COMPLETED"),
976 EV_ALIAS("branches", "BRANCHES_COMPLETED"),
977 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"),
978 EV_ALIAS(NULL, NULL)
979 };
980
981 static struct pmc_event_alias ppc970_aliases[] = {
982 EV_ALIAS("instructions", "INSTR_COMPLETED"),
983 EV_ALIAS("cycles", "CYCLES"),
984 EV_ALIAS(NULL, NULL)
985 };
986
987 static struct pmc_event_alias e500_aliases[] = {
988 EV_ALIAS("instructions", "INSTR_COMPLETED"),
989 EV_ALIAS("cycles", "CYCLES"),
990 EV_ALIAS(NULL, NULL)
991 };
992
993 #define POWERPC_KW_OS "os"
994 #define POWERPC_KW_USR "usr"
995 #define POWERPC_KW_ANYTHREAD "anythread"
996
997 static int
powerpc_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)998 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
999 struct pmc_op_pmcallocate *pmc_config __unused)
1000 {
1001 char *p;
1002
1003 (void) pe;
1004
1005 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1006
1007 while ((p = strsep(&ctrspec, ",")) != NULL) {
1008 if (KWMATCH(p, POWERPC_KW_OS))
1009 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1010 else if (KWMATCH(p, POWERPC_KW_USR))
1011 pmc_config->pm_caps |= PMC_CAP_USER;
1012 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD))
1013 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
1014 else
1015 return (-1);
1016 }
1017
1018 return (0);
1019 }
1020
1021 #endif /* __powerpc__ */
1022
1023
1024 /*
1025 * Match an event name `name' with its canonical form.
1026 *
1027 * Matches are case insensitive and spaces, periods, underscores and
1028 * hyphen characters are considered to match each other.
1029 *
1030 * Returns 1 for a match, 0 otherwise.
1031 */
1032
1033 static int
pmc_match_event_name(const char * name,const char * canonicalname)1034 pmc_match_event_name(const char *name, const char *canonicalname)
1035 {
1036 int cc, nc;
1037 const unsigned char *c, *n;
1038
1039 c = (const unsigned char *) canonicalname;
1040 n = (const unsigned char *) name;
1041
1042 for (; (nc = *n) && (cc = *c); n++, c++) {
1043
1044 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
1045 (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
1046 continue;
1047
1048 if (toupper(nc) == toupper(cc))
1049 continue;
1050
1051
1052 return (0);
1053 }
1054
1055 if (*n == '\0' && *c == '\0')
1056 return (1);
1057
1058 return (0);
1059 }
1060
1061 /*
1062 * Match an event name against all the event named supported by a
1063 * PMC class.
1064 *
1065 * Returns an event descriptor pointer on match or NULL otherwise.
1066 */
1067 static const struct pmc_event_descr *
pmc_match_event_class(const char * name,const struct pmc_class_descr * pcd)1068 pmc_match_event_class(const char *name,
1069 const struct pmc_class_descr *pcd)
1070 {
1071 size_t n;
1072 const struct pmc_event_descr *ev;
1073
1074 ev = pcd->pm_evc_event_table;
1075 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
1076 if (pmc_match_event_name(name, ev->pm_ev_name))
1077 return (ev);
1078
1079 return (NULL);
1080 }
1081
1082 /*
1083 * API entry points
1084 */
1085
1086 int
pmc_allocate(const char * ctrspec,enum pmc_mode mode,uint32_t flags,int cpu,pmc_id_t * pmcid,uint64_t count)1087 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
1088 uint32_t flags, int cpu, pmc_id_t *pmcid,
1089 uint64_t count)
1090 {
1091 size_t n;
1092 int retval;
1093 char *r, *spec_copy;
1094 const char *ctrname;
1095 const struct pmc_event_descr *ev;
1096 const struct pmc_event_alias *alias;
1097 struct pmc_op_pmcallocate pmc_config;
1098 const struct pmc_class_descr *pcd;
1099
1100 spec_copy = NULL;
1101 retval = -1;
1102
1103 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
1104 mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
1105 errno = EINVAL;
1106 goto out;
1107 }
1108 bzero(&pmc_config, sizeof(pmc_config));
1109 pmc_config.pm_cpu = cpu;
1110 pmc_config.pm_mode = mode;
1111 pmc_config.pm_flags = flags;
1112 pmc_config.pm_count = count;
1113 if (PMC_IS_SAMPLING_MODE(mode))
1114 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
1115
1116 /*
1117 * Try to pull the raw event ID directly from the pmu-events table. If
1118 * this is unsupported on the platform, or the event is not found,
1119 * continue with searching the regular event tables.
1120 */
1121 r = spec_copy = strdup(ctrspec);
1122 ctrname = strsep(&r, ",");
1123 if (pmc_pmu_enabled()) {
1124 errno = pmc_pmu_pmcallocate(ctrname, &pmc_config);
1125 if (errno == 0)
1126 goto found;
1127 if (errno == EOPNOTSUPP)
1128 goto out;
1129 }
1130 free(spec_copy);
1131 spec_copy = NULL;
1132
1133 /* replace an event alias with the canonical event specifier */
1134 if (pmc_mdep_event_aliases)
1135 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
1136 if (!strcasecmp(ctrspec, alias->pm_alias)) {
1137 spec_copy = strdup(alias->pm_spec);
1138 break;
1139 }
1140
1141 if (spec_copy == NULL)
1142 spec_copy = strdup(ctrspec);
1143
1144 r = spec_copy;
1145 ctrname = strsep(&r, ",");
1146
1147 /*
1148 * If a explicit class prefix was given by the user, restrict the
1149 * search for the event to the specified PMC class.
1150 */
1151 ev = NULL;
1152 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
1153 pcd = pmc_class_table[n];
1154 if (pcd != NULL && strncasecmp(ctrname, pcd->pm_evc_name,
1155 pcd->pm_evc_name_size) == 0) {
1156 if ((ev = pmc_match_event_class(ctrname +
1157 pcd->pm_evc_name_size, pcd)) == NULL) {
1158 errno = EINVAL;
1159 goto out;
1160 }
1161 break;
1162 }
1163 }
1164
1165 /*
1166 * Otherwise, search for this event in all compatible PMC
1167 * classes.
1168 */
1169 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
1170 pcd = pmc_class_table[n];
1171 if (pcd != NULL)
1172 ev = pmc_match_event_class(ctrname, pcd);
1173 }
1174
1175 if (ev == NULL) {
1176 errno = EINVAL;
1177 goto out;
1178 }
1179
1180 pmc_config.pm_ev = ev->pm_ev_code;
1181 pmc_config.pm_class = pcd->pm_evc_class;
1182
1183 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
1184 errno = EINVAL;
1185 goto out;
1186 }
1187
1188 found:
1189 if (PMC_CALL(PMC_OP_PMCALLOCATE, &pmc_config) == 0) {
1190 *pmcid = pmc_config.pm_pmcid;
1191 retval = 0;
1192 }
1193 out:
1194 if (spec_copy)
1195 free(spec_copy);
1196
1197 return (retval);
1198 }
1199
1200 int
pmc_attach(pmc_id_t pmc,pid_t pid)1201 pmc_attach(pmc_id_t pmc, pid_t pid)
1202 {
1203 struct pmc_op_pmcattach pmc_attach_args;
1204
1205 pmc_attach_args.pm_pmc = pmc;
1206 pmc_attach_args.pm_pid = pid;
1207
1208 return (PMC_CALL(PMC_OP_PMCATTACH, &pmc_attach_args));
1209 }
1210
1211 int
pmc_capabilities(pmc_id_t pmcid,uint32_t * caps)1212 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
1213 {
1214 struct pmc_op_caps args;
1215 int status;
1216
1217 args.pm_pmcid = pmcid;
1218 args.pm_caps = 0;
1219
1220 status = PMC_CALL(PMC_OP_GETCAPS, &args);
1221 *caps = args.pm_caps;
1222
1223 return (status);
1224 }
1225
1226 int
pmc_configure_logfile(int fd)1227 pmc_configure_logfile(int fd)
1228 {
1229 struct pmc_op_configurelog cla;
1230
1231 cla.pm_flags = 0;
1232 cla.pm_logfd = fd;
1233 if (PMC_CALL(PMC_OP_CONFIGURELOG, &cla) < 0)
1234 return (-1);
1235 return (0);
1236 }
1237
1238 int
pmc_cpuinfo(const struct pmc_cpuinfo ** pci)1239 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
1240 {
1241 if (pmc_syscall == -1) {
1242 errno = ENXIO;
1243 return (-1);
1244 }
1245
1246 *pci = &cpu_info;
1247 return (0);
1248 }
1249
1250 int
pmc_detach(pmc_id_t pmc,pid_t pid)1251 pmc_detach(pmc_id_t pmc, pid_t pid)
1252 {
1253 struct pmc_op_pmcattach pmc_detach_args;
1254
1255 pmc_detach_args.pm_pmc = pmc;
1256 pmc_detach_args.pm_pid = pid;
1257 return (PMC_CALL(PMC_OP_PMCDETACH, &pmc_detach_args));
1258 }
1259
1260 int
pmc_disable(int cpu,int pmc)1261 pmc_disable(int cpu, int pmc)
1262 {
1263 struct pmc_op_pmcadmin ssa;
1264
1265 ssa.pm_cpu = cpu;
1266 ssa.pm_pmc = pmc;
1267 ssa.pm_state = PMC_STATE_DISABLED;
1268 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1269 }
1270
1271 int
pmc_enable(int cpu,int pmc)1272 pmc_enable(int cpu, int pmc)
1273 {
1274 struct pmc_op_pmcadmin ssa;
1275
1276 ssa.pm_cpu = cpu;
1277 ssa.pm_pmc = pmc;
1278 ssa.pm_state = PMC_STATE_FREE;
1279 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1280 }
1281
1282 /*
1283 * Return a list of events known to a given PMC class. 'cl' is the
1284 * PMC class identifier, 'eventnames' is the returned list of 'const
1285 * char *' pointers pointing to the names of the events. 'nevents' is
1286 * the number of event name pointers returned.
1287 *
1288 * The space for 'eventnames' is allocated using malloc(3). The caller
1289 * is responsible for freeing this space when done.
1290 */
1291 int
pmc_event_names_of_class(enum pmc_class cl,const char *** eventnames,int * nevents)1292 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
1293 int *nevents)
1294 {
1295 int count;
1296 const char **names;
1297 const struct pmc_event_descr *ev;
1298
1299 switch (cl)
1300 {
1301 case PMC_CLASS_IAF:
1302 ev = iaf_event_table;
1303 count = PMC_EVENT_TABLE_SIZE(iaf);
1304 break;
1305 case PMC_CLASS_TSC:
1306 ev = tsc_event_table;
1307 count = PMC_EVENT_TABLE_SIZE(tsc);
1308 break;
1309 case PMC_CLASS_K8:
1310 ev = k8_event_table;
1311 count = PMC_EVENT_TABLE_SIZE(k8);
1312 break;
1313 case PMC_CLASS_IBS:
1314 ev = ibs_event_table;
1315 count = PMC_EVENT_TABLE_SIZE(ibs);
1316 break;
1317 case PMC_CLASS_ARMV7:
1318 switch (cpu_info.pm_cputype) {
1319 default:
1320 case PMC_CPU_ARMV7_CORTEX_A8:
1321 ev = cortex_a8_event_table;
1322 count = PMC_EVENT_TABLE_SIZE(cortex_a8);
1323 break;
1324 case PMC_CPU_ARMV7_CORTEX_A9:
1325 ev = cortex_a9_event_table;
1326 count = PMC_EVENT_TABLE_SIZE(cortex_a9);
1327 break;
1328 }
1329 break;
1330 case PMC_CLASS_ARMV8:
1331 switch (cpu_info.pm_cputype) {
1332 default:
1333 case PMC_CPU_ARMV8_CORTEX_A53:
1334 ev = cortex_a53_event_table;
1335 count = PMC_EVENT_TABLE_SIZE(cortex_a53);
1336 break;
1337 case PMC_CPU_ARMV8_CORTEX_A57:
1338 ev = cortex_a57_event_table;
1339 count = PMC_EVENT_TABLE_SIZE(cortex_a57);
1340 break;
1341 case PMC_CPU_ARMV8_CORTEX_A76:
1342 ev = cortex_a76_event_table;
1343 count = PMC_EVENT_TABLE_SIZE(cortex_a76);
1344 break;
1345 }
1346 break;
1347 case PMC_CLASS_CMN600_PMU:
1348 ev = cmn600_pmu_event_table;
1349 count = PMC_EVENT_TABLE_SIZE(cmn600_pmu);
1350 break;
1351 case PMC_CLASS_DMC620_PMU_CD2:
1352 ev = dmc620_pmu_cd2_event_table;
1353 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2);
1354 break;
1355 case PMC_CLASS_DMC620_PMU_C:
1356 ev = dmc620_pmu_c_event_table;
1357 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_c);
1358 break;
1359 case PMC_CLASS_PPC7450:
1360 ev = ppc7450_event_table;
1361 count = PMC_EVENT_TABLE_SIZE(ppc7450);
1362 break;
1363 case PMC_CLASS_PPC970:
1364 ev = ppc970_event_table;
1365 count = PMC_EVENT_TABLE_SIZE(ppc970);
1366 break;
1367 case PMC_CLASS_E500:
1368 ev = e500_event_table;
1369 count = PMC_EVENT_TABLE_SIZE(e500);
1370 break;
1371 case PMC_CLASS_SOFT:
1372 ev = soft_event_table;
1373 count = soft_event_info.pm_nevent;
1374 break;
1375 default:
1376 errno = EINVAL;
1377 return (-1);
1378 }
1379
1380 if ((names = malloc(count * sizeof(const char *))) == NULL)
1381 return (-1);
1382
1383 *eventnames = names;
1384 *nevents = count;
1385
1386 for (;count--; ev++, names++)
1387 *names = ev->pm_ev_name;
1388
1389 return (0);
1390 }
1391
1392 int
pmc_flush_logfile(void)1393 pmc_flush_logfile(void)
1394 {
1395 return (PMC_CALL(PMC_OP_FLUSHLOG, 0));
1396 }
1397
1398 int
pmc_close_logfile(void)1399 pmc_close_logfile(void)
1400 {
1401 return (PMC_CALL(PMC_OP_CLOSELOG, 0));
1402 }
1403
1404 int
pmc_get_driver_stats(struct pmc_driverstats * ds)1405 pmc_get_driver_stats(struct pmc_driverstats *ds)
1406 {
1407 struct pmc_op_getdriverstats gms;
1408
1409 if (PMC_CALL(PMC_OP_GETDRIVERSTATS, &gms) < 0)
1410 return (-1);
1411
1412 /* copy out fields in the current userland<->library interface */
1413 ds->pm_intr_ignored = gms.pm_intr_ignored;
1414 ds->pm_intr_processed = gms.pm_intr_processed;
1415 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
1416 ds->pm_syscalls = gms.pm_syscalls;
1417 ds->pm_syscall_errors = gms.pm_syscall_errors;
1418 ds->pm_buffer_requests = gms.pm_buffer_requests;
1419 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
1420 ds->pm_log_sweeps = gms.pm_log_sweeps;
1421 return (0);
1422 }
1423
1424 int
pmc_get_msr(pmc_id_t pmc,uint32_t * msr)1425 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
1426 {
1427 struct pmc_op_getmsr gm;
1428
1429 gm.pm_pmcid = pmc;
1430 if (PMC_CALL(PMC_OP_PMCGETMSR, &gm) < 0)
1431 return (-1);
1432 *msr = gm.pm_msr;
1433 return (0);
1434 }
1435
1436 int
pmc_init(void)1437 pmc_init(void)
1438 {
1439 int error, pmc_mod_id;
1440 unsigned int n;
1441 uint32_t abi_version;
1442 struct module_stat pmc_modstat;
1443 struct pmc_op_getcpuinfo op_cpu_info;
1444
1445 if (pmc_syscall != -1) /* already inited */
1446 return (0);
1447
1448 /* retrieve the system call number from the KLD */
1449 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
1450 return (-1);
1451
1452 pmc_modstat.version = sizeof(struct module_stat);
1453 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
1454 return (-1);
1455
1456 pmc_syscall = pmc_modstat.data.intval;
1457
1458 /* check the kernel module's ABI against our compiled-in version */
1459 abi_version = PMC_VERSION;
1460 if (PMC_CALL(PMC_OP_GETMODULEVERSION, &abi_version) < 0)
1461 return (pmc_syscall = -1);
1462
1463 /* ignore patch & minor numbers for the comparison */
1464 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
1465 errno = EPROGMISMATCH;
1466 return (pmc_syscall = -1);
1467 }
1468
1469 bzero(&op_cpu_info, sizeof(op_cpu_info));
1470 if (PMC_CALL(PMC_OP_GETCPUINFO, &op_cpu_info) < 0)
1471 return (pmc_syscall = -1);
1472
1473 cpu_info.pm_cputype = op_cpu_info.pm_cputype;
1474 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu;
1475 cpu_info.pm_npmc = op_cpu_info.pm_npmc;
1476 cpu_info.pm_nclass = op_cpu_info.pm_nclass;
1477 for (n = 0; n < op_cpu_info.pm_nclass; n++)
1478 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n],
1479 sizeof(cpu_info.pm_classes[n]));
1480
1481 pmc_class_table = calloc(PMC_CLASS_TABLE_SIZE,
1482 sizeof(struct pmc_class_descr *));
1483
1484 if (pmc_class_table == NULL)
1485 return (-1);
1486
1487 /*
1488 * Get soft events list.
1489 */
1490 soft_event_info.pm_class = PMC_CLASS_SOFT;
1491 if (PMC_CALL(PMC_OP_GETDYNEVENTINFO, &soft_event_info) < 0)
1492 return (pmc_syscall = -1);
1493
1494 /* Map soft events to static list. */
1495 for (n = 0; n < soft_event_info.pm_nevent; n++) {
1496 soft_event_table[n].pm_ev_name =
1497 soft_event_info.pm_events[n].pm_ev_name;
1498 soft_event_table[n].pm_ev_code =
1499 soft_event_info.pm_events[n].pm_ev_code;
1500 }
1501 soft_class_table_descr.pm_evc_event_table_size = \
1502 soft_event_info.pm_nevent;
1503 soft_class_table_descr.pm_evc_event_table = \
1504 soft_event_table;
1505
1506 /*
1507 * Fill in the class table.
1508 */
1509 n = 0;
1510 for (unsigned i = 0; i < PMC_CLASS_TABLE_SIZE; i++) {
1511 switch (cpu_info.pm_classes[i].pm_class) {
1512 #if defined(__amd64__) || defined(__i386__)
1513 case PMC_CLASS_TSC:
1514 pmc_class_table[n++] = &tsc_class_table_descr;
1515 break;
1516
1517 case PMC_CLASS_K8:
1518 pmc_class_table[n++] = &k8_class_table_descr;
1519 break;
1520
1521 case PMC_CLASS_IBS:
1522 pmc_class_table[n++] = &ibs_class_table_descr;
1523 break;
1524 #endif
1525
1526 case PMC_CLASS_SOFT:
1527 pmc_class_table[n++] = &soft_class_table_descr;
1528 break;
1529
1530 #if defined(__arm__)
1531 case PMC_CLASS_ARMV7:
1532 switch (cpu_info.pm_cputype) {
1533 case PMC_CPU_ARMV7_CORTEX_A8:
1534 pmc_class_table[n++] =
1535 &cortex_a8_class_table_descr;
1536 break;
1537 case PMC_CPU_ARMV7_CORTEX_A9:
1538 pmc_class_table[n++] =
1539 &cortex_a9_class_table_descr;
1540 break;
1541 default:
1542 errno = ENXIO;
1543 return (pmc_syscall = -1);
1544 }
1545 break;
1546 #endif
1547
1548 #if defined(__aarch64__)
1549 case PMC_CLASS_ARMV8:
1550 switch (cpu_info.pm_cputype) {
1551 case PMC_CPU_ARMV8_CORTEX_A53:
1552 pmc_class_table[n++] =
1553 &cortex_a53_class_table_descr;
1554 break;
1555 case PMC_CPU_ARMV8_CORTEX_A57:
1556 pmc_class_table[n++] =
1557 &cortex_a57_class_table_descr;
1558 break;
1559 case PMC_CPU_ARMV8_CORTEX_A76:
1560 pmc_class_table[n++] =
1561 &cortex_a76_class_table_descr;
1562 break;
1563 default:
1564 errno = ENXIO;
1565 return (pmc_syscall = -1);
1566 }
1567 break;
1568
1569 case PMC_CLASS_DMC620_PMU_CD2:
1570 pmc_class_table[n++] =
1571 &dmc620_pmu_cd2_class_table_descr;
1572 break;
1573
1574 case PMC_CLASS_DMC620_PMU_C:
1575 pmc_class_table[n++] = &dmc620_pmu_c_class_table_descr;
1576 break;
1577
1578 case PMC_CLASS_CMN600_PMU:
1579 pmc_class_table[n++] = &cmn600_pmu_class_table_descr;
1580 break;
1581 #endif
1582
1583 #if defined(__powerpc__)
1584 case PMC_CLASS_PPC7450:
1585 pmc_class_table[n++] = &ppc7450_class_table_descr;
1586 break;
1587
1588 case PMC_CLASS_PPC970:
1589 pmc_class_table[n++] = &ppc970_class_table_descr;
1590 break;
1591
1592 case PMC_CLASS_E500:
1593 pmc_class_table[n++] = &e500_class_table_descr;
1594 break;
1595 #endif
1596
1597 default:
1598 #if defined(DEBUG)
1599 printf("pm_class: 0x%x\n",
1600 cpu_info.pm_classes[i].pm_class);
1601 #endif
1602 break;
1603 }
1604 }
1605
1606 #define PMC_MDEP_INIT(C) pmc_mdep_event_aliases = C##_aliases
1607
1608 /* Configure the event name parser. */
1609 switch (cpu_info.pm_cputype) {
1610 #if defined(__amd64__) || defined(__i386__)
1611 case PMC_CPU_AMD_K8:
1612 PMC_MDEP_INIT(k8);
1613 break;
1614 #endif
1615 case PMC_CPU_GENERIC:
1616 PMC_MDEP_INIT(generic);
1617 break;
1618 #if defined(__arm__)
1619 case PMC_CPU_ARMV7_CORTEX_A8:
1620 PMC_MDEP_INIT(cortex_a8);
1621 break;
1622 case PMC_CPU_ARMV7_CORTEX_A9:
1623 PMC_MDEP_INIT(cortex_a9);
1624 break;
1625 #endif
1626 #if defined(__aarch64__)
1627 case PMC_CPU_ARMV8_CORTEX_A53:
1628 PMC_MDEP_INIT(cortex_a53);
1629 break;
1630 case PMC_CPU_ARMV8_CORTEX_A57:
1631 PMC_MDEP_INIT(cortex_a57);
1632 break;
1633 case PMC_CPU_ARMV8_CORTEX_A76:
1634 PMC_MDEP_INIT(cortex_a76);
1635 break;
1636 #endif
1637 #if defined(__powerpc__)
1638 case PMC_CPU_PPC_7450:
1639 PMC_MDEP_INIT(ppc7450);
1640 break;
1641 case PMC_CPU_PPC_970:
1642 PMC_MDEP_INIT(ppc970);
1643 break;
1644 case PMC_CPU_PPC_E500:
1645 PMC_MDEP_INIT(e500);
1646 break;
1647 #endif
1648 default:
1649 /*
1650 * Some kind of CPU this version of the library knows nothing
1651 * about. This shouldn't happen since the abi version check
1652 * should have caught this.
1653 */
1654 #if defined(__amd64__) || defined(__i386__) || defined(__powerpc64__)
1655 break;
1656 #endif
1657 errno = ENXIO;
1658 return (pmc_syscall = -1);
1659 }
1660
1661 return (0);
1662 }
1663
1664 const char *
pmc_name_of_capability(enum pmc_caps cap)1665 pmc_name_of_capability(enum pmc_caps cap)
1666 {
1667 int i;
1668
1669 /*
1670 * 'cap' should have a single bit set and should be in
1671 * range.
1672 */
1673 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
1674 cap > PMC_CAP_LAST) {
1675 errno = EINVAL;
1676 return (NULL);
1677 }
1678
1679 i = ffs(cap);
1680 return (pmc_capability_names[i - 1]);
1681 }
1682
1683 const char *
pmc_name_of_class(enum pmc_class pc)1684 pmc_name_of_class(enum pmc_class pc)
1685 {
1686 size_t n;
1687
1688 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++)
1689 if (pc == pmc_class_names[n].pm_class)
1690 return (pmc_class_names[n].pm_name);
1691
1692 errno = EINVAL;
1693 return (NULL);
1694 }
1695
1696 const char *
pmc_name_of_cputype(enum pmc_cputype cp)1697 pmc_name_of_cputype(enum pmc_cputype cp)
1698 {
1699 size_t n;
1700
1701 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
1702 if (cp == pmc_cputype_names[n].pm_cputype)
1703 return (pmc_cputype_names[n].pm_name);
1704
1705 errno = EINVAL;
1706 return (NULL);
1707 }
1708
1709 const char *
pmc_name_of_disposition(enum pmc_disp pd)1710 pmc_name_of_disposition(enum pmc_disp pd)
1711 {
1712 if ((int) pd >= PMC_DISP_FIRST &&
1713 pd <= PMC_DISP_LAST)
1714 return (pmc_disposition_names[pd]);
1715
1716 errno = EINVAL;
1717 return (NULL);
1718 }
1719
1720 const char *
_pmc_name_of_event(enum pmc_event pe,enum pmc_cputype cpu)1721 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
1722 {
1723 const struct pmc_event_descr *ev, *evfence;
1724
1725 ev = evfence = NULL;
1726 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
1727 ev = k8_event_table;
1728 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
1729 } else if (pe >= PMC_EV_IBS_FIRST && pe <= PMC_EV_IBS_LAST) {
1730 ev = ibs_event_table;
1731 evfence = ibs_event_table + PMC_EVENT_TABLE_SIZE(ibs);
1732 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) {
1733 switch (cpu) {
1734 case PMC_CPU_ARMV7_CORTEX_A8:
1735 ev = cortex_a8_event_table;
1736 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8);
1737 break;
1738 case PMC_CPU_ARMV7_CORTEX_A9:
1739 ev = cortex_a9_event_table;
1740 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9);
1741 break;
1742 default: /* Unknown CPU type. */
1743 break;
1744 }
1745 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) {
1746 switch (cpu) {
1747 case PMC_CPU_ARMV8_CORTEX_A53:
1748 ev = cortex_a53_event_table;
1749 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53);
1750 break;
1751 case PMC_CPU_ARMV8_CORTEX_A57:
1752 ev = cortex_a57_event_table;
1753 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57);
1754 break;
1755 case PMC_CPU_ARMV8_CORTEX_A76:
1756 ev = cortex_a76_event_table;
1757 evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76);
1758 break;
1759 default: /* Unknown CPU type. */
1760 break;
1761 }
1762 } else if (pe >= PMC_EV_CMN600_PMU_FIRST &&
1763 pe <= PMC_EV_CMN600_PMU_LAST) {
1764 ev = cmn600_pmu_event_table;
1765 evfence = cmn600_pmu_event_table +
1766 PMC_EVENT_TABLE_SIZE(cmn600_pmu);
1767 } else if (pe >= PMC_EV_DMC620_PMU_CD2_FIRST &&
1768 pe <= PMC_EV_DMC620_PMU_CD2_LAST) {
1769 ev = dmc620_pmu_cd2_event_table;
1770 evfence = dmc620_pmu_cd2_event_table +
1771 PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2);
1772 } else if (pe >= PMC_EV_DMC620_PMU_C_FIRST &&
1773 pe <= PMC_EV_DMC620_PMU_C_LAST) {
1774 ev = dmc620_pmu_c_event_table;
1775 evfence = dmc620_pmu_c_event_table +
1776 PMC_EVENT_TABLE_SIZE(dmc620_pmu_c);
1777 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
1778 ev = ppc7450_event_table;
1779 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
1780 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) {
1781 ev = ppc970_event_table;
1782 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970);
1783 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) {
1784 ev = e500_event_table;
1785 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500);
1786 } else if (pe == PMC_EV_TSC_TSC) {
1787 ev = tsc_event_table;
1788 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
1789 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) {
1790 ev = soft_event_table;
1791 evfence = soft_event_table + soft_event_info.pm_nevent;
1792 }
1793
1794 for (; ev != evfence; ev++)
1795 if (pe == ev->pm_ev_code)
1796 return (ev->pm_ev_name);
1797
1798 return (NULL);
1799 }
1800
1801 const char *
pmc_name_of_event(enum pmc_event pe)1802 pmc_name_of_event(enum pmc_event pe)
1803 {
1804 const char *n;
1805
1806 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
1807 return (n);
1808
1809 errno = EINVAL;
1810 return (NULL);
1811 }
1812
1813 const char *
pmc_name_of_mode(enum pmc_mode pm)1814 pmc_name_of_mode(enum pmc_mode pm)
1815 {
1816 if ((int) pm >= PMC_MODE_FIRST &&
1817 pm <= PMC_MODE_LAST)
1818 return (pmc_mode_names[pm]);
1819
1820 errno = EINVAL;
1821 return (NULL);
1822 }
1823
1824 const char *
pmc_name_of_state(enum pmc_state ps)1825 pmc_name_of_state(enum pmc_state ps)
1826 {
1827 if ((int) ps >= PMC_STATE_FIRST &&
1828 ps <= PMC_STATE_LAST)
1829 return (pmc_state_names[ps]);
1830
1831 errno = EINVAL;
1832 return (NULL);
1833 }
1834
1835 int
pmc_ncpu(void)1836 pmc_ncpu(void)
1837 {
1838 if (pmc_syscall == -1) {
1839 errno = ENXIO;
1840 return (-1);
1841 }
1842
1843 return (cpu_info.pm_ncpu);
1844 }
1845
1846 int
pmc_npmc(int cpu)1847 pmc_npmc(int cpu)
1848 {
1849 if (pmc_syscall == -1) {
1850 errno = ENXIO;
1851 return (-1);
1852 }
1853
1854 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
1855 errno = EINVAL;
1856 return (-1);
1857 }
1858
1859 return (cpu_info.pm_npmc);
1860 }
1861
1862 int
pmc_pmcinfo(int cpu,struct pmc_pmcinfo ** ppmci)1863 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
1864 {
1865 int nbytes, npmc;
1866 struct pmc_op_getpmcinfo *pmci;
1867
1868 if ((npmc = pmc_npmc(cpu)) < 0)
1869 return (-1);
1870
1871 nbytes = sizeof(struct pmc_op_getpmcinfo) +
1872 npmc * sizeof(struct pmc_info);
1873
1874 if ((pmci = calloc(1, nbytes)) == NULL)
1875 return (-1);
1876
1877 pmci->pm_cpu = cpu;
1878
1879 if (PMC_CALL(PMC_OP_GETPMCINFO, pmci) < 0) {
1880 free(pmci);
1881 return (-1);
1882 }
1883
1884 /* kernel<->library, library<->userland interfaces are identical */
1885 *ppmci = (struct pmc_pmcinfo *) pmci;
1886 return (0);
1887 }
1888
1889 int
pmc_read(pmc_id_t pmc,pmc_value_t * value)1890 pmc_read(pmc_id_t pmc, pmc_value_t *value)
1891 {
1892 struct pmc_op_pmcrw pmc_read_op;
1893
1894 pmc_read_op.pm_pmcid = pmc;
1895 pmc_read_op.pm_flags = PMC_F_OLDVALUE;
1896 pmc_read_op.pm_value = -1;
1897
1898 if (PMC_CALL(PMC_OP_PMCRW, &pmc_read_op) < 0)
1899 return (-1);
1900
1901 *value = pmc_read_op.pm_value;
1902 return (0);
1903 }
1904
1905 int
pmc_release(pmc_id_t pmc)1906 pmc_release(pmc_id_t pmc)
1907 {
1908 struct pmc_op_simple pmc_release_args;
1909
1910 pmc_release_args.pm_pmcid = pmc;
1911 return (PMC_CALL(PMC_OP_PMCRELEASE, &pmc_release_args));
1912 }
1913
1914 int
pmc_rw(pmc_id_t pmc,pmc_value_t newvalue,pmc_value_t * oldvaluep)1915 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
1916 {
1917 struct pmc_op_pmcrw pmc_rw_op;
1918
1919 pmc_rw_op.pm_pmcid = pmc;
1920 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
1921 pmc_rw_op.pm_value = newvalue;
1922
1923 if (PMC_CALL(PMC_OP_PMCRW, &pmc_rw_op) < 0)
1924 return (-1);
1925
1926 *oldvaluep = pmc_rw_op.pm_value;
1927 return (0);
1928 }
1929
1930 int
pmc_set(pmc_id_t pmc,pmc_value_t value)1931 pmc_set(pmc_id_t pmc, pmc_value_t value)
1932 {
1933 struct pmc_op_pmcsetcount sc;
1934
1935 sc.pm_pmcid = pmc;
1936 sc.pm_count = value;
1937
1938 if (PMC_CALL(PMC_OP_PMCSETCOUNT, &sc) < 0)
1939 return (-1);
1940 return (0);
1941 }
1942
1943 int
pmc_start(pmc_id_t pmc)1944 pmc_start(pmc_id_t pmc)
1945 {
1946 struct pmc_op_simple pmc_start_args;
1947
1948 pmc_start_args.pm_pmcid = pmc;
1949 return (PMC_CALL(PMC_OP_PMCSTART, &pmc_start_args));
1950 }
1951
1952 int
pmc_stop(pmc_id_t pmc)1953 pmc_stop(pmc_id_t pmc)
1954 {
1955 struct pmc_op_simple pmc_stop_args;
1956
1957 pmc_stop_args.pm_pmcid = pmc;
1958 return (PMC_CALL(PMC_OP_PMCSTOP, &pmc_stop_args));
1959 }
1960
1961 int
pmc_width(pmc_id_t pmcid,uint32_t * width)1962 pmc_width(pmc_id_t pmcid, uint32_t *width)
1963 {
1964 unsigned int i;
1965 enum pmc_class cl;
1966
1967 cl = PMC_ID_TO_CLASS(pmcid);
1968 for (i = 0; i < cpu_info.pm_nclass; i++)
1969 if (cpu_info.pm_classes[i].pm_class == cl) {
1970 *width = cpu_info.pm_classes[i].pm_width;
1971 return (0);
1972 }
1973 errno = EINVAL;
1974 return (-1);
1975 }
1976
1977 int
pmc_write(pmc_id_t pmc,pmc_value_t value)1978 pmc_write(pmc_id_t pmc, pmc_value_t value)
1979 {
1980 struct pmc_op_pmcrw pmc_write_op;
1981
1982 pmc_write_op.pm_pmcid = pmc;
1983 pmc_write_op.pm_flags = PMC_F_NEWVALUE;
1984 pmc_write_op.pm_value = value;
1985 return (PMC_CALL(PMC_OP_PMCRW, &pmc_write_op));
1986 }
1987
1988 int
pmc_writelog(uint32_t userdata)1989 pmc_writelog(uint32_t userdata)
1990 {
1991 struct pmc_op_writelog wl;
1992
1993 wl.pm_userdata = userdata;
1994 return (PMC_CALL(PMC_OP_WRITELOG, &wl));
1995 }
1996