1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __IRIS_PLATFORM_COMMON_H__ 7 #define __IRIS_PLATFORM_COMMON_H__ 8 9 #include <linux/bits.h> 10 11 struct iris_core; 12 struct iris_inst; 13 14 #define IRIS_PAS_ID 9 15 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ 16 #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */ 17 18 #define REGISTER_BIT_DEPTH(luma, chroma) ((luma) << 16 | (chroma)) 19 #define BIT_DEPTH_8 REGISTER_BIT_DEPTH(8, 8) 20 #define CODED_FRAMES_PROGRESSIVE 0x0 21 #define DEFAULT_MAX_HOST_BUF_COUNT 64 22 #define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256 23 #define DEFAULT_FPS 30 24 #define NUM_MBS_8K ((8192 * 4352) / 256) 25 26 enum stage_type { 27 STAGE_1 = 1, 28 STAGE_2 = 2, 29 }; 30 31 enum pipe_type { 32 PIPE_1 = 1, 33 PIPE_2 = 2, 34 PIPE_4 = 4, 35 }; 36 37 extern struct iris_platform_data qcs8300_data; 38 extern struct iris_platform_data sm8250_data; 39 extern struct iris_platform_data sm8550_data; 40 extern struct iris_platform_data sm8650_data; 41 42 enum platform_clk_type { 43 IRIS_AXI_CLK, 44 IRIS_CTRL_CLK, 45 IRIS_HW_CLK, 46 }; 47 48 struct platform_clk_data { 49 enum platform_clk_type clk_type; 50 const char *clk_name; 51 }; 52 53 struct tz_cp_config { 54 u32 cp_start; 55 u32 cp_size; 56 u32 cp_nonpixel_start; 57 u32 cp_nonpixel_size; 58 }; 59 60 struct ubwc_config_data { 61 u32 max_channels; 62 u32 mal_length; 63 u32 highest_bank_bit; 64 u32 bank_swzl_level; 65 u32 bank_swz2_level; 66 u32 bank_swz3_level; 67 u32 bank_spreading; 68 }; 69 70 struct platform_inst_caps { 71 u32 min_frame_width; 72 u32 max_frame_width; 73 u32 min_frame_height; 74 u32 max_frame_height; 75 u32 max_mbpf; 76 u32 mb_cycles_vsp; 77 u32 mb_cycles_vpp; 78 u32 mb_cycles_fw; 79 u32 mb_cycles_fw_vpp; 80 u32 num_comv; 81 }; 82 83 enum platform_inst_fw_cap_type { 84 PROFILE_H264 = 1, 85 PROFILE_HEVC, 86 PROFILE_VP9, 87 LEVEL_H264, 88 LEVEL_HEVC, 89 LEVEL_VP9, 90 INPUT_BUF_HOST_MAX_COUNT, 91 STAGE, 92 PIPE, 93 POC, 94 CODED_FRAMES, 95 BIT_DEPTH, 96 RAP_FRAME, 97 TIER, 98 INST_FW_CAP_MAX, 99 }; 100 101 enum platform_inst_fw_cap_flags { 102 CAP_FLAG_DYNAMIC_ALLOWED = BIT(0), 103 CAP_FLAG_MENU = BIT(1), 104 CAP_FLAG_INPUT_PORT = BIT(2), 105 CAP_FLAG_OUTPUT_PORT = BIT(3), 106 CAP_FLAG_CLIENT_SET = BIT(4), 107 CAP_FLAG_BITMASK = BIT(5), 108 CAP_FLAG_VOLATILE = BIT(6), 109 }; 110 111 struct platform_inst_fw_cap { 112 enum platform_inst_fw_cap_type cap_id; 113 s64 min; 114 s64 max; 115 s64 step_or_mask; 116 s64 value; 117 u32 hfi_id; 118 enum platform_inst_fw_cap_flags flags; 119 int (*set)(struct iris_inst *inst, 120 enum platform_inst_fw_cap_type cap_id); 121 }; 122 123 struct bw_info { 124 u32 mbs_per_sec; 125 u32 bw_ddr; 126 }; 127 128 struct iris_core_power { 129 u64 clk_freq; 130 u64 icc_bw; 131 }; 132 133 struct iris_inst_power { 134 u64 min_freq; 135 u32 icc_bw; 136 }; 137 138 struct icc_vote_data { 139 u32 height, width; 140 u32 fps; 141 }; 142 143 enum platform_pm_domain_type { 144 IRIS_CTRL_POWER_DOMAIN, 145 IRIS_HW_POWER_DOMAIN, 146 }; 147 148 struct iris_platform_data { 149 void (*init_hfi_command_ops)(struct iris_core *core); 150 void (*init_hfi_response_ops)(struct iris_core *core); 151 struct iris_inst *(*get_instance)(void); 152 const struct vpu_ops *vpu_ops; 153 void (*set_preset_registers)(struct iris_core *core); 154 const struct icc_info *icc_tbl; 155 unsigned int icc_tbl_size; 156 const struct bw_info *bw_tbl_dec; 157 unsigned int bw_tbl_dec_size; 158 const char * const *pmdomain_tbl; 159 unsigned int pmdomain_tbl_size; 160 const char * const *opp_pd_tbl; 161 unsigned int opp_pd_tbl_size; 162 const struct platform_clk_data *clk_tbl; 163 unsigned int clk_tbl_size; 164 const char * const *clk_rst_tbl; 165 unsigned int clk_rst_tbl_size; 166 const char * const *controller_rst_tbl; 167 unsigned int controller_rst_tbl_size; 168 u64 dma_mask; 169 const char *fwname; 170 u32 pas_id; 171 struct platform_inst_caps *inst_caps; 172 struct platform_inst_fw_cap *inst_fw_caps; 173 u32 inst_fw_caps_size; 174 struct tz_cp_config *tz_cp_config_data; 175 u32 core_arch; 176 u32 hw_response_timeout; 177 struct ubwc_config_data *ubwc_config; 178 u32 num_vpp_pipe; 179 u32 max_session_count; 180 /* max number of macroblocks per frame supported */ 181 u32 max_core_mbpf; 182 const u32 *input_config_params_default; 183 unsigned int input_config_params_default_size; 184 const u32 *input_config_params_hevc; 185 unsigned int input_config_params_hevc_size; 186 const u32 *input_config_params_vp9; 187 unsigned int input_config_params_vp9_size; 188 const u32 *output_config_params; 189 unsigned int output_config_params_size; 190 const u32 *dec_input_prop; 191 unsigned int dec_input_prop_size; 192 const u32 *dec_output_prop_avc; 193 unsigned int dec_output_prop_avc_size; 194 const u32 *dec_output_prop_hevc; 195 unsigned int dec_output_prop_hevc_size; 196 const u32 *dec_output_prop_vp9; 197 unsigned int dec_output_prop_vp9_size; 198 const u32 *dec_ip_int_buf_tbl; 199 unsigned int dec_ip_int_buf_tbl_size; 200 const u32 *dec_op_int_buf_tbl; 201 unsigned int dec_op_int_buf_tbl_size; 202 }; 203 204 #endif 205