1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * ISH registers definitions
4  *
5  * Copyright (c) 2012-2016, Intel Corporation.
6  */
7 
8 #ifndef _ISHTP_ISH_REGS_H_
9 #define _ISHTP_ISH_REGS_H_
10 
11 
12 /*** IPC PCI Offsets and sizes ***/
13 /* ISH IPC Base Address */
14 #define IPC_REG_BASE		0x0000
15 /* Peripheral Interrupt Status Register */
16 #define IPC_REG_PISR_CHV_AB      (IPC_REG_BASE + 0x00)
17 /* Peripheral Interrupt Mask Register */
18 #define IPC_REG_PIMR_CHV_AB      (IPC_REG_BASE + 0x04)
19 /*BXT, CHV_K0*/
20 /*Peripheral Interrupt Status Register */
21 #define IPC_REG_PISR_BXT	 (IPC_REG_BASE + 0x0C)
22 /*Peripheral Interrupt Mask Register */
23 #define IPC_REG_PIMR_BXT	 (IPC_REG_BASE + 0x08)
24 /***********************************/
25 /* ISH Host Firmware status Register */
26 #define IPC_REG_ISH_HOST_FWSTS	(IPC_REG_BASE + 0x34)
27 /* Host Communication Register */
28 #define IPC_REG_HOST_COMM	(IPC_REG_BASE + 0x38)
29 /* Reset register */
30 #define IPC_REG_ISH_RST		(IPC_REG_BASE + 0x44)
31 
32 /* Inbound doorbell register Host to ISH */
33 #define IPC_REG_HOST2ISH_DRBL	(IPC_REG_BASE + 0x48)
34 /* Outbound doorbell register ISH to Host */
35 #define IPC_REG_ISH2HOST_DRBL	(IPC_REG_BASE + 0x54)
36 /* ISH to HOST message registers */
37 #define IPC_REG_ISH2HOST_MSG	(IPC_REG_BASE + 0x60)
38 /* HOST to ISH message registers */
39 #define IPC_REG_HOST2ISH_MSG	(IPC_REG_BASE + 0xE0)
40 /* REMAP2 to enable DMA (D3 RCR) */
41 #define	IPC_REG_ISH_RMP2	(IPC_REG_BASE + 0x368)
42 
43 #define	IPC_REG_MAX		(IPC_REG_BASE + 0x400)
44 
45 /*** register bits - HISR ***/
46 /* bit corresponds HOST2ISH interrupt in PISR and PIMR registers */
47 #define IPC_INT_HOST2ISH_BIT            (1<<0)
48 /***********************************/
49 /*CHV_A0, CHV_B0*/
50 /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
51 #define IPC_INT_ISH2HOST_BIT_CHV_AB	(1<<3)
52 /*BXT, CHV_K0*/
53 /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
54 #define IPC_INT_ISH2HOST_BIT_BXT	(1<<0)
55 /***********************************/
56 
57 /* bit corresponds ISH2HOST busy clear interrupt in PIMR register */
58 #define IPC_INT_ISH2HOST_CLR_MASK_BIT	(1<<11)
59 
60 /* offset of ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
61 #define IPC_INT_ISH2HOST_CLR_OFFS	(0)
62 
63 /* bit corresponds ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
64 #define IPC_INT_ISH2HOST_CLR_BIT	(1<<IPC_INT_ISH2HOST_CLR_OFFS)
65 
66 /* bit corresponds busy bit in doorbell registers */
67 #define IPC_DRBL_BUSY_OFFS		(31)
68 #define IPC_DRBL_BUSY_BIT		(1<<IPC_DRBL_BUSY_OFFS)
69 
70 #define	IPC_HOST_OWNS_MSG_OFFS		(30)
71 
72 /*
73  * A0: bit means that host owns MSGnn registers and is reading them.
74  * ISH FW may not write to them
75  */
76 #define	IPC_HOST_OWNS_MSG_BIT		(1<<IPC_HOST_OWNS_MSG_OFFS)
77 
78 /*
79  * Host status bits (HOSTCOMM)
80  */
81 /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */
82 #define IPC_HOSTCOMM_READY_OFFS		(7)
83 #define IPC_HOSTCOMM_READY_BIT		(1<<IPC_HOSTCOMM_READY_OFFS)
84 
85 /***********************************/
86 /*CHV_A0, CHV_B0*/
87 #define	IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB	(31)
88 #define	IPC_HOSTCOMM_INT_EN_BIT_CHV_AB		\
89 	(1<<IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB)
90 /*BXT, CHV_K0*/
91 #define IPC_PIMR_INT_EN_OFFS_BXT	(0)
92 #define IPC_PIMR_INT_EN_BIT_BXT		(1<<IPC_PIMR_INT_EN_OFFS_BXT)
93 
94 #define IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT	(8)
95 #define IPC_HOST2ISH_BUSYCLEAR_MASK_BIT		\
96 	(1<<IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT)
97 /***********************************/
98 /*
99  * both Host and ISH have ILUP at bit 0
100  * bit corresponds host ready bit in both status registers
101  */
102 #define IPC_ILUP_OFFS			(0)
103 #define IPC_ILUP_BIT			(1<<IPC_ILUP_OFFS)
104 
105 /*
106  * ISH FW status bits in ISH FW Status Register
107  */
108 #define IPC_ISH_FWSTS_SHIFT		12
109 #define IPC_ISH_FWSTS_MASK		GENMASK(15, 12)
110 #define IPC_GET_ISH_FWSTS(status)	\
111 	(((status) & IPC_ISH_FWSTS_MASK) >> IPC_ISH_FWSTS_SHIFT)
112 
113 /*
114  * FW status bits (relevant)
115  */
116 #define	IPC_FWSTS_ILUP		0x1
117 #define	IPC_FWSTS_ISHTP_UP	(1<<1)
118 #define	IPC_FWSTS_DMA0		(1<<16)
119 #define	IPC_FWSTS_DMA1		(1<<17)
120 #define	IPC_FWSTS_DMA2		(1<<18)
121 #define	IPC_FWSTS_DMA3		(1<<19)
122 
123 #define	IPC_ISH_IN_DMA		\
124 	(IPC_FWSTS_DMA0 | IPC_FWSTS_DMA1 | IPC_FWSTS_DMA2 | IPC_FWSTS_DMA3)
125 
126 /* bit corresponds host ready bit in ISH FW Status Register */
127 #define IPC_ISH_ISHTP_READY_OFFS		(1)
128 #define IPC_ISH_ISHTP_READY_BIT		(1<<IPC_ISH_ISHTP_READY_OFFS)
129 
130 #define	IPC_RMP2_DMA_ENABLED	0x1	/* Value to enable DMA, per D3 RCR */
131 
132 #define IPC_MSG_MAX_SIZE	0x80
133 
134 
135 #define IPC_HEADER_LENGTH_MASK		0x03FF
136 #define IPC_HEADER_PROTOCOL_MASK	0x0F
137 #define IPC_HEADER_MNG_CMD_MASK		0x0F
138 
139 #define IPC_HEADER_LENGTH_OFFSET	0
140 #define IPC_HEADER_PROTOCOL_OFFSET	10
141 #define IPC_HEADER_MNG_CMD_OFFSET	16
142 
143 #define IPC_HEADER_GET_LENGTH(drbl_reg)		\
144 	(((drbl_reg) >> IPC_HEADER_LENGTH_OFFSET)&IPC_HEADER_LENGTH_MASK)
145 #define IPC_HEADER_GET_PROTOCOL(drbl_reg)	\
146 	(((drbl_reg) >> IPC_HEADER_PROTOCOL_OFFSET)&IPC_HEADER_PROTOCOL_MASK)
147 #define IPC_HEADER_GET_MNG_CMD(drbl_reg)	\
148 	(((drbl_reg) >> IPC_HEADER_MNG_CMD_OFFSET)&IPC_HEADER_MNG_CMD_MASK)
149 
150 #define IPC_IS_BUSY(drbl_reg)			\
151 	(((drbl_reg)&IPC_DRBL_BUSY_BIT) == ((uint32_t)IPC_DRBL_BUSY_BIT))
152 
153 /***********************************/
154 /*CHV_A0, CHV_B0*/
155 #define IPC_INT_FROM_ISH_TO_HOST_CHV_AB(drbl_reg) \
156 	(((drbl_reg)&IPC_INT_ISH2HOST_BIT_CHV_AB) == \
157 	((u32)IPC_INT_ISH2HOST_BIT_CHV_AB))
158 /*BXT, CHV_K0*/
159 #define IPC_INT_FROM_ISH_TO_HOST_BXT(drbl_reg) \
160 	(((drbl_reg)&IPC_INT_ISH2HOST_BIT_BXT) == \
161 	((u32)IPC_INT_ISH2HOST_BIT_BXT))
162 /***********************************/
163 
164 #define IPC_BUILD_HEADER(length, protocol, busy)		\
165 	(((busy)<<IPC_DRBL_BUSY_OFFS) |				\
166 	((protocol) << IPC_HEADER_PROTOCOL_OFFSET) |		\
167 	((length)<<IPC_HEADER_LENGTH_OFFSET))
168 
169 #define IPC_BUILD_MNG_MSG(cmd, length)				\
170 	(((1)<<IPC_DRBL_BUSY_OFFS)|				\
171 	((IPC_PROTOCOL_MNG)<<IPC_HEADER_PROTOCOL_OFFSET)|	\
172 	((cmd)<<IPC_HEADER_MNG_CMD_OFFSET)|			\
173 	 ((length)<<IPC_HEADER_LENGTH_OFFSET))
174 
175 
176 #define IPC_SET_HOST_READY(host_status)		\
177 				((host_status) |= (IPC_HOSTCOMM_READY_BIT))
178 
179 #define IPC_SET_HOST_ILUP(host_status)		\
180 				((host_status) |= (IPC_ILUP_BIT))
181 
182 #define IPC_CLEAR_HOST_READY(host_status)	\
183 				((host_status) ^= (IPC_HOSTCOMM_READY_BIT))
184 
185 #define IPC_CLEAR_HOST_ILUP(host_status)	\
186 				((host_status) ^= (IPC_ILUP_BIT))
187 
188 /* todo - temp until PIMR HW ready */
189 #define IPC_HOST_BUSY_READING_OFFS	6
190 
191 /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */
192 #define IPC_HOST_BUSY_READING_BIT	(1<<IPC_HOST_BUSY_READING_OFFS)
193 
194 #define IPC_SET_HOST_BUSY_READING(host_status)	\
195 				((host_status) |= (IPC_HOST_BUSY_READING_BIT))
196 
197 #define IPC_CLEAR_HOST_BUSY_READING(host_status)\
198 				((host_status) ^= (IPC_HOST_BUSY_READING_BIT))
199 
200 
201 #define IPC_IS_ISH_ISHTP_READY(ish_status)	\
202 		(((ish_status) & IPC_ISH_ISHTP_READY_BIT) ==	\
203 			((uint32_t)IPC_ISH_ISHTP_READY_BIT))
204 
205 #define IPC_IS_ISH_ILUP(ish_status)		\
206 		(((ish_status) & IPC_ILUP_BIT) == ((uint32_t)IPC_ILUP_BIT))
207 
208 
209 #define IPC_PROTOCOL_ISHTP		1
210 #define IPC_PROTOCOL_MNG		3
211 
212 #define MNG_RX_CMPL_ENABLE		0
213 #define MNG_RX_CMPL_DISABLE		1
214 #define MNG_RX_CMPL_INDICATION		2
215 #define MNG_RESET_NOTIFY		3
216 #define MNG_RESET_NOTIFY_ACK		4
217 #define MNG_SYNC_FW_CLOCK		5
218 #define MNG_ILLEGAL_CMD			0xFF
219 
220 #endif /* _ISHTP_ISH_REGS_H_ */
221