1 /*
2 * QEMU PCI test device
3 *
4 * Copyright (c) 2012 Red Hat Inc.
5 * Author: Michael S. Tsirkin <mst@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/pci/pci_device.h"
23 #include "hw/qdev-properties.h"
24 #include "qemu/event_notifier.h"
25 #include "qemu/module.h"
26 #include "system/kvm.h"
27 #include "qom/object.h"
28
29 typedef struct PCITestDevHdr {
30 uint8_t test;
31 uint8_t width;
32 uint8_t pad0[2];
33 uint32_t offset;
34 uint8_t data;
35 uint8_t pad1[3];
36 uint32_t count;
37 uint8_t name[];
38 } PCITestDevHdr;
39
40 typedef struct IOTest {
41 MemoryRegion *mr;
42 EventNotifier notifier;
43 bool hasnotifier;
44 unsigned size;
45 bool match_data;
46 PCITestDevHdr *hdr;
47 unsigned bufsize;
48 } IOTest;
49
50 #define IOTEST_DATAMATCH 0xFA
51 #define IOTEST_NOMATCH 0xCE
52
53 #define IOTEST_IOSIZE 128
54 #define IOTEST_MEMSIZE 2048
55
56 static const char *iotest_test[] = {
57 "no-eventfd",
58 "wildcard-eventfd",
59 "datamatch-eventfd"
60 };
61
62 static const char *iotest_type[] = {
63 "mmio",
64 "portio"
65 };
66
67 #define IOTEST_TEST(i) (iotest_test[((i) % ARRAY_SIZE(iotest_test))])
68 #define IOTEST_TYPE(i) (iotest_type[((i) / ARRAY_SIZE(iotest_test))])
69 #define IOTEST_MAX_TEST (ARRAY_SIZE(iotest_test))
70 #define IOTEST_MAX_TYPE (ARRAY_SIZE(iotest_type))
71 #define IOTEST_MAX (IOTEST_MAX_TEST * IOTEST_MAX_TYPE)
72
73 enum {
74 IOTEST_ACCESS_NAME,
75 IOTEST_ACCESS_DATA,
76 IOTEST_ACCESS_MAX,
77 };
78
79 #define IOTEST_ACCESS_TYPE uint8_t
80 #define IOTEST_ACCESS_WIDTH (sizeof(uint8_t))
81
82 struct PCITestDevState {
83 /*< private >*/
84 PCIDevice parent_obj;
85 /*< public >*/
86
87 MemoryRegion mmio;
88 MemoryRegion portio;
89 IOTest *tests;
90 int current;
91
92 uint64_t membar_size;
93 bool membar_backed;
94 MemoryRegion membar;
95 };
96
97 #define TYPE_PCI_TEST_DEV "pci-testdev"
98
OBJECT_DECLARE_SIMPLE_TYPE(PCITestDevState,PCI_TEST_DEV)99 OBJECT_DECLARE_SIMPLE_TYPE(PCITestDevState, PCI_TEST_DEV)
100
101 #define IOTEST_IS_MEM(i) (strcmp(IOTEST_TYPE(i), "portio"))
102 #define IOTEST_REGION(d, i) (IOTEST_IS_MEM(i) ? &(d)->mmio : &(d)->portio)
103 #define IOTEST_SIZE(i) (IOTEST_IS_MEM(i) ? IOTEST_MEMSIZE : IOTEST_IOSIZE)
104 #define IOTEST_PCI_BAR(i) (IOTEST_IS_MEM(i) ? PCI_BASE_ADDRESS_SPACE_MEMORY : \
105 PCI_BASE_ADDRESS_SPACE_IO)
106
107 static int pci_testdev_start(IOTest *test)
108 {
109 test->hdr->count = 0;
110 if (!test->hasnotifier) {
111 return 0;
112 }
113 event_notifier_test_and_clear(&test->notifier);
114 memory_region_add_eventfd(test->mr,
115 le32_to_cpu(test->hdr->offset),
116 test->size,
117 test->match_data,
118 test->hdr->data,
119 &test->notifier);
120 return 0;
121 }
122
pci_testdev_stop(IOTest * test)123 static void pci_testdev_stop(IOTest *test)
124 {
125 if (!test->hasnotifier) {
126 return;
127 }
128 memory_region_del_eventfd(test->mr,
129 le32_to_cpu(test->hdr->offset),
130 test->size,
131 test->match_data,
132 test->hdr->data,
133 &test->notifier);
134 }
135
136 static void
pci_testdev_reset(PCITestDevState * d)137 pci_testdev_reset(PCITestDevState *d)
138 {
139 if (d->current == -1) {
140 return;
141 }
142 pci_testdev_stop(&d->tests[d->current]);
143 d->current = -1;
144 }
145
pci_testdev_inc(IOTest * test,unsigned inc)146 static void pci_testdev_inc(IOTest *test, unsigned inc)
147 {
148 uint32_t c = le32_to_cpu(test->hdr->count);
149 test->hdr->count = cpu_to_le32(c + inc);
150 }
151
152 static void
pci_testdev_write(void * opaque,hwaddr addr,uint64_t val,unsigned size,int type)153 pci_testdev_write(void *opaque, hwaddr addr, uint64_t val,
154 unsigned size, int type)
155 {
156 PCITestDevState *d = opaque;
157 IOTest *test;
158 int t, r;
159
160 if (addr == offsetof(PCITestDevHdr, test)) {
161 pci_testdev_reset(d);
162 if (val >= IOTEST_MAX_TEST) {
163 return;
164 }
165 t = type * IOTEST_MAX_TEST + val;
166 r = pci_testdev_start(&d->tests[t]);
167 if (r < 0) {
168 return;
169 }
170 d->current = t;
171 return;
172 }
173 if (d->current < 0) {
174 return;
175 }
176 test = &d->tests[d->current];
177 if (addr != le32_to_cpu(test->hdr->offset)) {
178 return;
179 }
180 if (test->match_data && test->size != size) {
181 return;
182 }
183 if (test->match_data && val != test->hdr->data) {
184 return;
185 }
186 pci_testdev_inc(test, 1);
187 }
188
189 static uint64_t
pci_testdev_read(void * opaque,hwaddr addr,unsigned size)190 pci_testdev_read(void *opaque, hwaddr addr, unsigned size)
191 {
192 PCITestDevState *d = opaque;
193 const char *buf;
194 IOTest *test;
195 if (d->current < 0) {
196 return 0;
197 }
198 test = &d->tests[d->current];
199 buf = (const char *)test->hdr;
200 if (addr + size >= test->bufsize) {
201 return 0;
202 }
203 if (test->hasnotifier) {
204 event_notifier_test_and_clear(&test->notifier);
205 }
206 return buf[addr];
207 }
208
209 static void
pci_testdev_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)210 pci_testdev_mmio_write(void *opaque, hwaddr addr, uint64_t val,
211 unsigned size)
212 {
213 pci_testdev_write(opaque, addr, val, size, 0);
214 }
215
216 static void
pci_testdev_pio_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)217 pci_testdev_pio_write(void *opaque, hwaddr addr, uint64_t val,
218 unsigned size)
219 {
220 pci_testdev_write(opaque, addr, val, size, 1);
221 }
222
223 static const MemoryRegionOps pci_testdev_mmio_ops = {
224 .read = pci_testdev_read,
225 .write = pci_testdev_mmio_write,
226 .endianness = DEVICE_LITTLE_ENDIAN,
227 .impl = {
228 .min_access_size = 1,
229 .max_access_size = 1,
230 },
231 };
232
233 static const MemoryRegionOps pci_testdev_pio_ops = {
234 .read = pci_testdev_read,
235 .write = pci_testdev_pio_write,
236 .endianness = DEVICE_LITTLE_ENDIAN,
237 .impl = {
238 .min_access_size = 1,
239 .max_access_size = 1,
240 },
241 };
242
pci_testdev_realize(PCIDevice * pci_dev,Error ** errp)243 static void pci_testdev_realize(PCIDevice *pci_dev, Error **errp)
244 {
245 PCITestDevState *d = PCI_TEST_DEV(pci_dev);
246 uint8_t *pci_conf;
247 char *name;
248 int r, i;
249
250 pci_conf = pci_dev->config;
251
252 pci_conf[PCI_INTERRUPT_PIN] = 0; /* no interrupt pin */
253
254 memory_region_init_io(&d->mmio, OBJECT(d), &pci_testdev_mmio_ops, d,
255 "pci-testdev-mmio", IOTEST_MEMSIZE * 2);
256 memory_region_init_io(&d->portio, OBJECT(d), &pci_testdev_pio_ops, d,
257 "pci-testdev-portio", IOTEST_IOSIZE * 2);
258 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
259 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->portio);
260
261 if (d->membar_size) {
262 if (d->membar_backed)
263 memory_region_init_ram(&d->membar, OBJECT(d),
264 "pci-testdev-membar-backed",
265 d->membar_size, NULL);
266 else
267 memory_region_init(&d->membar, OBJECT(d),
268 "pci-testdev-membar",
269 d->membar_size);
270 pci_register_bar(pci_dev, 2,
271 PCI_BASE_ADDRESS_SPACE_MEMORY |
272 PCI_BASE_ADDRESS_MEM_PREFETCH |
273 PCI_BASE_ADDRESS_MEM_TYPE_64,
274 &d->membar);
275 }
276
277 d->current = -1;
278 d->tests = g_malloc0(IOTEST_MAX * sizeof *d->tests);
279 for (i = 0; i < IOTEST_MAX; ++i) {
280 IOTest *test = &d->tests[i];
281 name = g_strdup_printf("%s-%s", IOTEST_TYPE(i), IOTEST_TEST(i));
282 test->bufsize = sizeof(PCITestDevHdr) + strlen(name) + 1;
283 test->hdr = g_malloc0(test->bufsize);
284 memcpy(test->hdr->name, name, strlen(name) + 1);
285 g_free(name);
286 test->hdr->offset = cpu_to_le32(IOTEST_SIZE(i) + i * IOTEST_ACCESS_WIDTH);
287 test->match_data = strcmp(IOTEST_TEST(i), "wildcard-eventfd");
288 if (IOTEST_IS_MEM(i) && !test->match_data) {
289 test->size = 0;
290 } else {
291 test->size = IOTEST_ACCESS_WIDTH;
292 }
293 test->hdr->test = i;
294 test->hdr->data = test->match_data ? IOTEST_DATAMATCH : IOTEST_NOMATCH;
295 test->hdr->width = IOTEST_ACCESS_WIDTH;
296 test->mr = IOTEST_REGION(d, i);
297 if (!strcmp(IOTEST_TEST(i), "no-eventfd")) {
298 test->hasnotifier = false;
299 continue;
300 }
301 r = event_notifier_init(&test->notifier, 0);
302 assert(r >= 0);
303 test->hasnotifier = true;
304 }
305 }
306
307 static void
pci_testdev_uninit(PCIDevice * dev)308 pci_testdev_uninit(PCIDevice *dev)
309 {
310 PCITestDevState *d = PCI_TEST_DEV(dev);
311 int i;
312
313 pci_testdev_reset(d);
314 for (i = 0; i < IOTEST_MAX; ++i) {
315 if (d->tests[i].hasnotifier) {
316 event_notifier_cleanup(&d->tests[i].notifier);
317 }
318 g_free(d->tests[i].hdr);
319 }
320 g_free(d->tests);
321 }
322
qdev_pci_testdev_reset(DeviceState * dev)323 static void qdev_pci_testdev_reset(DeviceState *dev)
324 {
325 PCITestDevState *d = PCI_TEST_DEV(dev);
326 pci_testdev_reset(d);
327 }
328
329 static const Property pci_testdev_properties[] = {
330 DEFINE_PROP_SIZE("membar", PCITestDevState, membar_size, 0),
331 DEFINE_PROP_BOOL("membar-backed", PCITestDevState, membar_backed, false),
332 };
333
pci_testdev_class_init(ObjectClass * klass,const void * data)334 static void pci_testdev_class_init(ObjectClass *klass, const void *data)
335 {
336 DeviceClass *dc = DEVICE_CLASS(klass);
337 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
338
339 k->realize = pci_testdev_realize;
340 k->exit = pci_testdev_uninit;
341 k->vendor_id = PCI_VENDOR_ID_REDHAT;
342 k->device_id = PCI_DEVICE_ID_REDHAT_TEST;
343 k->revision = 0x00;
344 k->class_id = PCI_CLASS_OTHERS;
345 dc->desc = "PCI Test Device";
346 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
347 device_class_set_legacy_reset(dc, qdev_pci_testdev_reset);
348 device_class_set_props(dc, pci_testdev_properties);
349 }
350
351 static const TypeInfo pci_testdev_info = {
352 .name = TYPE_PCI_TEST_DEV,
353 .parent = TYPE_PCI_DEVICE,
354 .instance_size = sizeof(PCITestDevState),
355 .class_init = pci_testdev_class_init,
356 .interfaces = (const InterfaceInfo[]) {
357 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
358 { },
359 },
360 };
361
pci_testdev_register_types(void)362 static void pci_testdev_register_types(void)
363 {
364 type_register_static(&pci_testdev_info);
365 }
366
367 type_init(pci_testdev_register_types)
368