1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8 #define IONIC_DEV_INFO_VERSION 1 9 #define IONIC_IFNAMSIZ 16 10 11 /* 12 * enum ionic_cmd_opcode - Device commands 13 */ 14 enum ionic_cmd_opcode { 15 IONIC_CMD_NOP = 0, 16 17 /* Device commands */ 18 IONIC_CMD_IDENTIFY = 1, 19 IONIC_CMD_INIT = 2, 20 IONIC_CMD_RESET = 3, 21 IONIC_CMD_GETATTR = 4, 22 IONIC_CMD_SETATTR = 5, 23 24 /* Port commands */ 25 IONIC_CMD_PORT_IDENTIFY = 10, 26 IONIC_CMD_PORT_INIT = 11, 27 IONIC_CMD_PORT_RESET = 12, 28 IONIC_CMD_PORT_GETATTR = 13, 29 IONIC_CMD_PORT_SETATTR = 14, 30 31 /* LIF commands */ 32 IONIC_CMD_LIF_IDENTIFY = 20, 33 IONIC_CMD_LIF_INIT = 21, 34 IONIC_CMD_LIF_RESET = 22, 35 IONIC_CMD_LIF_GETATTR = 23, 36 IONIC_CMD_LIF_SETATTR = 24, 37 IONIC_CMD_LIF_SETPHC = 25, 38 39 IONIC_CMD_RX_MODE_SET = 30, 40 IONIC_CMD_RX_FILTER_ADD = 31, 41 IONIC_CMD_RX_FILTER_DEL = 32, 42 43 /* Queue commands */ 44 IONIC_CMD_Q_IDENTIFY = 39, 45 IONIC_CMD_Q_INIT = 40, 46 IONIC_CMD_Q_CONTROL = 41, 47 48 /* RDMA commands */ 49 IONIC_CMD_RDMA_RESET_LIF = 50, 50 IONIC_CMD_RDMA_CREATE_EQ = 51, 51 IONIC_CMD_RDMA_CREATE_CQ = 52, 52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 53 54 /* SR/IOV commands */ 55 IONIC_CMD_VF_GETATTR = 60, 56 IONIC_CMD_VF_SETATTR = 61, 57 IONIC_CMD_VF_CTRL = 62, 58 59 /* CMB command */ 60 IONIC_CMD_DISCOVER_CMB = 80, 61 62 /* QoS commands */ 63 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 64 IONIC_CMD_QOS_CLASS_INIT = 241, 65 IONIC_CMD_QOS_CLASS_RESET = 242, 66 IONIC_CMD_QOS_CLASS_UPDATE = 243, 67 IONIC_CMD_QOS_CLEAR_STATS = 244, 68 IONIC_CMD_QOS_RESET = 245, 69 70 /* Firmware commands */ 71 IONIC_CMD_FW_DOWNLOAD = 252, 72 IONIC_CMD_FW_CONTROL = 253, 73 IONIC_CMD_FW_DOWNLOAD_V1 = 254, 74 IONIC_CMD_FW_CONTROL_V1 = 255, 75 }; 76 77 /* 78 * enum ionic_status_code - Device command return codes 79 */ 80 enum ionic_status_code { 81 IONIC_RC_SUCCESS = 0, /* Success */ 82 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 83 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 84 IONIC_RC_EIO = 3, /* I/O error */ 85 IONIC_RC_EPERM = 4, /* Permission denied */ 86 IONIC_RC_EQID = 5, /* Bad qid */ 87 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 88 IONIC_RC_ENOENT = 7, /* No such element */ 89 IONIC_RC_EINTR = 8, /* operation interrupted */ 90 IONIC_RC_EAGAIN = 9, /* Try again */ 91 IONIC_RC_ENOMEM = 10, /* Out of memory */ 92 IONIC_RC_EFAULT = 11, /* Bad address */ 93 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 94 IONIC_RC_EEXIST = 13, /* object already exists */ 95 IONIC_RC_EINVAL = 14, /* Invalid argument */ 96 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 97 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 98 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 99 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 100 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 101 IONIC_RC_ERROR = 29, /* Generic error */ 102 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 103 IONIC_RC_EVFID = 31, /* VF ID does not exist */ 104 IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */ 105 }; 106 107 enum ionic_notifyq_opcode { 108 IONIC_EVENT_LINK_CHANGE = 1, 109 IONIC_EVENT_RESET = 2, 110 IONIC_EVENT_HEARTBEAT = 3, 111 IONIC_EVENT_LOG = 4, 112 IONIC_EVENT_XCVR = 5, 113 }; 114 115 /** 116 * struct ionic_admin_cmd - General admin command format 117 * @opcode: Opcode for the command 118 * @rsvd: reserved byte(s) 119 * @lif_index: LIF index 120 * @cmd_data: Opcode-specific command bytes 121 */ 122 struct ionic_admin_cmd { 123 u8 opcode; 124 u8 rsvd; 125 __le16 lif_index; 126 u8 cmd_data[60]; 127 }; 128 129 /** 130 * struct ionic_admin_comp - General admin command completion format 131 * @status: Status of the command (enum ionic_status_code) 132 * @rsvd: reserved byte(s) 133 * @comp_index: Index in the descriptor ring for which this is the completion 134 * @cmd_data: Command-specific bytes 135 * @color: Color bit (Always 0 for commands issued to the 136 * Device Cmd Registers) 137 */ 138 struct ionic_admin_comp { 139 u8 status; 140 u8 rsvd; 141 __le16 comp_index; 142 u8 cmd_data[11]; 143 u8 color; 144 #define IONIC_COMP_COLOR_MASK 0x80 145 }; 146 147 static inline u8 color_match(u8 color, u8 done_color) 148 { 149 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 150 } 151 152 /** 153 * struct ionic_nop_cmd - NOP command 154 * @opcode: opcode 155 * @rsvd: reserved byte(s) 156 */ 157 struct ionic_nop_cmd { 158 u8 opcode; 159 u8 rsvd[63]; 160 }; 161 162 /** 163 * struct ionic_nop_comp - NOP command completion 164 * @status: Status of the command (enum ionic_status_code) 165 * @rsvd: reserved byte(s) 166 */ 167 struct ionic_nop_comp { 168 u8 status; 169 u8 rsvd[15]; 170 }; 171 172 /** 173 * struct ionic_dev_init_cmd - Device init command 174 * @opcode: opcode 175 * @type: Device type 176 * @rsvd: reserved byte(s) 177 */ 178 struct ionic_dev_init_cmd { 179 u8 opcode; 180 u8 type; 181 u8 rsvd[62]; 182 }; 183 184 /** 185 * struct ionic_dev_init_comp - Device init command completion 186 * @status: Status of the command (enum ionic_status_code) 187 * @rsvd: reserved byte(s) 188 */ 189 struct ionic_dev_init_comp { 190 u8 status; 191 u8 rsvd[15]; 192 }; 193 194 /** 195 * struct ionic_dev_reset_cmd - Device reset command 196 * @opcode: opcode 197 * @rsvd: reserved byte(s) 198 */ 199 struct ionic_dev_reset_cmd { 200 u8 opcode; 201 u8 rsvd[63]; 202 }; 203 204 /** 205 * struct ionic_dev_reset_comp - Reset command completion 206 * @status: Status of the command (enum ionic_status_code) 207 * @rsvd: reserved byte(s) 208 */ 209 struct ionic_dev_reset_comp { 210 u8 status; 211 u8 rsvd[15]; 212 }; 213 214 #define IONIC_IDENTITY_VERSION_1 1 215 #define IONIC_DEV_IDENTITY_VERSION_2 2 216 217 /** 218 * struct ionic_dev_identify_cmd - Driver/device identify command 219 * @opcode: opcode 220 * @ver: Highest version of identify supported by driver 221 * @rsvd: reserved byte(s) 222 */ 223 struct ionic_dev_identify_cmd { 224 u8 opcode; 225 u8 ver; 226 u8 rsvd[62]; 227 }; 228 229 /** 230 * struct ionic_dev_identify_comp - Driver/device identify command completion 231 * @status: Status of the command (enum ionic_status_code) 232 * @ver: Version of identify returned by device 233 * @rsvd: reserved byte(s) 234 */ 235 struct ionic_dev_identify_comp { 236 u8 status; 237 u8 ver; 238 u8 rsvd[14]; 239 }; 240 241 enum ionic_os_type { 242 IONIC_OS_TYPE_LINUX = 1, 243 IONIC_OS_TYPE_WIN = 2, 244 IONIC_OS_TYPE_DPDK = 3, 245 IONIC_OS_TYPE_FREEBSD = 4, 246 IONIC_OS_TYPE_IPXE = 5, 247 IONIC_OS_TYPE_ESXI = 6, 248 }; 249 250 /** 251 * union ionic_drv_identity - driver identity information 252 * @os_type: OS type (see enum ionic_os_type) 253 * @os_dist: OS distribution, numeric format 254 * @os_dist_str: OS distribution, string format 255 * @kernel_ver: Kernel version, numeric format 256 * @kernel_ver_str: Kernel version, string format 257 * @driver_ver_str: Driver version, string format 258 * @words: word access to struct contents 259 */ 260 union ionic_drv_identity { 261 struct { 262 __le32 os_type; 263 __le32 os_dist; 264 char os_dist_str[128]; 265 __le32 kernel_ver; 266 char kernel_ver_str[32]; 267 char driver_ver_str[32]; 268 }; 269 __le32 words[478]; 270 }; 271 272 /** 273 * enum ionic_dev_capability - Device capabilities 274 * @IONIC_DEV_CAP_VF_CTRL: Device supports VF ctrl operations 275 * @IONIC_DEV_CAP_DISC_CMB: Device supports CMB discovery operations 276 */ 277 enum ionic_dev_capability { 278 IONIC_DEV_CAP_VF_CTRL = BIT(0), 279 IONIC_DEV_CAP_DISC_CMB = BIT(1), 280 }; 281 282 /** 283 * union ionic_dev_identity - device identity information 284 * @version: Version of device identify 285 * @type: Identify type (0 for now) 286 * @rsvd: reserved byte(s) 287 * @nports: Number of ports provisioned 288 * @rsvd2: reserved byte(s) 289 * @nlifs: Number of LIFs provisioned 290 * @nintrs: Number of interrupts provisioned 291 * @ndbpgs_per_lif: Number of doorbell pages per LIF 292 * @intr_coal_mult: Interrupt coalescing multiplication factor 293 * Scale user-supplied interrupt coalescing 294 * value in usecs to device units using: 295 * device units = usecs * mult / div 296 * @intr_coal_div: Interrupt coalescing division factor 297 * Scale user-supplied interrupt coalescing 298 * value in usecs to device units using: 299 * device units = usecs * mult / div 300 * @eq_count: Number of shared event queues 301 * @hwstamp_mask: Bitmask for subtraction of hardware tick values. 302 * @hwstamp_mult: Hardware tick to nanosecond multiplier. 303 * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). 304 * @capabilities: Device capabilities 305 * @words: word access to struct contents 306 */ 307 union ionic_dev_identity { 308 struct { 309 u8 version; 310 u8 type; 311 u8 rsvd[2]; 312 u8 nports; 313 u8 rsvd2[3]; 314 __le32 nlifs; 315 __le32 nintrs; 316 __le32 ndbpgs_per_lif; 317 __le32 intr_coal_mult; 318 __le32 intr_coal_div; 319 __le32 eq_count; 320 __le64 hwstamp_mask; 321 __le32 hwstamp_mult; 322 __le32 hwstamp_shift; 323 __le64 capabilities; 324 }; 325 __le32 words[478]; 326 }; 327 328 enum ionic_lif_type { 329 IONIC_LIF_TYPE_CLASSIC = 0, 330 IONIC_LIF_TYPE_MACVLAN = 1, 331 IONIC_LIF_TYPE_NETQUEUE = 2, 332 }; 333 334 /** 335 * struct ionic_lif_identify_cmd - LIF identify command 336 * @opcode: opcode 337 * @type: LIF type (enum ionic_lif_type) 338 * @ver: Version of identify returned by device 339 * @rsvd: reserved byte(s) 340 */ 341 struct ionic_lif_identify_cmd { 342 u8 opcode; 343 u8 type; 344 u8 ver; 345 u8 rsvd[61]; 346 }; 347 348 /** 349 * struct ionic_lif_identify_comp - LIF identify command completion 350 * @status: Status of the command (enum ionic_status_code) 351 * @ver: Version of identify returned by device 352 * @rsvd2: reserved byte(s) 353 */ 354 struct ionic_lif_identify_comp { 355 u8 status; 356 u8 ver; 357 u8 rsvd2[14]; 358 }; 359 360 /** 361 * enum ionic_lif_capability - LIF capabilities 362 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 363 * @IONIC_LIF_CAP_RDMA: LIF supports RDMA 364 */ 365 enum ionic_lif_capability { 366 IONIC_LIF_CAP_ETH = BIT(0), 367 IONIC_LIF_CAP_RDMA = BIT(1), 368 }; 369 370 /** 371 * enum ionic_logical_qtype - Logical Queue Types 372 * @IONIC_QTYPE_ADMINQ: Administrative Queue 373 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 374 * @IONIC_QTYPE_RXQ: Receive Queue 375 * @IONIC_QTYPE_TXQ: Transmit Queue 376 * @IONIC_QTYPE_EQ: Event Queue 377 * @IONIC_QTYPE_MAX: Max queue type supported 378 */ 379 enum ionic_logical_qtype { 380 IONIC_QTYPE_ADMINQ = 0, 381 IONIC_QTYPE_NOTIFYQ = 1, 382 IONIC_QTYPE_RXQ = 2, 383 IONIC_QTYPE_TXQ = 3, 384 IONIC_QTYPE_EQ = 4, 385 IONIC_QTYPE_MAX = 16, 386 }; 387 388 /** 389 * enum ionic_q_feature - Common Features for most queue types 390 * 391 * Common features use bits 0-15. Per-queue-type features use higher bits. 392 * 393 * @IONIC_QIDENT_F_CQ: Queue has completion ring 394 * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring 395 * @IONIC_QIDENT_F_EQ: Queue can use event queue 396 * @IONIC_QIDENT_F_CMB: Queue is in cmb bar 397 * @IONIC_Q_F_2X_DESC: Double main descriptor size 398 * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size 399 * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size 400 * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size 401 * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size 402 * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size 403 * @IONIC_QIDENT_F_EXPDB: Queue supports express doorbell 404 */ 405 enum ionic_q_feature { 406 IONIC_QIDENT_F_CQ = BIT_ULL(0), 407 IONIC_QIDENT_F_SG = BIT_ULL(1), 408 IONIC_QIDENT_F_EQ = BIT_ULL(2), 409 IONIC_QIDENT_F_CMB = BIT_ULL(3), 410 IONIC_Q_F_2X_DESC = BIT_ULL(4), 411 IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5), 412 IONIC_Q_F_2X_SG_DESC = BIT_ULL(6), 413 IONIC_Q_F_4X_DESC = BIT_ULL(7), 414 IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8), 415 IONIC_Q_F_4X_SG_DESC = BIT_ULL(9), 416 IONIC_QIDENT_F_EXPDB = BIT_ULL(10), 417 }; 418 419 /** 420 * enum ionic_rxq_feature - RXQ-specific Features 421 * 422 * Per-queue-type features use bits 16 and higher. 423 * 424 * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping 425 */ 426 enum ionic_rxq_feature { 427 IONIC_RXQ_F_HWSTAMP = BIT_ULL(16), 428 }; 429 430 /** 431 * enum ionic_txq_feature - TXQ-specific Features 432 * 433 * Per-queue-type features use bits 16 and higher. 434 * 435 * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping 436 */ 437 enum ionic_txq_feature { 438 IONIC_TXQ_F_HWSTAMP = BIT(16), 439 }; 440 441 /** 442 * enum ionic_hwstamp_bits - Hardware timestamp decoding bits 443 * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value 444 * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset 445 * from the base cq descriptor. 446 */ 447 enum ionic_hwstamp_bits { 448 IONIC_HWSTAMP_INVALID = ~0ull, 449 IONIC_HWSTAMP_CQ_NEGOFFSET = 8, 450 }; 451 452 /** 453 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 454 * @qtype: Hardware Queue Type 455 * @rsvd: reserved byte(s) 456 * @qid_count: Number of Queue IDs of the logical type 457 * @qid_base: Minimum Queue ID of the logical type 458 */ 459 struct ionic_lif_logical_qtype { 460 u8 qtype; 461 u8 rsvd[3]; 462 __le32 qid_count; 463 __le32 qid_base; 464 }; 465 466 /** 467 * enum ionic_lif_state - LIF state 468 * @IONIC_LIF_DISABLE: LIF disabled 469 * @IONIC_LIF_ENABLE: LIF enabled 470 * @IONIC_LIF_QUIESCE: LIF Quiesced 471 */ 472 enum ionic_lif_state { 473 IONIC_LIF_QUIESCE = 0, 474 IONIC_LIF_ENABLE = 1, 475 IONIC_LIF_DISABLE = 2, 476 }; 477 478 /** 479 * union ionic_lif_config - LIF configuration 480 * @state: LIF state (enum ionic_lif_state) 481 * @rsvd: reserved byte(s) 482 * @name: LIF name 483 * @mtu: MTU 484 * @mac: Station MAC address 485 * @vlan: Default Vlan ID 486 * @features: Features (enum ionic_eth_hw_features) 487 * @queue_count: Queue counts per queue-type 488 * @words: word access to struct contents 489 */ 490 union ionic_lif_config { 491 struct { 492 u8 state; 493 u8 rsvd[3]; 494 char name[IONIC_IFNAMSIZ]; 495 __le32 mtu; 496 u8 mac[6]; 497 __le16 vlan; 498 __le64 features; 499 __le32 queue_count[IONIC_QTYPE_MAX]; 500 } __packed; 501 __le32 words[64]; 502 }; 503 504 /** 505 * enum ionic_lif_rdma_cap_stats - LIF stat type 506 * @IONIC_LIF_RDMA_STAT_GLOBAL: Global stats 507 * @IONIC_LIF_RDMA_STAT_QP: Queue pair stats 508 */ 509 enum ionic_lif_rdma_cap_stats { 510 IONIC_LIF_RDMA_STAT_GLOBAL = BIT(0), 511 IONIC_LIF_RDMA_STAT_QP = BIT(1), 512 }; 513 514 /** 515 * struct ionic_lif_identity - LIF identity information (type-specific) 516 * 517 * @capabilities: LIF capabilities 518 * 519 * @eth: Ethernet identify structure 520 * @eth.version: Ethernet identify structure version 521 * @eth.rsvd: reserved byte(s) 522 * @eth.max_ucast_filters: Number of perfect unicast addresses supported 523 * @eth.max_mcast_filters: Number of perfect multicast addresses supported 524 * @eth.min_frame_size: Minimum size of frames to be sent 525 * @eth.max_frame_size: Maximum size of frames to be sent 526 * @eth.rsvd2: reserved byte(s) 527 * @eth.hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) 528 * @eth.hwstamp_rx_filters: Bitmask of enum ionic_pkt_class 529 * @eth.rsvd3: reserved byte(s) 530 * @eth.config: LIF config struct with features, mtu, mac, q counts 531 * 532 * @rdma: RDMA identify structure 533 * @rdma.version: RDMA capability version 534 * @rdma.qp_opcodes: Number of RDMA queue pair opcodes supported 535 * @rdma.admin_opcodes: Number of RDMA admin opcodes supported 536 * @rdma.minor_version: RDMA capability minor version 537 * @rdma.npts_per_lif: Page table size per LIF 538 * @rdma.nmrs_per_lif: Number of memory regions per LIF 539 * @rdma.nahs_per_lif: Number of address handles per LIF 540 * @rdma.max_stride: Max work request stride 541 * @rdma.cl_stride: Cache line stride 542 * @rdma.pte_stride: Page table entry stride 543 * @rdma.rrq_stride: Remote RQ work request stride 544 * @rdma.rsq_stride: Remote SQ work request stride 545 * @rdma.dcqcn_profiles: Number of DCQCN profiles 546 * @rdma.udma_shift: Log2 number of queues per queue group 547 * @rdma.rsvd_dimensions: Reserved byte 548 * @rdma.page_size_cap: Supported page sizes 549 * @rdma.aq_qtype: RDMA Admin Qtype 550 * @rdma.sq_qtype: RDMA Send Qtype 551 * @rdma.rq_qtype: RDMA Receive Qtype 552 * @rdma.cq_qtype: RDMA Completion Qtype 553 * @rdma.eq_qtype: RDMA Event Qtype 554 * @rdma.stats_type: Supported statistics type 555 * (enum ionic_lif_rdma_cap_stats) 556 * @rdma.rsvd1: Reserved byte(s) 557 * @words: word access to struct contents 558 */ 559 union ionic_lif_identity { 560 struct { 561 __le64 capabilities; 562 563 struct { 564 u8 version; 565 u8 rsvd[3]; 566 __le32 max_ucast_filters; 567 __le32 max_mcast_filters; 568 __le16 rss_ind_tbl_sz; 569 __le32 min_frame_size; 570 __le32 max_frame_size; 571 u8 rsvd2[2]; 572 __le64 hwstamp_tx_modes; 573 __le64 hwstamp_rx_filters; 574 u8 rsvd3[88]; 575 union ionic_lif_config config; 576 } __packed eth; 577 578 struct { 579 u8 version; 580 u8 qp_opcodes; 581 u8 admin_opcodes; 582 u8 minor_version; 583 __le32 npts_per_lif; 584 __le32 nmrs_per_lif; 585 __le32 nahs_per_lif; 586 u8 max_stride; 587 u8 cl_stride; 588 u8 pte_stride; 589 u8 rrq_stride; 590 u8 rsq_stride; 591 u8 dcqcn_profiles; 592 u8 udma_shift; 593 u8 rsvd_dimensions; 594 __le64 page_size_cap; 595 struct ionic_lif_logical_qtype aq_qtype; 596 struct ionic_lif_logical_qtype sq_qtype; 597 struct ionic_lif_logical_qtype rq_qtype; 598 struct ionic_lif_logical_qtype cq_qtype; 599 struct ionic_lif_logical_qtype eq_qtype; 600 __le16 stats_type; 601 u8 rsvd1[162]; 602 } __packed rdma; 603 } __packed; 604 __le32 words[478]; 605 }; 606 607 /** 608 * struct ionic_lif_init_cmd - LIF init command 609 * @opcode: Opcode 610 * @type: LIF type (enum ionic_lif_type) 611 * @index: LIF index 612 * @rsvd: reserved byte(s) 613 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 614 * @rsvd2: reserved byte(s) 615 */ 616 struct ionic_lif_init_cmd { 617 u8 opcode; 618 u8 type; 619 __le16 index; 620 __le32 rsvd; 621 __le64 info_pa; 622 u8 rsvd2[48]; 623 }; 624 625 /** 626 * struct ionic_lif_init_comp - LIF init command completion 627 * @status: Status of the command (enum ionic_status_code) 628 * @rsvd: reserved byte(s) 629 * @hw_index: Hardware index of the initialized LIF 630 * @rsvd2: reserved byte(s) 631 */ 632 struct ionic_lif_init_comp { 633 u8 status; 634 u8 rsvd; 635 __le16 hw_index; 636 u8 rsvd2[12]; 637 }; 638 639 /** 640 * struct ionic_q_identify_cmd - queue identify command 641 * @opcode: opcode 642 * @rsvd: reserved byte(s) 643 * @lif_type: LIF type (enum ionic_lif_type) 644 * @type: Logical queue type (enum ionic_logical_qtype) 645 * @ver: Highest queue type version that the driver supports 646 * @rsvd2: reserved byte(s) 647 */ 648 struct ionic_q_identify_cmd { 649 u8 opcode; 650 u8 rsvd; 651 __le16 lif_type; 652 u8 type; 653 u8 ver; 654 u8 rsvd2[58]; 655 }; 656 657 /** 658 * struct ionic_q_identify_comp - queue identify command completion 659 * @status: Status of the command (enum ionic_status_code) 660 * @rsvd: reserved byte(s) 661 * @comp_index: Index in the descriptor ring for which this is the completion 662 * @ver: Queue type version that can be used with FW 663 * @rsvd2: reserved byte(s) 664 */ 665 struct ionic_q_identify_comp { 666 u8 status; 667 u8 rsvd; 668 __le16 comp_index; 669 u8 ver; 670 u8 rsvd2[11]; 671 }; 672 673 /** 674 * union ionic_q_identity - queue identity information 675 * @version: Queue type version that can be used with FW 676 * @supported: Bitfield of queue versions, first bit = ver 0 677 * @rsvd: reserved byte(s) 678 * @features: Queue features (enum ionic_q_feature, etc) 679 * @desc_sz: Descriptor size 680 * @comp_sz: Completion descriptor size 681 * @sg_desc_sz: Scatter/Gather descriptor size 682 * @max_sg_elems: Maximum number of Scatter/Gather elements 683 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 684 * @words: word access to struct contents 685 */ 686 union ionic_q_identity { 687 struct { 688 u8 version; 689 u8 supported; 690 u8 rsvd[6]; 691 __le64 features; 692 __le16 desc_sz; 693 __le16 comp_sz; 694 __le16 sg_desc_sz; 695 __le16 max_sg_elems; 696 __le16 sg_desc_stride; 697 }; 698 __le32 words[478]; 699 }; 700 701 /** 702 * struct ionic_q_init_cmd - Queue init command 703 * @opcode: opcode 704 * @rsvd: reserved byte(s) 705 * @type: Logical queue type 706 * @ver: Queue type version 707 * @rsvd1: reserved byte(s) 708 * @lif_index: LIF index 709 * @index: (LIF, qtype) relative admin queue index 710 * @intr_index: Interrupt control register index, or Event queue index 711 * @pid: Process ID 712 * @flags: 713 * IRQ: Interrupt requested on completion 714 * ENA: Enable the queue. If ENA=0 the queue is initialized 715 * but remains disabled, to be later enabled with the 716 * Queue Enable command. If ENA=1, then queue is 717 * initialized and then enabled. 718 * SG: Enable Scatter-Gather on the queue. 719 * in number of descs. The actual ring size is 720 * (1 << ring_size). For example, to 721 * select a ring size of 64 descriptors write 722 * ring_size = 6. The minimum ring_size value is 2 723 * for a ring size of 4 descriptors. The maximum 724 * ring_size value is 16 for a ring size of 64k 725 * descriptors. Values of ring_size <2 and >16 are 726 * reserved. 727 * EQ: Enable the Event Queue 728 * @cos: Class of service for this queue 729 * @ring_size: Queue ring size, encoded as a log2(size) 730 * @ring_base: Queue ring base address 731 * @cq_ring_base: Completion queue ring base address 732 * @sg_ring_base: Scatter/Gather ring base address 733 * @rsvd2: reserved byte(s) 734 * @features: Mask of queue features to enable, if not in the flags above. 735 */ 736 struct ionic_q_init_cmd { 737 u8 opcode; 738 u8 rsvd; 739 __le16 lif_index; 740 u8 type; 741 u8 ver; 742 u8 rsvd1[2]; 743 __le32 index; 744 __le16 pid; 745 __le16 intr_index; 746 __le16 flags; 747 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 748 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 749 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 750 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 751 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 752 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 753 u8 cos; 754 u8 ring_size; 755 __le64 ring_base; 756 __le64 cq_ring_base; 757 __le64 sg_ring_base; 758 u8 rsvd2[12]; 759 __le64 features; 760 } __packed; 761 762 /** 763 * struct ionic_q_init_comp - Queue init command completion 764 * @status: Status of the command (enum ionic_status_code) 765 * @rsvd: reserved byte(s) 766 * @comp_index: Index in the descriptor ring for which this is the completion 767 * @hw_index: Hardware Queue ID 768 * @hw_type: Hardware Queue type 769 * @rsvd2: reserved byte(s) 770 * @color: Color 771 */ 772 struct ionic_q_init_comp { 773 u8 status; 774 u8 rsvd; 775 __le16 comp_index; 776 __le32 hw_index; 777 u8 hw_type; 778 u8 rsvd2[6]; 779 u8 color; 780 }; 781 782 /* the device's internal addressing uses up to 52 bits */ 783 #define IONIC_ADDR_LEN 52 784 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 785 786 enum ionic_txq_desc_opcode { 787 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 788 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 789 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 790 IONIC_TXQ_DESC_OPCODE_TSO = 3, 791 }; 792 793 /** 794 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 795 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 796 * 797 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 798 * Non-offload send. No segmentation, 799 * fragmentation or checksum calc/insertion is 800 * performed by device; packet is prepared 801 * to send by software stack and requires 802 * no further manipulation from device. 803 * 804 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 805 * Offload 16-bit L4 checksum 806 * calculation/insertion. The device will 807 * calculate the L4 checksum value and 808 * insert the result in the packet's L4 809 * header checksum field. The L4 checksum 810 * is calculated starting at @csum_start bytes 811 * into the packet to the end of the packet. 812 * The checksum insertion position is given 813 * in @csum_offset, which is the offset from 814 * @csum_start to the checksum field in the L4 815 * header. This feature is only applicable to 816 * protocols such as TCP, UDP and ICMP where a 817 * standard (i.e. the 'IP-style' checksum) 818 * one's complement 16-bit checksum is used, 819 * using an IP pseudo-header to seed the 820 * calculation. Software will preload the L4 821 * checksum field with the IP pseudo-header 822 * checksum. 823 * 824 * For tunnel encapsulation, @csum_start and 825 * @csum_offset refer to the inner L4 826 * header. Supported tunnels encapsulations 827 * are: IPIP, GRE, and UDP. If the @encap 828 * is clear, no further processing by the 829 * device is required; software will 830 * calculate the outer header checksums. If 831 * the @encap is set, the device will 832 * offload the outer header checksums using 833 * LCO (local checksum offload) (see 834 * Documentation/networking/checksum-offloads.rst 835 * for more info). 836 * 837 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 838 * Offload 16-bit checksum computation to hardware. 839 * If @csum_l3 is set then the packet's L3 checksum is 840 * updated. Similarly, if @csum_l4 is set the L4 841 * checksum is updated. If @encap is set then encap header 842 * checksums are also updated. 843 * 844 * IONIC_TXQ_DESC_OPCODE_TSO: 845 * Device performs TCP segmentation offload 846 * (TSO). @hdr_len is the number of bytes 847 * to the end of TCP header (the offset to 848 * the TCP payload). @mss is the desired 849 * MSS, the TCP payload length for each 850 * segment. The device will calculate/ 851 * insert IP (IPv4 only) and TCP checksums 852 * for each segment. In the first data 853 * buffer containing the header template, 854 * the driver will set IPv4 checksum to 0 855 * and preload TCP checksum with the IP 856 * pseudo header calculated with IP length = 0. 857 * 858 * Supported tunnel encapsulations are IPIP, 859 * layer-3 GRE, and UDP. @hdr_len includes 860 * both outer and inner headers. The driver 861 * will set IPv4 checksum to zero and 862 * preload TCP checksum with IP pseudo 863 * header on the inner header. 864 * 865 * TCP ECN offload is supported. The device 866 * will set CWR flag in the first segment if 867 * CWR is set in the template header, and 868 * clear CWR in remaining segments. 869 * flags: 870 * vlan: 871 * Insert an L2 VLAN header using @vlan_tci 872 * encap: 873 * Calculate encap header checksum 874 * csum_l3: 875 * Compute L3 header checksum 876 * csum_l4: 877 * Compute L4 header checksum 878 * tso_sot: 879 * TSO start 880 * tso_eot: 881 * TSO end 882 * num_sg_elems: Number of scatter-gather elements in SG 883 * descriptor 884 * addr: First data buffer's DMA address 885 * (Subsequent data buffers are on txq_sg_desc) 886 * @len: First data buffer's length, in bytes 887 * @vlan_tci: VLAN tag to insert in the packet (if requested 888 * by @V-bit). Includes .1p and .1q tags 889 * @hword0: half word padding 890 * @hdr_len: Length of packet headers, including 891 * encapsulating outer header, if applicable 892 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 893 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 894 * all other modes. For 895 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 896 * of headers up to inner-most L4 header. For 897 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 898 * inner-most L4 payload, so inclusive of 899 * inner-most L4 header. 900 * @hword1: half word padding 901 * @mss: Desired MSS value for TSO; only applicable for 902 * IONIC_TXQ_DESC_OPCODE_TSO 903 * @csum_start: Offset from packet to first byte checked in L4 checksum 904 * @csum_offset: Offset from csum_start to L4 checksum field 905 * @hword2: half word padding 906 */ 907 struct ionic_txq_desc { 908 __le64 cmd; 909 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 910 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 911 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 912 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 913 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 914 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 915 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 916 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 917 918 /* common flags */ 919 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 920 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 921 922 /* flags for csum_hw opcode */ 923 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 924 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 925 926 /* flags for tso opcode */ 927 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 928 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 929 930 __le16 len; 931 union { 932 __le16 vlan_tci; 933 __le16 hword0; 934 }; 935 union { 936 __le16 csum_start; 937 __le16 hdr_len; 938 __le16 hword1; 939 }; 940 union { 941 __le16 csum_offset; 942 __le16 mss; 943 __le16 hword2; 944 }; 945 }; 946 947 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 948 u8 nsge, u64 addr) 949 { 950 u64 cmd; 951 952 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 953 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 954 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 955 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 956 957 return cmd; 958 }; 959 960 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 961 u8 *nsge, u64 *addr) 962 { 963 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 964 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 965 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 966 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 967 }; 968 969 /** 970 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 971 * @addr: DMA address of SG element data buffer 972 * @len: Length of SG element data buffer, in bytes 973 * @rsvd: reserved byte(s) 974 */ 975 struct ionic_txq_sg_elem { 976 __le64 addr; 977 __le16 len; 978 __le16 rsvd[3]; 979 }; 980 981 /** 982 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 983 * @elems: Scatter-gather elements 984 */ 985 struct ionic_txq_sg_desc { 986 #define IONIC_TX_MAX_SG_ELEMS 8 987 #define IONIC_TX_SG_DESC_STRIDE 8 988 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 989 }; 990 991 struct ionic_txq_sg_desc_v1 { 992 #define IONIC_TX_MAX_SG_ELEMS_V1 15 993 #define IONIC_TX_SG_DESC_STRIDE_V1 16 994 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 995 }; 996 997 /** 998 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 999 * @status: Status of the command (enum ionic_status_code) 1000 * @rsvd: reserved byte(s) 1001 * @comp_index: Index in the descriptor ring for which this is the completion 1002 * @rsvd2: reserved byte(s) 1003 * @color: Color bit 1004 */ 1005 struct ionic_txq_comp { 1006 u8 status; 1007 u8 rsvd; 1008 __le16 comp_index; 1009 u8 rsvd2[11]; 1010 u8 color; 1011 }; 1012 1013 enum ionic_rxq_desc_opcode { 1014 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 1015 IONIC_RXQ_DESC_OPCODE_SG = 1, 1016 }; 1017 1018 /** 1019 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 1020 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 1021 * 1022 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 1023 * Receive full packet into data buffer 1024 * starting at @addr. Results of 1025 * receive, including actual bytes received, 1026 * are recorded in Rx completion descriptor. 1027 * 1028 * @rsvd: reserved byte(s) 1029 * @len: Data buffer's length, in bytes 1030 * @addr: Data buffer's DMA address 1031 */ 1032 struct ionic_rxq_desc { 1033 u8 opcode; 1034 u8 rsvd[5]; 1035 __le16 len; 1036 __le64 addr; 1037 }; 1038 1039 /** 1040 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 1041 * @addr: DMA address of SG element data buffer 1042 * @len: Length of SG element data buffer, in bytes 1043 * @rsvd: reserved byte(s) 1044 */ 1045 struct ionic_rxq_sg_elem { 1046 __le64 addr; 1047 __le16 len; 1048 __le16 rsvd[3]; 1049 }; 1050 1051 /** 1052 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 1053 * @elems: Scatter-gather elements 1054 */ 1055 struct ionic_rxq_sg_desc { 1056 #define IONIC_RX_MAX_SG_ELEMS 8 1057 #define IONIC_RX_SG_DESC_STRIDE 8 1058 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 1059 }; 1060 1061 /** 1062 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 1063 * @status: Status of the command (enum ionic_status_code) 1064 * @num_sg_elems: Number of SG elements used by this descriptor 1065 * @comp_index: Index in the descriptor ring for which this is the completion 1066 * @rss_hash: 32-bit RSS hash 1067 * @csum: 16-bit sum of the packet's L2 payload 1068 * If the packet's L2 payload is odd length, an extra 1069 * zero-value byte is included in the @csum calculation but 1070 * not included in @len. 1071 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 1072 * set. Includes .1p and .1q tags. 1073 * @len: Received packet length, in bytes. Excludes FCS. 1074 * @csum_calc L2 payload checksum is computed or not 1075 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 1076 * 1077 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 1078 * The TCP checksum calculated by the device 1079 * matched the checksum in the receive packet's 1080 * TCP header. 1081 * 1082 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 1083 * The TCP checksum calculated by the device did 1084 * not match the checksum in the receive packet's 1085 * TCP header. 1086 * 1087 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 1088 * The UDP checksum calculated by the device 1089 * matched the checksum in the receive packet's 1090 * UDP header 1091 * 1092 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 1093 * The UDP checksum calculated by the device did 1094 * not match the checksum in the receive packet's 1095 * UDP header. 1096 * 1097 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 1098 * The IPv4 checksum calculated by the device 1099 * matched the checksum in the receive packet's 1100 * first IPv4 header. If the receive packet 1101 * contains both a tunnel IPv4 header and a 1102 * transport IPv4 header, the device validates the 1103 * checksum for both IPv4 headers. 1104 * 1105 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 1106 * The IPv4 checksum calculated by the device did 1107 * not match the checksum in the receive packet's 1108 * first IPv4 header. If the receive packet 1109 * contains both a tunnel IPv4 header and a 1110 * transport IPv4 header, the device validates the 1111 * checksum for both IP headers. 1112 * 1113 * IONIC_RXQ_COMP_CSUM_F_VLAN: 1114 * The VLAN header was stripped and placed in @vlan_tci. 1115 * 1116 * IONIC_RXQ_COMP_CSUM_F_CALC: 1117 * The checksum was calculated by the device. 1118 * 1119 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 1120 */ 1121 struct ionic_rxq_comp { 1122 u8 status; 1123 u8 num_sg_elems; 1124 __le16 comp_index; 1125 __le32 rss_hash; 1126 __le16 csum; 1127 __le16 vlan_tci; 1128 __le16 len; 1129 u8 csum_flags; 1130 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 1131 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 1132 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 1133 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 1134 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 1135 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 1136 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 1137 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 1138 u8 pkt_type_color; 1139 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 1140 }; 1141 1142 enum ionic_pkt_type { 1143 IONIC_PKT_TYPE_NON_IP = 0x00, 1144 IONIC_PKT_TYPE_IPV4 = 0x01, 1145 IONIC_PKT_TYPE_IPV4_TCP = 0x03, 1146 IONIC_PKT_TYPE_IPV4_UDP = 0x05, 1147 IONIC_PKT_TYPE_IPV6 = 0x08, 1148 IONIC_PKT_TYPE_IPV6_TCP = 0x18, 1149 IONIC_PKT_TYPE_IPV6_UDP = 0x28, 1150 /* below types are only used if encap offloads are enabled on lif */ 1151 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 1152 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 1153 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 1154 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 1155 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 1156 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 1157 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 1158 }; 1159 1160 enum ionic_eth_hw_features { 1161 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1162 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1163 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1164 IONIC_ETH_HW_RX_HASH = BIT(3), 1165 IONIC_ETH_HW_RX_CSUM = BIT(4), 1166 IONIC_ETH_HW_TX_SG = BIT(5), 1167 IONIC_ETH_HW_RX_SG = BIT(6), 1168 IONIC_ETH_HW_TX_CSUM = BIT(7), 1169 IONIC_ETH_HW_TSO = BIT(8), 1170 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1171 IONIC_ETH_HW_TSO_ECN = BIT(10), 1172 IONIC_ETH_HW_TSO_GRE = BIT(11), 1173 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1174 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1175 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1176 IONIC_ETH_HW_TSO_UDP = BIT(15), 1177 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1178 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 1179 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 1180 IONIC_ETH_HW_TSO_GENEVE = BIT(19), 1181 IONIC_ETH_HW_TIMESTAMP = BIT(20), 1182 }; 1183 1184 /** 1185 * enum ionic_pkt_class - Packet classification mask. 1186 * 1187 * Used with rx steering filter, packets indicated by the mask can be steered 1188 * toward a specific receive queue. 1189 * 1190 * @IONIC_PKT_CLS_NTP_ALL: All NTP packets. 1191 * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync 1192 * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request 1193 * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets 1194 * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync 1195 * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request 1196 * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets 1197 * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync 1198 * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request 1199 * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets 1200 * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync 1201 * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request 1202 * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets 1203 * @IONIC_PKT_CLS_PTP_SYNC: PTP sync 1204 * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request 1205 * @IONIC_PKT_CLS_PTP_ALL: PTP all packets 1206 */ 1207 enum ionic_pkt_class { 1208 IONIC_PKT_CLS_NTP_ALL = BIT(0), 1209 1210 IONIC_PKT_CLS_PTP1_SYNC = BIT(1), 1211 IONIC_PKT_CLS_PTP1_DREQ = BIT(2), 1212 IONIC_PKT_CLS_PTP1_ALL = BIT(3) | 1213 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ, 1214 1215 IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4), 1216 IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5), 1217 IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) | 1218 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ, 1219 1220 IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7), 1221 IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8), 1222 IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) | 1223 IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ, 1224 1225 IONIC_PKT_CLS_PTP2_SYNC = 1226 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC, 1227 IONIC_PKT_CLS_PTP2_DREQ = 1228 IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ, 1229 IONIC_PKT_CLS_PTP2_ALL = 1230 IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL, 1231 1232 IONIC_PKT_CLS_PTP_SYNC = 1233 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC, 1234 IONIC_PKT_CLS_PTP_DREQ = 1235 IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ, 1236 IONIC_PKT_CLS_PTP_ALL = 1237 IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL, 1238 }; 1239 1240 /** 1241 * struct ionic_q_control_cmd - Queue control command 1242 * @opcode: opcode 1243 * @type: Queue type 1244 * @lif_index: LIF index 1245 * @index: Queue index 1246 * @oper: Operation (enum ionic_q_control_oper) 1247 * @rsvd: reserved byte(s) 1248 */ 1249 struct ionic_q_control_cmd { 1250 u8 opcode; 1251 u8 type; 1252 __le16 lif_index; 1253 __le32 index; 1254 u8 oper; 1255 u8 rsvd[55]; 1256 }; 1257 1258 typedef struct ionic_admin_comp ionic_q_control_comp; 1259 1260 enum ionic_q_control_oper { 1261 IONIC_Q_DISABLE = 0, 1262 IONIC_Q_ENABLE = 1, 1263 IONIC_Q_HANG_RESET = 2, 1264 }; 1265 1266 /** 1267 * enum ionic_phy_type - Physical connection type 1268 * @IONIC_PHY_TYPE_NONE: No PHY installed 1269 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1270 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1271 */ 1272 enum ionic_phy_type { 1273 IONIC_PHY_TYPE_NONE = 0, 1274 IONIC_PHY_TYPE_COPPER = 1, 1275 IONIC_PHY_TYPE_FIBER = 2, 1276 }; 1277 1278 /** 1279 * enum ionic_xcvr_state - Transceiver status 1280 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1281 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1282 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1283 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1284 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1285 */ 1286 enum ionic_xcvr_state { 1287 IONIC_XCVR_STATE_REMOVED = 0, 1288 IONIC_XCVR_STATE_INSERTED = 1, 1289 IONIC_XCVR_STATE_PENDING = 2, 1290 IONIC_XCVR_STATE_SPROM_READ = 3, 1291 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1292 }; 1293 1294 /* 1295 * enum ionic_xcvr_pid - Supported link modes 1296 */ 1297 enum ionic_xcvr_pid { 1298 IONIC_XCVR_PID_UNKNOWN = 0, 1299 1300 /* CU */ 1301 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1302 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1303 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1304 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1305 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1306 IONIC_XCVR_PID_QSFP_50G_CR2_FC = 6, 1307 IONIC_XCVR_PID_QSFP_50G_CR2 = 7, 1308 IONIC_XCVR_PID_QSFP_200G_CR4 = 8, 1309 IONIC_XCVR_PID_QSFP_400G_CR4 = 9, 1310 /* Fiber */ 1311 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1312 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1313 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1314 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1315 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1316 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1317 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1318 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1319 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1320 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1321 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1322 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1323 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1324 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1325 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1326 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1327 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1328 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1329 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1330 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1331 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1332 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1333 IONIC_XCVR_PID_SFP_10GBASE_T = 72, 1334 IONIC_XCVR_PID_SFP_1000BASE_T = 73, 1335 IONIC_XCVR_PID_QSFP_200G_AOC = 74, 1336 IONIC_XCVR_PID_QSFP_200G_FR4 = 75, 1337 IONIC_XCVR_PID_QSFP_200G_DR4 = 76, 1338 IONIC_XCVR_PID_QSFP_200G_SR4 = 77, 1339 IONIC_XCVR_PID_QSFP_200G_ACC = 78, 1340 IONIC_XCVR_PID_QSFP_400G_FR4 = 79, 1341 IONIC_XCVR_PID_QSFP_400G_DR4 = 80, 1342 IONIC_XCVR_PID_QSFP_400G_SR4 = 81, 1343 IONIC_XCVR_PID_QSFP_400G_VR4 = 82, 1344 IONIC_XCVR_PID_QSFP_400G_AOC = 83, 1345 IONIC_XCVR_PID_QSFP_400G_AEC = 84, 1346 IONIC_XCVR_PID_QSFP_200G_AEC = 85, 1347 IONIC_XCVR_PID_QSFP_400G_LPO = 86, 1348 IONIC_XCVR_PID_QSFP_100G_FR4 = 87, 1349 IONIC_XCVR_PID_QSFP_100G_DR4 = 88, 1350 }; 1351 1352 /** 1353 * enum ionic_port_type - Port types 1354 * @IONIC_PORT_TYPE_NONE: Port type not configured 1355 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1356 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1357 */ 1358 enum ionic_port_type { 1359 IONIC_PORT_TYPE_NONE = 0, 1360 IONIC_PORT_TYPE_ETH = 1, 1361 IONIC_PORT_TYPE_MGMT = 2, 1362 }; 1363 1364 /** 1365 * enum ionic_port_admin_state - Port config state 1366 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1367 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1368 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1369 */ 1370 enum ionic_port_admin_state { 1371 IONIC_PORT_ADMIN_STATE_NONE = 0, 1372 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1373 IONIC_PORT_ADMIN_STATE_UP = 2, 1374 }; 1375 1376 /** 1377 * enum ionic_port_oper_status - Port operational status 1378 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1379 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1380 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1381 */ 1382 enum ionic_port_oper_status { 1383 IONIC_PORT_OPER_STATUS_NONE = 0, 1384 IONIC_PORT_OPER_STATUS_UP = 1, 1385 IONIC_PORT_OPER_STATUS_DOWN = 2, 1386 }; 1387 1388 /** 1389 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1390 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1391 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1392 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1393 */ 1394 enum ionic_port_fec_type { 1395 IONIC_PORT_FEC_TYPE_NONE = 0, 1396 IONIC_PORT_FEC_TYPE_FC = 1, 1397 IONIC_PORT_FEC_TYPE_RS = 2, 1398 }; 1399 1400 /** 1401 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1402 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1403 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1404 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1405 */ 1406 enum ionic_port_pause_type { 1407 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1408 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1409 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1410 }; 1411 1412 /** 1413 * enum ionic_port_loopback_mode - Loopback modes 1414 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1415 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1416 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1417 */ 1418 enum ionic_port_loopback_mode { 1419 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1420 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1421 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1422 }; 1423 1424 /** 1425 * struct ionic_xcvr_status - Transceiver Status information 1426 * @state: Transceiver status (enum ionic_xcvr_state) 1427 * @phy: Physical connection type (enum ionic_phy_type) 1428 * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1429 * @sprom: Transceiver sprom contents 1430 */ 1431 struct ionic_xcvr_status { 1432 u8 state; 1433 u8 phy; 1434 __le16 pid; 1435 u8 sprom[256]; 1436 }; 1437 1438 /** 1439 * union ionic_port_config - Port configuration 1440 * @speed: port speed (in Mbps) 1441 * @mtu: mtu 1442 * @state: port admin state (enum ionic_port_admin_state) 1443 * @an_enable: autoneg enable 1444 * @fec_type: fec type (enum ionic_port_fec_type) 1445 * @pause_type: pause type (enum ionic_port_pause_type) 1446 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1447 * @words: word access to struct contents 1448 */ 1449 union ionic_port_config { 1450 struct { 1451 #define IONIC_SPEED_400G 400000 /* 400G in Mbps */ 1452 #define IONIC_SPEED_200G 200000 /* 200G in Mbps */ 1453 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1454 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1455 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1456 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1457 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1458 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1459 __le32 speed; 1460 __le32 mtu; 1461 u8 state; 1462 u8 an_enable; 1463 u8 fec_type; 1464 #define IONIC_PAUSE_TYPE_MASK 0x0f 1465 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1466 #define IONIC_PAUSE_F_TX 0x10 1467 #define IONIC_PAUSE_F_RX 0x20 1468 u8 pause_type; 1469 u8 loopback_mode; 1470 }; 1471 __le32 words[64]; 1472 }; 1473 1474 /** 1475 * struct ionic_port_status - Port Status information 1476 * @status: link status (enum ionic_port_oper_status) 1477 * @id: port id 1478 * @speed: link speed (in Mbps) 1479 * @link_down_count: number of times link went from up to down 1480 * @fec_type: fec type (enum ionic_port_fec_type) 1481 * @rsvd: reserved byte(s) 1482 * @xcvr: transceiver status 1483 */ 1484 struct ionic_port_status { 1485 __le32 id; 1486 __le32 speed; 1487 u8 status; 1488 __le16 link_down_count; 1489 u8 fec_type; 1490 u8 rsvd[48]; 1491 struct ionic_xcvr_status xcvr; 1492 } __packed; 1493 1494 /** 1495 * struct ionic_port_identify_cmd - Port identify command 1496 * @opcode: opcode 1497 * @index: port index 1498 * @ver: Highest version of identify supported by driver 1499 * @rsvd: reserved byte(s) 1500 */ 1501 struct ionic_port_identify_cmd { 1502 u8 opcode; 1503 u8 index; 1504 u8 ver; 1505 u8 rsvd[61]; 1506 }; 1507 1508 /** 1509 * struct ionic_port_identify_comp - Port identify command completion 1510 * @status: Status of the command (enum ionic_status_code) 1511 * @ver: Version of identify returned by device 1512 * @rsvd: reserved byte(s) 1513 */ 1514 struct ionic_port_identify_comp { 1515 u8 status; 1516 u8 ver; 1517 u8 rsvd[14]; 1518 }; 1519 1520 /** 1521 * struct ionic_port_init_cmd - Port initialization command 1522 * @opcode: opcode 1523 * @index: port index 1524 * @rsvd: reserved byte(s) 1525 * @info_pa: destination address for port info (struct ionic_port_info) 1526 * @rsvd2: reserved byte(s) 1527 */ 1528 struct ionic_port_init_cmd { 1529 u8 opcode; 1530 u8 index; 1531 u8 rsvd[6]; 1532 __le64 info_pa; 1533 u8 rsvd2[48]; 1534 }; 1535 1536 /** 1537 * struct ionic_port_init_comp - Port initialization command completion 1538 * @status: Status of the command (enum ionic_status_code) 1539 * @rsvd: reserved byte(s) 1540 */ 1541 struct ionic_port_init_comp { 1542 u8 status; 1543 u8 rsvd[15]; 1544 }; 1545 1546 /** 1547 * struct ionic_port_reset_cmd - Port reset command 1548 * @opcode: opcode 1549 * @index: port index 1550 * @rsvd: reserved byte(s) 1551 */ 1552 struct ionic_port_reset_cmd { 1553 u8 opcode; 1554 u8 index; 1555 u8 rsvd[62]; 1556 }; 1557 1558 /** 1559 * struct ionic_port_reset_comp - Port reset command completion 1560 * @status: Status of the command (enum ionic_status_code) 1561 * @rsvd: reserved byte(s) 1562 */ 1563 struct ionic_port_reset_comp { 1564 u8 status; 1565 u8 rsvd[15]; 1566 }; 1567 1568 /** 1569 * enum ionic_stats_ctl_cmd - List of commands for stats control 1570 * @IONIC_STATS_CTL_RESET: Reset statistics 1571 */ 1572 enum ionic_stats_ctl_cmd { 1573 IONIC_STATS_CTL_RESET = 0, 1574 }; 1575 1576 /** 1577 * enum ionic_txstamp_mode - List of TX Timestamping Modes 1578 * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping. 1579 * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping. 1580 * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets. 1581 * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp. 1582 */ 1583 enum ionic_txstamp_mode { 1584 IONIC_TXSTAMP_OFF = 0, 1585 IONIC_TXSTAMP_ON = 1, 1586 IONIC_TXSTAMP_ONESTEP_SYNC = 2, 1587 IONIC_TXSTAMP_ONESTEP_P2P = 3, 1588 }; 1589 1590 /** 1591 * enum ionic_port_attr - List of device attributes 1592 * @IONIC_PORT_ATTR_STATE: Port state attribute 1593 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1594 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1595 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute 1596 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1597 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1598 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1599 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1600 */ 1601 enum ionic_port_attr { 1602 IONIC_PORT_ATTR_STATE = 0, 1603 IONIC_PORT_ATTR_SPEED = 1, 1604 IONIC_PORT_ATTR_MTU = 2, 1605 IONIC_PORT_ATTR_AUTONEG = 3, 1606 IONIC_PORT_ATTR_FEC = 4, 1607 IONIC_PORT_ATTR_PAUSE = 5, 1608 IONIC_PORT_ATTR_LOOPBACK = 6, 1609 IONIC_PORT_ATTR_STATS_CTRL = 7, 1610 }; 1611 1612 /** 1613 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1614 * @opcode: Opcode 1615 * @index: Port index 1616 * @attr: Attribute type (enum ionic_port_attr) 1617 * @rsvd: reserved byte(s) 1618 * @state: Port state 1619 * @speed: Port speed 1620 * @mtu: Port MTU 1621 * @an_enable: Port autonegotiation setting 1622 * @fec_type: Port FEC type setting 1623 * @pause_type: Port pause type setting 1624 * @loopback_mode: Port loopback mode 1625 * @stats_ctl: Port stats setting 1626 * @rsvd2: reserved byte(s) 1627 */ 1628 struct ionic_port_setattr_cmd { 1629 u8 opcode; 1630 u8 index; 1631 u8 attr; 1632 u8 rsvd; 1633 union { 1634 u8 state; 1635 __le32 speed; 1636 __le32 mtu; 1637 u8 an_enable; 1638 u8 fec_type; 1639 u8 pause_type; 1640 u8 loopback_mode; 1641 u8 stats_ctl; 1642 u8 rsvd2[60]; 1643 }; 1644 }; 1645 1646 /** 1647 * struct ionic_port_setattr_comp - Port set attr command completion 1648 * @status: Status of the command (enum ionic_status_code) 1649 * @rsvd: reserved byte(s) 1650 * @color: Color bit 1651 */ 1652 struct ionic_port_setattr_comp { 1653 u8 status; 1654 u8 rsvd[14]; 1655 u8 color; 1656 }; 1657 1658 /** 1659 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1660 * @opcode: Opcode 1661 * @index: port index 1662 * @attr: Attribute type (enum ionic_port_attr) 1663 * @rsvd: reserved byte(s) 1664 */ 1665 struct ionic_port_getattr_cmd { 1666 u8 opcode; 1667 u8 index; 1668 u8 attr; 1669 u8 rsvd[61]; 1670 }; 1671 1672 /** 1673 * struct ionic_port_getattr_comp - Port get attr command completion 1674 * @status: Status of the command (enum ionic_status_code) 1675 * @rsvd: reserved byte(s) 1676 * @state: Port state 1677 * @speed: Port speed 1678 * @mtu: Port MTU 1679 * @an_enable: Port autonegotiation setting 1680 * @fec_type: Port FEC type setting 1681 * @pause_type: Port pause type setting 1682 * @loopback_mode: Port loopback mode 1683 * @rsvd2: reserved byte(s) 1684 * @color: Color bit 1685 */ 1686 struct ionic_port_getattr_comp { 1687 u8 status; 1688 u8 rsvd[3]; 1689 union { 1690 u8 state; 1691 __le32 speed; 1692 __le32 mtu; 1693 u8 an_enable; 1694 u8 fec_type; 1695 u8 pause_type; 1696 u8 loopback_mode; 1697 u8 rsvd2[11]; 1698 } __packed; 1699 u8 color; 1700 }; 1701 1702 /** 1703 * struct ionic_lif_status - LIF status register 1704 * @eid: most recent NotifyQ event id 1705 * @port_num: port the LIF is connected to 1706 * @rsvd: reserved byte(s) 1707 * @link_status: port status (enum ionic_port_oper_status) 1708 * @link_speed: speed of link in Mbps 1709 * @link_down_count: number of times link went from up to down 1710 * @rsvd2: reserved byte(s) 1711 */ 1712 struct ionic_lif_status { 1713 __le64 eid; 1714 u8 port_num; 1715 u8 rsvd; 1716 __le16 link_status; 1717 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1718 __le16 link_down_count; 1719 u8 rsvd2[46]; 1720 }; 1721 1722 /** 1723 * struct ionic_lif_reset_cmd - LIF reset command 1724 * @opcode: opcode 1725 * @rsvd: reserved byte(s) 1726 * @index: LIF index 1727 * @rsvd2: reserved byte(s) 1728 */ 1729 struct ionic_lif_reset_cmd { 1730 u8 opcode; 1731 u8 rsvd; 1732 __le16 index; 1733 __le32 rsvd2[15]; 1734 }; 1735 1736 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1737 1738 enum ionic_dev_state { 1739 IONIC_DEV_DISABLE = 0, 1740 IONIC_DEV_ENABLE = 1, 1741 IONIC_DEV_HANG_RESET = 2, 1742 }; 1743 1744 /** 1745 * enum ionic_dev_attr - List of device attributes 1746 * @IONIC_DEV_ATTR_STATE: Device state attribute 1747 * @IONIC_DEV_ATTR_NAME: Device name attribute 1748 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1749 */ 1750 enum ionic_dev_attr { 1751 IONIC_DEV_ATTR_STATE = 0, 1752 IONIC_DEV_ATTR_NAME = 1, 1753 IONIC_DEV_ATTR_FEATURES = 2, 1754 }; 1755 1756 /** 1757 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1758 * @opcode: Opcode 1759 * @attr: Attribute type (enum ionic_dev_attr) 1760 * @rsvd: reserved byte(s) 1761 * @state: Device state (enum ionic_dev_state) 1762 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1763 * @features: Device features 1764 * @rsvd2: reserved byte(s) 1765 */ 1766 struct ionic_dev_setattr_cmd { 1767 u8 opcode; 1768 u8 attr; 1769 __le16 rsvd; 1770 union { 1771 u8 state; 1772 char name[IONIC_IFNAMSIZ]; 1773 __le64 features; 1774 u8 rsvd2[60]; 1775 } __packed; 1776 }; 1777 1778 /** 1779 * struct ionic_dev_setattr_comp - Device set attr command completion 1780 * @status: Status of the command (enum ionic_status_code) 1781 * @rsvd: reserved byte(s) 1782 * @features: Device features 1783 * @rsvd2: reserved byte(s) 1784 * @color: Color bit 1785 */ 1786 struct ionic_dev_setattr_comp { 1787 u8 status; 1788 u8 rsvd[3]; 1789 union { 1790 __le64 features; 1791 u8 rsvd2[11]; 1792 } __packed; 1793 u8 color; 1794 }; 1795 1796 /** 1797 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1798 * @opcode: opcode 1799 * @attr: Attribute type (enum ionic_dev_attr) 1800 * @rsvd: reserved byte(s) 1801 */ 1802 struct ionic_dev_getattr_cmd { 1803 u8 opcode; 1804 u8 attr; 1805 u8 rsvd[62]; 1806 }; 1807 1808 /** 1809 * struct ionic_dev_getattr_comp - Device set attr command completion 1810 * @status: Status of the command (enum ionic_status_code) 1811 * @rsvd: reserved byte(s) 1812 * @features: Device features 1813 * @rsvd2: reserved byte(s) 1814 * @color: Color bit 1815 */ 1816 struct ionic_dev_getattr_comp { 1817 u8 status; 1818 u8 rsvd[3]; 1819 union { 1820 __le64 features; 1821 u8 rsvd2[11]; 1822 } __packed; 1823 u8 color; 1824 }; 1825 1826 /* 1827 * RSS parameters 1828 */ 1829 #define IONIC_RSS_HASH_KEY_SIZE 40 1830 1831 enum ionic_rss_hash_types { 1832 IONIC_RSS_TYPE_IPV4 = BIT(0), 1833 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1834 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1835 IONIC_RSS_TYPE_IPV6 = BIT(3), 1836 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1837 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1838 }; 1839 1840 /** 1841 * enum ionic_lif_attr - List of LIF attributes 1842 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1843 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1844 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1845 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1846 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1847 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1848 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1849 * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode 1850 * @IONIC_LIF_ATTR_MAX: maximum attribute value 1851 */ 1852 enum ionic_lif_attr { 1853 IONIC_LIF_ATTR_STATE = 0, 1854 IONIC_LIF_ATTR_NAME = 1, 1855 IONIC_LIF_ATTR_MTU = 2, 1856 IONIC_LIF_ATTR_MAC = 3, 1857 IONIC_LIF_ATTR_FEATURES = 4, 1858 IONIC_LIF_ATTR_RSS = 5, 1859 IONIC_LIF_ATTR_STATS_CTRL = 6, 1860 IONIC_LIF_ATTR_TXSTAMP = 7, 1861 IONIC_LIF_ATTR_MAX = 255, 1862 }; 1863 1864 /** 1865 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1866 * @opcode: Opcode 1867 * @attr: Attribute type (enum ionic_lif_attr) 1868 * @index: LIF index 1869 * @state: LIF state (enum ionic_lif_state) 1870 * @name: The netdev name string, 0 terminated 1871 * @mtu: Mtu 1872 * @mac: Station mac 1873 * @features: Features (enum ionic_eth_hw_features) 1874 * @rss: RSS properties 1875 * @rss.types: The hash types to enable (see rss_hash_types) 1876 * @rss.key: The hash secret key 1877 * @rss.rsvd: reserved byte(s) 1878 * @rss.addr: Address for the indirection table shared memory 1879 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1880 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1881 * @rsvd: reserved byte(s) 1882 */ 1883 struct ionic_lif_setattr_cmd { 1884 u8 opcode; 1885 u8 attr; 1886 __le16 index; 1887 union { 1888 u8 state; 1889 char name[IONIC_IFNAMSIZ]; 1890 __le32 mtu; 1891 u8 mac[6]; 1892 __le64 features; 1893 struct { 1894 __le16 types; 1895 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1896 u8 rsvd[6]; 1897 __le64 addr; 1898 } rss; 1899 u8 stats_ctl; 1900 __le16 txstamp_mode; 1901 u8 rsvd[60]; 1902 } __packed; 1903 }; 1904 1905 /** 1906 * struct ionic_lif_setattr_comp - LIF set attr command completion 1907 * @status: Status of the command (enum ionic_status_code) 1908 * @rsvd: reserved byte(s) 1909 * @comp_index: Index in the descriptor ring for which this is the completion 1910 * @features: features (enum ionic_eth_hw_features) 1911 * @rsvd2: reserved byte(s) 1912 * @color: Color bit 1913 */ 1914 struct ionic_lif_setattr_comp { 1915 u8 status; 1916 u8 rsvd; 1917 __le16 comp_index; 1918 union { 1919 __le64 features; 1920 u8 rsvd2[11]; 1921 } __packed; 1922 u8 color; 1923 }; 1924 1925 /** 1926 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1927 * @opcode: Opcode 1928 * @attr: Attribute type (enum ionic_lif_attr) 1929 * @index: LIF index 1930 * @rsvd: reserved byte(s) 1931 */ 1932 struct ionic_lif_getattr_cmd { 1933 u8 opcode; 1934 u8 attr; 1935 __le16 index; 1936 u8 rsvd[60]; 1937 }; 1938 1939 /** 1940 * struct ionic_lif_getattr_comp - LIF get attr command completion 1941 * @status: Status of the command (enum ionic_status_code) 1942 * @rsvd: reserved byte(s) 1943 * @comp_index: Index in the descriptor ring for which this is the completion 1944 * @state: LIF state (enum ionic_lif_state) 1945 * @mtu: Mtu 1946 * @mac: Station mac 1947 * @features: Features (enum ionic_eth_hw_features) 1948 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1949 * @rsvd2: reserved byte(s) 1950 * @color: Color bit 1951 */ 1952 struct ionic_lif_getattr_comp { 1953 u8 status; 1954 u8 rsvd; 1955 __le16 comp_index; 1956 union { 1957 u8 state; 1958 __le32 mtu; 1959 u8 mac[6]; 1960 __le64 features; 1961 __le16 txstamp_mode; 1962 u8 rsvd2[11]; 1963 } __packed; 1964 u8 color; 1965 }; 1966 1967 /** 1968 * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock 1969 * @opcode: Opcode 1970 * @rsvd1: reserved byte(s) 1971 * @lif_index: LIF index 1972 * @rsvd2: reserved byte(s) 1973 * @tick: Hardware stamp tick of an instant in time. 1974 * @nsec: Nanosecond stamp of the same instant. 1975 * @frac: Fractional nanoseconds at the same instant. 1976 * @mult: Cycle to nanosecond multiplier. 1977 * @shift: Cycle to nanosecond divisor (power of two). 1978 * @rsvd3: reserved byte(s) 1979 */ 1980 struct ionic_lif_setphc_cmd { 1981 u8 opcode; 1982 u8 rsvd1; 1983 __le16 lif_index; 1984 u8 rsvd2[4]; 1985 __le64 tick; 1986 __le64 nsec; 1987 __le64 frac; 1988 __le32 mult; 1989 __le32 shift; 1990 u8 rsvd3[24]; 1991 }; 1992 1993 enum ionic_rx_mode { 1994 IONIC_RX_MODE_F_UNICAST = BIT(0), 1995 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1996 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1997 IONIC_RX_MODE_F_PROMISC = BIT(3), 1998 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1999 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 2000 }; 2001 2002 /** 2003 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 2004 * @opcode: opcode 2005 * @rsvd: reserved byte(s) 2006 * @lif_index: LIF index 2007 * @rx_mode: Rx mode flags: 2008 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 2009 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 2010 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 2011 * IONIC_RX_MODE_F_PROMISC: Accept any packets 2012 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 2013 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 2014 * @rsvd2: reserved byte(s) 2015 */ 2016 struct ionic_rx_mode_set_cmd { 2017 u8 opcode; 2018 u8 rsvd; 2019 __le16 lif_index; 2020 __le16 rx_mode; 2021 __le16 rsvd2[29]; 2022 }; 2023 2024 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 2025 2026 enum ionic_rx_filter_match_type { 2027 IONIC_RX_FILTER_MATCH_VLAN = 0x0, 2028 IONIC_RX_FILTER_MATCH_MAC = 0x1, 2029 IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2, 2030 IONIC_RX_FILTER_STEER_PKTCLASS = 0x10, 2031 }; 2032 2033 /** 2034 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 2035 * @opcode: opcode 2036 * @qtype: Queue type 2037 * @lif_index: LIF index 2038 * @qid: Queue ID 2039 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 2040 * @vlan: VLAN filter 2041 * @vlan.vlan: VLAN ID 2042 * @mac: MAC filter 2043 * @mac.addr: MAC address (network-byte order) 2044 * @mac_vlan: MACVLAN filter 2045 * @mac_vlan.vlan: VLAN ID 2046 * @mac_vlan.addr: MAC address (network-byte order) 2047 * @pkt_class: Packet classification filter 2048 * @rsvd: reserved byte(s) 2049 */ 2050 struct ionic_rx_filter_add_cmd { 2051 u8 opcode; 2052 u8 qtype; 2053 __le16 lif_index; 2054 __le32 qid; 2055 __le16 match; 2056 union { 2057 struct { 2058 __le16 vlan; 2059 } vlan; 2060 struct { 2061 u8 addr[6]; 2062 } mac; 2063 struct { 2064 __le16 vlan; 2065 u8 addr[6]; 2066 } mac_vlan; 2067 __le64 pkt_class; 2068 u8 rsvd[54]; 2069 } __packed; 2070 }; 2071 2072 /** 2073 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 2074 * @status: Status of the command (enum ionic_status_code) 2075 * @rsvd: reserved byte(s) 2076 * @comp_index: Index in the descriptor ring for which this is the completion 2077 * @filter_id: Filter ID 2078 * @rsvd2: reserved byte(s) 2079 * @color: Color bit 2080 */ 2081 struct ionic_rx_filter_add_comp { 2082 u8 status; 2083 u8 rsvd; 2084 __le16 comp_index; 2085 __le32 filter_id; 2086 u8 rsvd2[7]; 2087 u8 color; 2088 }; 2089 2090 /** 2091 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 2092 * @opcode: opcode 2093 * @rsvd: reserved byte(s) 2094 * @lif_index: LIF index 2095 * @filter_id: Filter ID 2096 * @rsvd2: reserved byte(s) 2097 */ 2098 struct ionic_rx_filter_del_cmd { 2099 u8 opcode; 2100 u8 rsvd; 2101 __le16 lif_index; 2102 __le32 filter_id; 2103 u8 rsvd2[56]; 2104 }; 2105 2106 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 2107 2108 enum ionic_vf_attr { 2109 IONIC_VF_ATTR_SPOOFCHK = 1, 2110 IONIC_VF_ATTR_TRUST = 2, 2111 IONIC_VF_ATTR_MAC = 3, 2112 IONIC_VF_ATTR_LINKSTATE = 4, 2113 IONIC_VF_ATTR_VLAN = 5, 2114 IONIC_VF_ATTR_RATE = 6, 2115 IONIC_VF_ATTR_STATSADDR = 7, 2116 }; 2117 2118 /** 2119 * enum ionic_vf_link_status - Virtual Function link status 2120 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 2121 * @IONIC_VF_LINK_STATUS_UP: Link always up 2122 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 2123 */ 2124 enum ionic_vf_link_status { 2125 IONIC_VF_LINK_STATUS_AUTO = 0, 2126 IONIC_VF_LINK_STATUS_UP = 1, 2127 IONIC_VF_LINK_STATUS_DOWN = 2, 2128 }; 2129 2130 /** 2131 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 2132 * @opcode: Opcode 2133 * @attr: Attribute type (enum ionic_vf_attr) 2134 * @vf_index: VF index 2135 * @macaddr: mac address 2136 * @vlanid: vlan ID 2137 * @maxrate: max Tx rate in Mbps 2138 * @spoofchk: enable address spoof checking 2139 * @trust: enable VF trust 2140 * @linkstate: set link up or down 2141 * @stats_pa: set DMA address for VF stats 2142 * @pad: reserved byte(s) 2143 */ 2144 struct ionic_vf_setattr_cmd { 2145 u8 opcode; 2146 u8 attr; 2147 __le16 vf_index; 2148 union { 2149 u8 macaddr[6]; 2150 __le16 vlanid; 2151 __le32 maxrate; 2152 u8 spoofchk; 2153 u8 trust; 2154 u8 linkstate; 2155 __le64 stats_pa; 2156 u8 pad[60]; 2157 } __packed; 2158 }; 2159 2160 struct ionic_vf_setattr_comp { 2161 u8 status; 2162 u8 attr; 2163 __le16 vf_index; 2164 __le16 comp_index; 2165 u8 rsvd[9]; 2166 u8 color; 2167 }; 2168 2169 /** 2170 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 2171 * @opcode: Opcode 2172 * @attr: Attribute type (enum ionic_vf_attr) 2173 * @vf_index: VF index 2174 * @rsvd: reserved byte(s) 2175 */ 2176 struct ionic_vf_getattr_cmd { 2177 u8 opcode; 2178 u8 attr; 2179 __le16 vf_index; 2180 u8 rsvd[60]; 2181 }; 2182 2183 struct ionic_vf_getattr_comp { 2184 u8 status; 2185 u8 attr; 2186 __le16 vf_index; 2187 union { 2188 u8 macaddr[6]; 2189 __le16 vlanid; 2190 __le32 maxrate; 2191 u8 spoofchk; 2192 u8 trust; 2193 u8 linkstate; 2194 __le64 stats_pa; 2195 u8 pad[11]; 2196 } __packed; 2197 u8 color; 2198 }; 2199 2200 enum ionic_vf_ctrl_opcode { 2201 IONIC_VF_CTRL_START_ALL = 0, 2202 IONIC_VF_CTRL_START = 1, 2203 }; 2204 2205 /** 2206 * struct ionic_vf_ctrl_cmd - VF control command 2207 * @opcode: Opcode for the command 2208 * @ctrl_opcode: VF control operation type 2209 * @vf_index: VF Index. It is unused if op START_ALL is used. 2210 */ 2211 struct ionic_vf_ctrl_cmd { 2212 u8 opcode; 2213 u8 ctrl_opcode; 2214 __le16 vf_index; 2215 /* private: */ 2216 u8 rsvd1[60]; 2217 }; 2218 2219 /** 2220 * struct ionic_vf_ctrl_comp - VF_CTRL command completion. 2221 * @status: Status of the command (enum ionic_status_code) 2222 */ 2223 struct ionic_vf_ctrl_comp { 2224 u8 status; 2225 /* private: */ 2226 u8 rsvd[15]; 2227 }; 2228 2229 /** 2230 * struct ionic_discover_cmb_cmd - CMB discovery command 2231 * @opcode: Opcode for the command 2232 * @rsvd: Reserved bytes 2233 */ 2234 struct ionic_discover_cmb_cmd { 2235 u8 opcode; 2236 u8 rsvd[63]; 2237 }; 2238 2239 /** 2240 * struct ionic_discover_cmb_comp - CMB discover command completion. 2241 * @status: Status of the command (enum ionic_status_code) 2242 * @rsvd: Reserved bytes 2243 */ 2244 struct ionic_discover_cmb_comp { 2245 u8 status; 2246 u8 rsvd[15]; 2247 }; 2248 2249 #define IONIC_MAX_CMB_REGIONS 16 2250 #define IONIC_CMB_SHIFT_64K 16 2251 2252 enum ionic_cmb_type { 2253 IONIC_CMB_TYPE_DEVMEM = 0, 2254 IONIC_CMB_TYPE_EXPDB64 = 1, 2255 IONIC_CMB_TYPE_EXPDB128 = 2, 2256 IONIC_CMB_TYPE_EXPDB256 = 3, 2257 IONIC_CMB_TYPE_EXPDB512 = 4, 2258 }; 2259 2260 /** 2261 * union ionic_cmb_region - Configuration for CMB region 2262 * @bar_num: CMB mapping number from FW 2263 * @cmb_type: Type of CMB this region describes (enum ionic_cmb_type) 2264 * @rsvd: Reserved 2265 * @offset: Offset within BAR in 64KB pages 2266 * @length: Length of the CMB region 2267 * @words: 32-bit words for direct access to the entire region 2268 */ 2269 union ionic_cmb_region { 2270 struct { 2271 u8 bar_num; 2272 u8 cmb_type; 2273 u8 rsvd[6]; 2274 __le32 offset; 2275 __le32 length; 2276 } __packed; 2277 __le32 words[4]; 2278 }; 2279 2280 /** 2281 * union ionic_discover_cmb_identity - CMB layout identity structure 2282 * @num_regions: Number of CMB regions, up to 16 2283 * @flags: Feature and capability bits (0 for express 2284 * doorbell, 1 for 4K alignment indicator, 2285 * 31-24 for version information) 2286 * @region: CMB mappings region, entry 0 for regular 2287 * mapping, entries 1-7 for WQE sizes 64, 2288 * 128, 256, 512, 1024, 2048 and 4096 bytes 2289 * @words: Full union buffer size 2290 */ 2291 union ionic_discover_cmb_identity { 2292 struct { 2293 __le32 num_regions; 2294 #define IONIC_CMB_FLAG_EXPDB BIT(0) 2295 #define IONIC_CMB_FLAG_4KALIGN BIT(1) 2296 #define IONIC_CMB_FLAG_VERSION 0xff000000 2297 __le32 flags; 2298 union ionic_cmb_region region[IONIC_MAX_CMB_REGIONS]; 2299 }; 2300 __le32 words[478]; 2301 }; 2302 2303 /** 2304 * struct ionic_qos_identify_cmd - QoS identify command 2305 * @opcode: opcode 2306 * @ver: Highest version of identify supported by driver 2307 * @rsvd: reserved byte(s) 2308 */ 2309 struct ionic_qos_identify_cmd { 2310 u8 opcode; 2311 u8 ver; 2312 u8 rsvd[62]; 2313 }; 2314 2315 /** 2316 * struct ionic_qos_identify_comp - QoS identify command completion 2317 * @status: Status of the command (enum ionic_status_code) 2318 * @ver: Version of identify returned by device 2319 * @rsvd: reserved byte(s) 2320 */ 2321 struct ionic_qos_identify_comp { 2322 u8 status; 2323 u8 ver; 2324 u8 rsvd[14]; 2325 }; 2326 2327 #define IONIC_QOS_TC_MAX 8 2328 #define IONIC_QOS_ALL_TC 0xFF 2329 /* Capri max supported, should be renamed. */ 2330 #define IONIC_QOS_CLASS_MAX 7 2331 #define IONIC_QOS_PCP_MAX 8 2332 #define IONIC_QOS_CLASS_NAME_SZ 32 2333 #define IONIC_QOS_DSCP_MAX 64 2334 #define IONIC_QOS_ALL_PCP 0xFF 2335 #define IONIC_DSCP_BLOCK_SIZE 8 2336 2337 /* 2338 * enum ionic_qos_class 2339 */ 2340 enum ionic_qos_class { 2341 IONIC_QOS_CLASS_DEFAULT = 0, 2342 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 2343 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 2344 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 2345 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 2346 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 2347 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 2348 }; 2349 2350 /** 2351 * enum ionic_qos_class_type - Traffic classification criteria 2352 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 2353 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 2354 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 2355 */ 2356 enum ionic_qos_class_type { 2357 IONIC_QOS_CLASS_TYPE_NONE = 0, 2358 IONIC_QOS_CLASS_TYPE_PCP = 1, 2359 IONIC_QOS_CLASS_TYPE_DSCP = 2, 2360 }; 2361 2362 /** 2363 * enum ionic_qos_sched_type - QoS class scheduling type 2364 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 2365 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 2366 */ 2367 enum ionic_qos_sched_type { 2368 IONIC_QOS_SCHED_TYPE_STRICT = 0, 2369 IONIC_QOS_SCHED_TYPE_DWRR = 1, 2370 }; 2371 2372 /** 2373 * union ionic_qos_config - QoS configuration structure 2374 * @flags: Configuration flags 2375 * IONIC_QOS_CONFIG_F_ENABLE enable 2376 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 2377 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 2378 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 2379 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 2380 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 2381 * @class_type: QoS class type (enum ionic_qos_class_type) 2382 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 2383 * @name: QoS class name 2384 * @mtu: MTU of the class 2385 * @pfc_cos: Priority-Flow Control class of service 2386 * @dwrr_weight: QoS class scheduling weight 2387 * @strict_rlmt: Rate limit for strict priority scheduling 2388 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) 2389 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) 2390 * @dot1q_pcp: Dot1q pcp value 2391 * @ndscp: Number of valid dscp values in the ip_dscp field 2392 * @ip_dscp: IP dscp values 2393 * @words: word access to struct contents 2394 */ 2395 union ionic_qos_config { 2396 struct { 2397 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 2398 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 2399 /* Used to rewrite PCP or DSCP value. */ 2400 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 2401 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 2402 /* Non-disruptive TC update */ 2403 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 2404 u8 flags; 2405 u8 sched_type; 2406 u8 class_type; 2407 u8 pause_type; 2408 char name[IONIC_QOS_CLASS_NAME_SZ]; 2409 __le32 mtu; 2410 /* flow control */ 2411 u8 pfc_cos; 2412 /* scheduler */ 2413 union { 2414 u8 dwrr_weight; 2415 __le64 strict_rlmt; 2416 }; 2417 /* marking */ 2418 /* Used to rewrite PCP or DSCP value. */ 2419 union { 2420 u8 rw_dot1q_pcp; 2421 u8 rw_ip_dscp; 2422 }; 2423 /* classification */ 2424 union { 2425 u8 dot1q_pcp; 2426 struct { 2427 u8 ndscp; 2428 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 2429 }; 2430 }; 2431 }; 2432 __le32 words[64]; 2433 }; 2434 2435 /** 2436 * union ionic_qos_identity - QoS identity structure 2437 * @version: Version of the identify structure 2438 * @type: QoS system type 2439 * @rsvd: reserved byte(s) 2440 * @config: Current configuration of classes 2441 * @words: word access to struct contents 2442 */ 2443 union ionic_qos_identity { 2444 struct { 2445 u8 version; 2446 u8 type; 2447 u8 rsvd[62]; 2448 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2449 }; 2450 __le32 words[478]; 2451 }; 2452 2453 /** 2454 * struct ionic_qos_init_cmd - QoS config init command 2455 * @opcode: Opcode 2456 * @group: QoS class id 2457 * @rsvd: reserved byte(s) 2458 * @info_pa: destination address for qos info 2459 * @rsvd1: reserved byte(s) 2460 */ 2461 struct ionic_qos_init_cmd { 2462 u8 opcode; 2463 u8 group; 2464 u8 rsvd[6]; 2465 __le64 info_pa; 2466 u8 rsvd1[48]; 2467 }; 2468 2469 typedef struct ionic_admin_comp ionic_qos_init_comp; 2470 2471 /** 2472 * struct ionic_qos_reset_cmd - QoS config reset command 2473 * @opcode: Opcode 2474 * @group: QoS class id 2475 * @rsvd: reserved byte(s) 2476 */ 2477 struct ionic_qos_reset_cmd { 2478 u8 opcode; 2479 u8 group; 2480 u8 rsvd[62]; 2481 }; 2482 2483 /** 2484 * struct ionic_qos_clear_stats_cmd - Qos config reset command 2485 * @opcode: Opcode 2486 * @group_bitmap: bitmap of groups to be cleared 2487 * @rsvd: reserved byte(s) 2488 */ 2489 struct ionic_qos_clear_stats_cmd { 2490 u8 opcode; 2491 u8 group_bitmap; 2492 u8 rsvd[62]; 2493 }; 2494 2495 typedef struct ionic_admin_comp ionic_qos_reset_comp; 2496 2497 /** 2498 * struct ionic_fw_download_cmd - Firmware download command 2499 * @opcode: opcode 2500 * @rsvd: reserved byte(s) 2501 * @addr: dma address of the firmware buffer 2502 * @offset: offset of the firmware buffer within the full image 2503 * @length: number of valid bytes in the firmware buffer 2504 */ 2505 struct ionic_fw_download_cmd { 2506 u8 opcode; 2507 u8 rsvd[3]; 2508 __le32 offset; 2509 __le64 addr; 2510 __le32 length; 2511 }; 2512 2513 typedef struct ionic_admin_comp ionic_fw_download_comp; 2514 2515 /** 2516 * enum ionic_fw_control_oper - FW control operations 2517 * @IONIC_FW_RESET: Reset firmware 2518 * @IONIC_FW_INSTALL: Install firmware 2519 * @IONIC_FW_ACTIVATE: Activate firmware 2520 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously 2521 * @IONIC_FW_INSTALL_STATUS: Firmware installation status 2522 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously 2523 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status 2524 * @IONIC_FW_UPDATE_CLEANUP: Clean up after an interrupted fw update 2525 */ 2526 enum ionic_fw_control_oper { 2527 IONIC_FW_RESET = 0, 2528 IONIC_FW_INSTALL = 1, 2529 IONIC_FW_ACTIVATE = 2, 2530 IONIC_FW_INSTALL_ASYNC = 3, 2531 IONIC_FW_INSTALL_STATUS = 4, 2532 IONIC_FW_ACTIVATE_ASYNC = 5, 2533 IONIC_FW_ACTIVATE_STATUS = 6, 2534 IONIC_FW_UPDATE_CLEANUP = 7, 2535 }; 2536 2537 /** 2538 * struct ionic_fw_control_cmd - Firmware control command 2539 * @opcode: opcode 2540 * @rsvd: reserved byte(s) 2541 * @oper: firmware control operation (enum ionic_fw_control_oper) 2542 * @slot: slot to activate 2543 * @rsvd1: reserved byte(s) 2544 */ 2545 struct ionic_fw_control_cmd { 2546 u8 opcode; 2547 u8 rsvd[3]; 2548 u8 oper; 2549 u8 slot; 2550 u8 rsvd1[58]; 2551 }; 2552 2553 /** 2554 * struct ionic_fw_control_comp - Firmware control copletion 2555 * @status: Status of the command (enum ionic_status_code) 2556 * @rsvd: reserved byte(s) 2557 * @comp_index: Index in the descriptor ring for which this is the completion 2558 * @slot: Slot where the firmware was installed 2559 * @rsvd1: reserved byte(s) 2560 * @color: Color bit 2561 */ 2562 struct ionic_fw_control_comp { 2563 u8 status; 2564 u8 rsvd; 2565 __le16 comp_index; 2566 u8 slot; 2567 u8 rsvd1[10]; 2568 u8 color; 2569 }; 2570 2571 /****************************************************************** 2572 ******************* RDMA Commands ******************************** 2573 ******************************************************************/ 2574 2575 /** 2576 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2577 * @opcode: opcode 2578 * @rsvd: reserved byte(s) 2579 * @lif_index: LIF index 2580 * @rsvd2: reserved byte(s) 2581 * 2582 * There is no RDMA specific dev command completion struct. Completion uses 2583 * the common struct ionic_admin_comp. Only the status is indicated. 2584 * Nonzero status means the LIF does not support RDMA. 2585 **/ 2586 struct ionic_rdma_reset_cmd { 2587 u8 opcode; 2588 u8 rsvd; 2589 __le16 lif_index; 2590 u8 rsvd2[60]; 2591 }; 2592 2593 /** 2594 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2595 * @opcode: opcode, 52, 53 2596 * @rsvd: reserved byte(s) 2597 * @lif_index: LIF index 2598 * @qid_ver: (qid | (RDMA version << 24)) 2599 * @cid: intr, eq_id, or cq_id 2600 * @dbid: doorbell page id 2601 * @depth_log2: log base two of queue depth 2602 * @stride_log2: log base two of queue stride 2603 * @dma_addr: address of the queue memory 2604 * @rsvd2: reserved byte(s) 2605 * 2606 * The same command struct is used to create an RDMA event queue, completion 2607 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2608 * queue, an event queue id for a completion queue, or a completion queue id 2609 * for an RDMA admin queue. 2610 * 2611 * The queue created via a dev command must be contiguous in dma space. 2612 * 2613 * The dev commands are intended only to be used during driver initialization, 2614 * to create queues supporting the RDMA admin queue. Other queues, and other 2615 * types of RDMA resources like memory regions, will be created and registered 2616 * via the RDMA admin queue, and will support a more complete interface 2617 * providing scatter gather lists for larger, scattered queue buffers and 2618 * memory registration. 2619 * 2620 * There is no RDMA specific dev command completion struct. Completion uses 2621 * the common struct ionic_admin_comp. Only the status is indicated. 2622 **/ 2623 struct ionic_rdma_queue_cmd { 2624 u8 opcode; 2625 u8 rsvd; 2626 __le16 lif_index; 2627 __le32 qid_ver; 2628 __le32 cid; 2629 __le16 dbid; 2630 u8 depth_log2; 2631 u8 stride_log2; 2632 __le64 dma_addr; 2633 u8 rsvd2[40]; 2634 }; 2635 2636 /****************************************************************** 2637 ******************* Notify Events ******************************** 2638 ******************************************************************/ 2639 2640 /** 2641 * struct ionic_notifyq_event - Generic event reporting structure 2642 * @eid: event number 2643 * @ecode: event code 2644 * @data: unspecified data about the event 2645 * 2646 * This is the generic event report struct from which the other 2647 * actual events will be formed. 2648 */ 2649 struct ionic_notifyq_event { 2650 __le64 eid; 2651 __le16 ecode; 2652 u8 data[54]; 2653 }; 2654 2655 /** 2656 * struct ionic_link_change_event - Link change event notification 2657 * @eid: event number 2658 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2659 * @link_status: link up/down, with error bits (enum ionic_port_status) 2660 * @link_speed: speed of the network link 2661 * @rsvd: reserved byte(s) 2662 * 2663 * Sent when the network link state changes between UP and DOWN 2664 */ 2665 struct ionic_link_change_event { 2666 __le64 eid; 2667 __le16 ecode; 2668 __le16 link_status; 2669 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2670 u8 rsvd[48]; 2671 }; 2672 2673 /** 2674 * struct ionic_reset_event - Reset event notification 2675 * @eid: event number 2676 * @ecode: event code = IONIC_EVENT_RESET 2677 * @reset_code: reset type 2678 * @state: 0=pending, 1=complete, 2=error 2679 * @rsvd: reserved byte(s) 2680 * 2681 * Sent when the NIC or some subsystem is going to be or 2682 * has been reset. 2683 */ 2684 struct ionic_reset_event { 2685 __le64 eid; 2686 __le16 ecode; 2687 u8 reset_code; 2688 u8 state; 2689 u8 rsvd[52]; 2690 }; 2691 2692 /** 2693 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2694 * @eid: event number 2695 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2696 * @rsvd: reserved byte(s) 2697 */ 2698 struct ionic_heartbeat_event { 2699 __le64 eid; 2700 __le16 ecode; 2701 u8 rsvd[54]; 2702 }; 2703 2704 /** 2705 * struct ionic_log_event - Sent to notify the driver of an internal error 2706 * @eid: event number 2707 * @ecode: event code = IONIC_EVENT_LOG 2708 * @data: log data 2709 */ 2710 struct ionic_log_event { 2711 __le64 eid; 2712 __le16 ecode; 2713 u8 data[54]; 2714 }; 2715 2716 /** 2717 * struct ionic_xcvr_event - Transceiver change event 2718 * @eid: event number 2719 * @ecode: event code = IONIC_EVENT_XCVR 2720 * @rsvd: reserved byte(s) 2721 */ 2722 struct ionic_xcvr_event { 2723 __le64 eid; 2724 __le16 ecode; 2725 u8 rsvd[54]; 2726 }; 2727 2728 /* 2729 * struct ionic_port_stats - Port statistics structure 2730 */ 2731 struct ionic_port_stats { 2732 __le64 frames_rx_ok; 2733 __le64 frames_rx_all; 2734 __le64 frames_rx_bad_fcs; 2735 __le64 frames_rx_bad_all; 2736 __le64 octets_rx_ok; 2737 __le64 octets_rx_all; 2738 __le64 frames_rx_unicast; 2739 __le64 frames_rx_multicast; 2740 __le64 frames_rx_broadcast; 2741 __le64 frames_rx_pause; 2742 __le64 frames_rx_bad_length; 2743 __le64 frames_rx_undersized; 2744 __le64 frames_rx_oversized; 2745 __le64 frames_rx_fragments; 2746 __le64 frames_rx_jabber; 2747 __le64 frames_rx_pripause; 2748 __le64 frames_rx_stomped_crc; 2749 __le64 frames_rx_too_long; 2750 __le64 frames_rx_vlan_good; 2751 __le64 frames_rx_dropped; 2752 __le64 frames_rx_less_than_64b; 2753 __le64 frames_rx_64b; 2754 __le64 frames_rx_65b_127b; 2755 __le64 frames_rx_128b_255b; 2756 __le64 frames_rx_256b_511b; 2757 __le64 frames_rx_512b_1023b; 2758 __le64 frames_rx_1024b_1518b; 2759 __le64 frames_rx_1519b_2047b; 2760 __le64 frames_rx_2048b_4095b; 2761 __le64 frames_rx_4096b_8191b; 2762 __le64 frames_rx_8192b_9215b; 2763 __le64 frames_rx_other; 2764 __le64 frames_tx_ok; 2765 __le64 frames_tx_all; 2766 __le64 frames_tx_bad; 2767 __le64 octets_tx_ok; 2768 __le64 octets_tx_total; 2769 __le64 frames_tx_unicast; 2770 __le64 frames_tx_multicast; 2771 __le64 frames_tx_broadcast; 2772 __le64 frames_tx_pause; 2773 __le64 frames_tx_pripause; 2774 __le64 frames_tx_vlan; 2775 __le64 frames_tx_less_than_64b; 2776 __le64 frames_tx_64b; 2777 __le64 frames_tx_65b_127b; 2778 __le64 frames_tx_128b_255b; 2779 __le64 frames_tx_256b_511b; 2780 __le64 frames_tx_512b_1023b; 2781 __le64 frames_tx_1024b_1518b; 2782 __le64 frames_tx_1519b_2047b; 2783 __le64 frames_tx_2048b_4095b; 2784 __le64 frames_tx_4096b_8191b; 2785 __le64 frames_tx_8192b_9215b; 2786 __le64 frames_tx_other; 2787 __le64 frames_tx_pri_0; 2788 __le64 frames_tx_pri_1; 2789 __le64 frames_tx_pri_2; 2790 __le64 frames_tx_pri_3; 2791 __le64 frames_tx_pri_4; 2792 __le64 frames_tx_pri_5; 2793 __le64 frames_tx_pri_6; 2794 __le64 frames_tx_pri_7; 2795 __le64 frames_rx_pri_0; 2796 __le64 frames_rx_pri_1; 2797 __le64 frames_rx_pri_2; 2798 __le64 frames_rx_pri_3; 2799 __le64 frames_rx_pri_4; 2800 __le64 frames_rx_pri_5; 2801 __le64 frames_rx_pri_6; 2802 __le64 frames_rx_pri_7; 2803 __le64 tx_pripause_0_1us_count; 2804 __le64 tx_pripause_1_1us_count; 2805 __le64 tx_pripause_2_1us_count; 2806 __le64 tx_pripause_3_1us_count; 2807 __le64 tx_pripause_4_1us_count; 2808 __le64 tx_pripause_5_1us_count; 2809 __le64 tx_pripause_6_1us_count; 2810 __le64 tx_pripause_7_1us_count; 2811 __le64 rx_pripause_0_1us_count; 2812 __le64 rx_pripause_1_1us_count; 2813 __le64 rx_pripause_2_1us_count; 2814 __le64 rx_pripause_3_1us_count; 2815 __le64 rx_pripause_4_1us_count; 2816 __le64 rx_pripause_5_1us_count; 2817 __le64 rx_pripause_6_1us_count; 2818 __le64 rx_pripause_7_1us_count; 2819 __le64 rx_pause_1us_count; 2820 __le64 frames_tx_truncated; 2821 }; 2822 2823 struct ionic_mgmt_port_stats { 2824 __le64 frames_rx_ok; 2825 __le64 frames_rx_all; 2826 __le64 frames_rx_bad_fcs; 2827 __le64 frames_rx_bad_all; 2828 __le64 octets_rx_ok; 2829 __le64 octets_rx_all; 2830 __le64 frames_rx_unicast; 2831 __le64 frames_rx_multicast; 2832 __le64 frames_rx_broadcast; 2833 __le64 frames_rx_pause; 2834 __le64 frames_rx_bad_length; 2835 __le64 frames_rx_undersized; 2836 __le64 frames_rx_oversized; 2837 __le64 frames_rx_fragments; 2838 __le64 frames_rx_jabber; 2839 __le64 frames_rx_64b; 2840 __le64 frames_rx_65b_127b; 2841 __le64 frames_rx_128b_255b; 2842 __le64 frames_rx_256b_511b; 2843 __le64 frames_rx_512b_1023b; 2844 __le64 frames_rx_1024b_1518b; 2845 __le64 frames_rx_gt_1518b; 2846 __le64 frames_rx_fifo_full; 2847 __le64 frames_tx_ok; 2848 __le64 frames_tx_all; 2849 __le64 frames_tx_bad; 2850 __le64 octets_tx_ok; 2851 __le64 octets_tx_total; 2852 __le64 frames_tx_unicast; 2853 __le64 frames_tx_multicast; 2854 __le64 frames_tx_broadcast; 2855 __le64 frames_tx_pause; 2856 }; 2857 2858 enum ionic_pb_buffer_drop_stats { 2859 IONIC_BUFFER_INTRINSIC_DROP = 0, 2860 IONIC_BUFFER_DISCARDED, 2861 IONIC_BUFFER_ADMITTED, 2862 IONIC_BUFFER_OUT_OF_CELLS_DROP, 2863 IONIC_BUFFER_OUT_OF_CELLS_DROP_2, 2864 IONIC_BUFFER_OUT_OF_CREDIT_DROP, 2865 IONIC_BUFFER_TRUNCATION_DROP, 2866 IONIC_BUFFER_PORT_DISABLED_DROP, 2867 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, 2868 IONIC_BUFFER_SPAN_TAIL_DROP, 2869 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, 2870 IONIC_BUFFER_ENQUEUE_ERROR_DROP, 2871 IONIC_BUFFER_INVALID_PORT_DROP, 2872 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, 2873 IONIC_BUFFER_DROP_MAX, 2874 }; 2875 2876 enum ionic_oflow_drop_stats { 2877 IONIC_OFLOW_OCCUPANCY_DROP, 2878 IONIC_OFLOW_EMERGENCY_STOP_DROP, 2879 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP, 2880 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP, 2881 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP, 2882 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP, 2883 IONIC_OFLOW_DROP_MAX, 2884 }; 2885 2886 /* struct ionic_port_pb_stats - packet buffers system stats 2887 * uses ionic_pb_buffer_drop_stats for drop_counts[] 2888 */ 2889 struct ionic_port_pb_stats { 2890 __le64 sop_count_in; 2891 __le64 eop_count_in; 2892 __le64 sop_count_out; 2893 __le64 eop_count_out; 2894 __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; 2895 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2896 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; 2897 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; 2898 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX]; 2899 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX]; 2900 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX]; 2901 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX]; 2902 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX]; 2903 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX]; 2904 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX]; 2905 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2906 }; 2907 2908 /** 2909 * struct ionic_port_identity - port identity structure 2910 * @version: identity structure version 2911 * @type: type of port (enum ionic_port_type) 2912 * @num_lanes: number of lanes for the port 2913 * @autoneg: autoneg supported 2914 * @min_frame_size: minimum frame size supported 2915 * @max_frame_size: maximum frame size supported 2916 * @fec_type: supported fec types 2917 * @pause_type: supported pause types 2918 * @loopback_mode: supported loopback mode 2919 * @speeds: supported speeds 2920 * @rsvd2: reserved byte(s) 2921 * @config: current port configuration 2922 * @words: word access to struct contents 2923 */ 2924 union ionic_port_identity { 2925 struct { 2926 u8 version; 2927 u8 type; 2928 u8 num_lanes; 2929 u8 autoneg; 2930 __le32 min_frame_size; 2931 __le32 max_frame_size; 2932 u8 fec_type[4]; 2933 u8 pause_type[2]; 2934 u8 loopback_mode[2]; 2935 __le32 speeds[16]; 2936 u8 rsvd2[44]; 2937 union ionic_port_config config; 2938 }; 2939 __le32 words[478]; 2940 }; 2941 2942 /** 2943 * struct ionic_port_info - port info structure 2944 * @config: Port configuration data 2945 * @status: Port status data 2946 * @stats: Port statistics data 2947 * @mgmt_stats: Port management statistics data 2948 * @sprom_epage: Extended Transceiver sprom 2949 * @sprom_page1: Extended Transceiver sprom, page 1 2950 * @sprom_page2: Extended Transceiver sprom, page 2 2951 * @sprom_page17: Extended Transceiver sprom, page 17 2952 * @rsvd: reserved byte(s) 2953 * @pb_stats: uplink pb drop stats 2954 */ 2955 struct ionic_port_info { 2956 union ionic_port_config config; 2957 struct ionic_port_status status; 2958 union { 2959 struct ionic_port_stats stats; 2960 struct ionic_mgmt_port_stats mgmt_stats; 2961 }; 2962 union { 2963 u8 sprom_epage[384]; 2964 struct { 2965 u8 sprom_page1[128]; 2966 u8 sprom_page2[128]; 2967 u8 sprom_page17[128]; 2968 }; 2969 }; 2970 u8 rsvd[376]; 2971 2972 /* pb_stats must start at 2k offset */ 2973 struct ionic_port_pb_stats pb_stats; 2974 }; 2975 2976 /* 2977 * struct ionic_lif_stats - LIF statistics structure 2978 */ 2979 struct ionic_lif_stats { 2980 /* RX */ 2981 __le64 rx_ucast_bytes; 2982 __le64 rx_ucast_packets; 2983 __le64 rx_mcast_bytes; 2984 __le64 rx_mcast_packets; 2985 __le64 rx_bcast_bytes; 2986 __le64 rx_bcast_packets; 2987 __le64 rsvd0; 2988 __le64 rsvd1; 2989 /* RX drops */ 2990 __le64 rx_ucast_drop_bytes; 2991 __le64 rx_ucast_drop_packets; 2992 __le64 rx_mcast_drop_bytes; 2993 __le64 rx_mcast_drop_packets; 2994 __le64 rx_bcast_drop_bytes; 2995 __le64 rx_bcast_drop_packets; 2996 __le64 rx_dma_error; 2997 __le64 rsvd2; 2998 /* TX */ 2999 __le64 tx_ucast_bytes; 3000 __le64 tx_ucast_packets; 3001 __le64 tx_mcast_bytes; 3002 __le64 tx_mcast_packets; 3003 __le64 tx_bcast_bytes; 3004 __le64 tx_bcast_packets; 3005 __le64 rsvd3; 3006 __le64 rsvd4; 3007 /* TX drops */ 3008 __le64 tx_ucast_drop_bytes; 3009 __le64 tx_ucast_drop_packets; 3010 __le64 tx_mcast_drop_bytes; 3011 __le64 tx_mcast_drop_packets; 3012 __le64 tx_bcast_drop_bytes; 3013 __le64 tx_bcast_drop_packets; 3014 __le64 tx_dma_error; 3015 __le64 rsvd5; 3016 /* Rx Queue/Ring drops */ 3017 __le64 rx_queue_disabled; 3018 __le64 rx_queue_empty; 3019 __le64 rx_queue_error; 3020 __le64 rx_desc_fetch_error; 3021 __le64 rx_desc_data_error; 3022 __le64 rsvd6; 3023 __le64 rsvd7; 3024 __le64 rsvd8; 3025 /* Tx Queue/Ring drops */ 3026 __le64 tx_queue_disabled; 3027 __le64 tx_queue_error; 3028 __le64 tx_desc_fetch_error; 3029 __le64 tx_desc_data_error; 3030 __le64 tx_queue_empty; 3031 __le64 rsvd10; 3032 __le64 rsvd11; 3033 __le64 rsvd12; 3034 3035 /* RDMA/ROCE TX */ 3036 __le64 tx_rdma_ucast_bytes; 3037 __le64 tx_rdma_ucast_packets; 3038 __le64 tx_rdma_mcast_bytes; 3039 __le64 tx_rdma_mcast_packets; 3040 __le64 tx_rdma_cnp_packets; 3041 __le64 rsvd13; 3042 __le64 rsvd14; 3043 __le64 rsvd15; 3044 3045 /* RDMA/ROCE RX */ 3046 __le64 rx_rdma_ucast_bytes; 3047 __le64 rx_rdma_ucast_packets; 3048 __le64 rx_rdma_mcast_bytes; 3049 __le64 rx_rdma_mcast_packets; 3050 __le64 rx_rdma_cnp_packets; 3051 __le64 rx_rdma_ecn_packets; 3052 __le64 rsvd16; 3053 __le64 rsvd17; 3054 3055 __le64 rsvd18; 3056 __le64 rsvd19; 3057 __le64 rsvd20; 3058 __le64 rsvd21; 3059 __le64 rsvd22; 3060 __le64 rsvd23; 3061 __le64 rsvd24; 3062 __le64 rsvd25; 3063 3064 __le64 rsvd26; 3065 __le64 rsvd27; 3066 __le64 rsvd28; 3067 __le64 rsvd29; 3068 __le64 rsvd30; 3069 __le64 rsvd31; 3070 __le64 rsvd32; 3071 __le64 rsvd33; 3072 3073 __le64 rsvd34; 3074 __le64 rsvd35; 3075 __le64 rsvd36; 3076 __le64 rsvd37; 3077 __le64 rsvd38; 3078 __le64 rsvd39; 3079 __le64 rsvd40; 3080 __le64 rsvd41; 3081 3082 __le64 rsvd42; 3083 __le64 rsvd43; 3084 __le64 rsvd44; 3085 __le64 rsvd45; 3086 __le64 rsvd46; 3087 __le64 rsvd47; 3088 __le64 rsvd48; 3089 __le64 rsvd49; 3090 3091 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 3092 __le64 rdma_req_rx_pkt_seq_err; 3093 __le64 rdma_req_rx_rnr_retry_err; 3094 __le64 rdma_req_rx_remote_access_err; 3095 __le64 rdma_req_rx_remote_inv_req_err; 3096 __le64 rdma_req_rx_remote_oper_err; 3097 __le64 rdma_req_rx_implied_nak_seq_err; 3098 __le64 rdma_req_rx_cqe_err; 3099 __le64 rdma_req_rx_cqe_flush_err; 3100 3101 __le64 rdma_req_rx_dup_responses; 3102 __le64 rdma_req_rx_invalid_packets; 3103 __le64 rdma_req_tx_local_access_err; 3104 __le64 rdma_req_tx_local_oper_err; 3105 __le64 rdma_req_tx_memory_mgmt_err; 3106 __le64 rsvd52; 3107 __le64 rsvd53; 3108 __le64 rsvd54; 3109 3110 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 3111 __le64 rdma_resp_rx_dup_requests; 3112 __le64 rdma_resp_rx_out_of_buffer; 3113 __le64 rdma_resp_rx_out_of_seq_pkts; 3114 __le64 rdma_resp_rx_cqe_err; 3115 __le64 rdma_resp_rx_cqe_flush_err; 3116 __le64 rdma_resp_rx_local_len_err; 3117 __le64 rdma_resp_rx_inv_request_err; 3118 __le64 rdma_resp_rx_local_qp_oper_err; 3119 3120 __le64 rdma_resp_rx_out_of_atomic_resource; 3121 __le64 rdma_resp_tx_pkt_seq_err; 3122 __le64 rdma_resp_tx_remote_inv_req_err; 3123 __le64 rdma_resp_tx_remote_access_err; 3124 __le64 rdma_resp_tx_remote_oper_err; 3125 __le64 rdma_resp_tx_rnr_retry_err; 3126 __le64 rsvd57; 3127 __le64 rsvd58; 3128 }; 3129 3130 /** 3131 * struct ionic_lif_info - LIF info structure 3132 * @config: LIF configuration structure 3133 * @status: LIF status structure 3134 * @stats: LIF statistics structure 3135 */ 3136 struct ionic_lif_info { 3137 union ionic_lif_config config; 3138 struct ionic_lif_status status; 3139 struct ionic_lif_stats stats; 3140 }; 3141 3142 union ionic_dev_cmd { 3143 u32 words[16]; 3144 struct ionic_admin_cmd cmd; 3145 struct ionic_nop_cmd nop; 3146 3147 struct ionic_dev_identify_cmd identify; 3148 struct ionic_dev_init_cmd init; 3149 struct ionic_dev_reset_cmd reset; 3150 struct ionic_dev_getattr_cmd getattr; 3151 struct ionic_dev_setattr_cmd setattr; 3152 3153 struct ionic_port_identify_cmd port_identify; 3154 struct ionic_port_init_cmd port_init; 3155 struct ionic_port_reset_cmd port_reset; 3156 struct ionic_port_getattr_cmd port_getattr; 3157 struct ionic_port_setattr_cmd port_setattr; 3158 3159 struct ionic_vf_setattr_cmd vf_setattr; 3160 struct ionic_vf_getattr_cmd vf_getattr; 3161 struct ionic_vf_ctrl_cmd vf_ctrl; 3162 3163 struct ionic_discover_cmb_cmd discover_cmb; 3164 3165 struct ionic_lif_identify_cmd lif_identify; 3166 struct ionic_lif_init_cmd lif_init; 3167 struct ionic_lif_reset_cmd lif_reset; 3168 3169 struct ionic_qos_identify_cmd qos_identify; 3170 struct ionic_qos_init_cmd qos_init; 3171 struct ionic_qos_reset_cmd qos_reset; 3172 struct ionic_qos_clear_stats_cmd qos_clear_stats; 3173 3174 struct ionic_q_identify_cmd q_identify; 3175 struct ionic_q_init_cmd q_init; 3176 struct ionic_q_control_cmd q_control; 3177 3178 struct ionic_fw_download_cmd fw_download; 3179 struct ionic_fw_control_cmd fw_control; 3180 }; 3181 3182 union ionic_dev_cmd_comp { 3183 u32 words[4]; 3184 u8 status; 3185 struct ionic_admin_comp comp; 3186 struct ionic_nop_comp nop; 3187 3188 struct ionic_dev_identify_comp identify; 3189 struct ionic_dev_init_comp init; 3190 struct ionic_dev_reset_comp reset; 3191 struct ionic_dev_getattr_comp getattr; 3192 struct ionic_dev_setattr_comp setattr; 3193 3194 struct ionic_port_identify_comp port_identify; 3195 struct ionic_port_init_comp port_init; 3196 struct ionic_port_reset_comp port_reset; 3197 struct ionic_port_getattr_comp port_getattr; 3198 struct ionic_port_setattr_comp port_setattr; 3199 3200 struct ionic_vf_setattr_comp vf_setattr; 3201 struct ionic_vf_getattr_comp vf_getattr; 3202 struct ionic_vf_ctrl_comp vf_ctrl; 3203 3204 struct ionic_discover_cmb_comp discover_cmb; 3205 3206 struct ionic_lif_identify_comp lif_identify; 3207 struct ionic_lif_init_comp lif_init; 3208 ionic_lif_reset_comp lif_reset; 3209 3210 struct ionic_qos_identify_comp qos_identify; 3211 ionic_qos_init_comp qos_init; 3212 ionic_qos_reset_comp qos_reset; 3213 3214 struct ionic_q_identify_comp q_identify; 3215 struct ionic_q_init_comp q_init; 3216 3217 ionic_fw_download_comp fw_download; 3218 struct ionic_fw_control_comp fw_control; 3219 }; 3220 3221 /** 3222 * struct ionic_hwstamp_regs - Hardware current timestamp registers 3223 * @tick_low: Low 32 bits of hardware timestamp 3224 * @tick_high: High 32 bits of hardware timestamp 3225 */ 3226 struct ionic_hwstamp_regs { 3227 u32 tick_low; 3228 u32 tick_high; 3229 }; 3230 3231 /** 3232 * union ionic_dev_info_regs - Device info register format (read-only) 3233 * @signature: Signature value of 0x44455649 ('DEVI') 3234 * @version: Current version of info 3235 * @asic_type: Asic type 3236 * @asic_rev: Asic revision 3237 * @fw_status: Firmware status 3238 * bit 0 - 1 = fw running 3239 * bit 4-7 - 4 bit generation number, changes on fw restart 3240 * @fw_heartbeat: Firmware heartbeat counter 3241 * @serial_num: Serial number 3242 * @rsvd_pad1024: reserved byte(s) 3243 * @fw_version: Firmware version 3244 * @hwstamp: Hardware current timestamp registers 3245 * @words: word access to struct contents 3246 */ 3247 union ionic_dev_info_regs { 3248 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 3249 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 3250 struct { 3251 u32 signature; 3252 u8 version; 3253 u8 asic_type; 3254 u8 asic_rev; 3255 #define IONIC_FW_STS_F_RUNNING 0x01 3256 #define IONIC_FW_STS_F_GENERATION 0xF0 3257 u8 fw_status; 3258 u32 fw_heartbeat; 3259 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 3260 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 3261 u8 rsvd_pad1024[948]; 3262 struct ionic_hwstamp_regs hwstamp; 3263 }; 3264 u32 words[512]; 3265 }; 3266 3267 /** 3268 * union ionic_dev_cmd_regs - Device command register format (read-write) 3269 * @doorbell: Device Cmd Doorbell, write-only 3270 * Write a 1 to signal device to process cmd, 3271 * poll done for completion. 3272 * @done: Done indicator, bit 0 == 1 when command is complete 3273 * @cmd: Opcode-specific command bytes 3274 * @comp: Opcode-specific response bytes 3275 * @rsvd: reserved byte(s) 3276 * @data: Opcode-specific side-data 3277 * @words: word access to struct contents 3278 */ 3279 union ionic_dev_cmd_regs { 3280 struct { 3281 u32 doorbell; 3282 u32 done; 3283 union ionic_dev_cmd cmd; 3284 union ionic_dev_cmd_comp comp; 3285 u8 rsvd[48]; 3286 u32 data[478]; 3287 } __packed; 3288 u32 words[512]; 3289 }; 3290 3291 /** 3292 * union ionic_dev_regs - Device register format for bar 0 page 0 3293 * @info: Device info registers 3294 * @devcmd: Device command registers 3295 * @words: word access to struct contents 3296 */ 3297 union ionic_dev_regs { 3298 struct { 3299 union ionic_dev_info_regs info; 3300 union ionic_dev_cmd_regs devcmd; 3301 } __packed; 3302 __le32 words[1024]; 3303 }; 3304 3305 union ionic_adminq_cmd { 3306 struct ionic_admin_cmd cmd; 3307 struct ionic_nop_cmd nop; 3308 struct ionic_q_identify_cmd q_identify; 3309 struct ionic_q_init_cmd q_init; 3310 struct ionic_q_control_cmd q_control; 3311 struct ionic_lif_setattr_cmd lif_setattr; 3312 struct ionic_lif_getattr_cmd lif_getattr; 3313 struct ionic_lif_setphc_cmd lif_setphc; 3314 struct ionic_rx_mode_set_cmd rx_mode_set; 3315 struct ionic_rx_filter_add_cmd rx_filter_add; 3316 struct ionic_rx_filter_del_cmd rx_filter_del; 3317 struct ionic_rdma_reset_cmd rdma_reset; 3318 struct ionic_rdma_queue_cmd rdma_queue; 3319 struct ionic_fw_download_cmd fw_download; 3320 struct ionic_fw_control_cmd fw_control; 3321 }; 3322 3323 union ionic_adminq_comp { 3324 struct ionic_admin_comp comp; 3325 struct ionic_nop_comp nop; 3326 struct ionic_q_identify_comp q_identify; 3327 struct ionic_q_init_comp q_init; 3328 struct ionic_lif_setattr_comp lif_setattr; 3329 struct ionic_lif_getattr_comp lif_getattr; 3330 struct ionic_admin_comp lif_setphc; 3331 struct ionic_rx_filter_add_comp rx_filter_add; 3332 struct ionic_fw_control_comp fw_control; 3333 }; 3334 3335 #define IONIC_BARS_MAX 6 3336 #define IONIC_PCI_BAR_DBELL 1 3337 #define IONIC_PCI_BAR_CMB 2 3338 3339 #define IONIC_BAR0_SIZE 0x8000 3340 #define IONIC_BAR2_SIZE 0x800000 3341 3342 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 3343 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 3344 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 3345 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 3346 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 3347 3348 /* BAR2 */ 3349 #define IONIC_BAR2_CMB_ENTRY_SIZE 0x800000 3350 #define IONIC_DEV_CMD_DONE 0x00000001 3351 3352 #define IONIC_ASIC_TYPE_NONE 0 3353 #define IONIC_ASIC_TYPE_CAPRI 1 3354 #define IONIC_ASIC_TYPE_ELBA 2 3355 #define IONIC_ASIC_TYPE_GIGLIO 3 3356 #define IONIC_ASIC_TYPE_SALINA 4 3357 3358 /** 3359 * struct ionic_doorbell - Doorbell register layout 3360 * @p_index: Producer index 3361 * @ring: Selects the specific ring of the queue to update 3362 * Type-specific meaning: 3363 * ring=0: Default producer/consumer queue 3364 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 3365 * send events to EQs when armed. EQs send 3366 * interrupts when armed. 3367 * @qid_lo: Queue destination for the producer index and flags (low bits) 3368 * @qid_hi: Queue destination for the producer index and flags (high bits) 3369 * @rsvd2: reserved byte(s) 3370 */ 3371 struct ionic_doorbell { 3372 __le16 p_index; 3373 u8 ring; 3374 u8 qid_lo; 3375 __le16 qid_hi; 3376 u16 rsvd2; 3377 }; 3378 3379 struct ionic_intr_status { 3380 u32 status[2]; 3381 }; 3382 3383 struct ionic_notifyq_cmd { 3384 __le32 data; /* Not used but needed for qcq structure */ 3385 }; 3386 3387 union ionic_notifyq_comp { 3388 struct ionic_notifyq_event event; 3389 struct ionic_link_change_event link_change; 3390 struct ionic_reset_event reset; 3391 struct ionic_heartbeat_event heartbeat; 3392 struct ionic_log_event log; 3393 }; 3394 3395 /* Deprecate */ 3396 struct ionic_identity { 3397 union ionic_drv_identity drv; 3398 union ionic_dev_identity dev; 3399 union ionic_lif_identity lif; 3400 union ionic_port_identity port; 3401 union ionic_qos_identity qos; 3402 union ionic_q_identity txq; 3403 union ionic_discover_cmb_identity cmb_layout; 3404 }; 3405 3406 #endif /* _IONIC_IF_H_ */ 3407