1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * This header file defines the register offsets and bit fields 4 * of ENETC4 PF and VFs. Note that the same registers as ENETC 5 * version 1.0 are defined in the enetc_hw.h file. 6 * 7 * Copyright 2024 NXP 8 */ 9 #ifndef __ENETC4_HW_H_ 10 #define __ENETC4_HW_H_ 11 12 #define NXP_ENETC_VENDOR_ID 0x1131 13 #define NXP_ENETC_PF_DEV_ID 0xe101 14 15 /**********************Station interface registers************************/ 16 /* Station interface LSO segmentation flag mask register 0/1 */ 17 #define ENETC4_SILSOSFMR0 0x1300 18 #define SILSOSFMR0_TCP_MID_SEG GENMASK(27, 16) 19 #define SILSOSFMR0_TCP_1ST_SEG GENMASK(11, 0) 20 #define SILSOSFMR0_VAL_SET(first, mid) (FIELD_PREP(SILSOSFMR0_TCP_MID_SEG, mid) | \ 21 FIELD_PREP(SILSOSFMR0_TCP_1ST_SEG, first)) 22 23 #define ENETC4_SILSOSFMR1 0x1304 24 #define SILSOSFMR1_TCP_LAST_SEG GENMASK(11, 0) 25 #define ENETC4_TCP_FLAGS_FIN BIT(0) 26 #define ENETC4_TCP_FLAGS_SYN BIT(1) 27 #define ENETC4_TCP_FLAGS_RST BIT(2) 28 #define ENETC4_TCP_FLAGS_PSH BIT(3) 29 #define ENETC4_TCP_FLAGS_ACK BIT(4) 30 #define ENETC4_TCP_FLAGS_URG BIT(5) 31 #define ENETC4_TCP_FLAGS_ECE BIT(6) 32 #define ENETC4_TCP_FLAGS_CWR BIT(7) 33 #define ENETC4_TCP_FLAGS_NS BIT(8) 34 /* According to tso_build_hdr(), clear all special flags for not last packet. */ 35 #define ENETC4_TCP_NL_SEG_FLAGS_DMASK (ENETC4_TCP_FLAGS_FIN | \ 36 ENETC4_TCP_FLAGS_RST | ENETC4_TCP_FLAGS_PSH) 37 38 /***************************ENETC port registers**************************/ 39 #define ENETC4_ECAPR0 0x0 40 #define ECAPR0_RFS BIT(2) 41 #define ECAPR0_TSD BIT(5) 42 #define ECAPR0_RSS BIT(8) 43 #define ECAPR0_RSC BIT(9) 44 #define ECAPR0_LSO BIT(10) 45 #define ECAPR0_WO BIT(13) 46 47 #define ENETC4_ECAPR1 0x4 48 #define ECAPR1_NUM_TCS GENMASK(6, 4) 49 #define ECAPR1_NUM_MCH GENMASK(9, 8) 50 #define ECAPR1_NUM_UCH GENMASK(11, 10) 51 #define ECAPR1_NUM_MSIX GENMASK(22, 12) 52 #define ECAPR1_NUM_VSI GENMASK(27, 24) 53 #define ECAPR1_NUM_IPV BIT(31) 54 55 #define ENETC4_ECAPR2 0x8 56 #define ECAPR2_NUM_TX_BDR GENMASK(9, 0) 57 #define ECAPR2_NUM_RX_BDR GENMASK(25, 16) 58 59 #define ENETC4_PMR 0x10 60 #define PMR_SI_EN(a) BIT((16 + (a))) 61 62 /* Port Pause ON/OFF threshold register */ 63 #define ENETC4_PPAUONTR 0x108 64 #define ENETC4_PPAUOFFTR 0x10c 65 66 /* Port Station interface promiscuous MAC mode register */ 67 #define ENETC4_PSIPMMR 0x200 68 #define PSIPMMR_SI_MAC_UP(a) BIT(a) /* a = SI index */ 69 #define PSIPMMR_SI_MAC_MP(a) BIT((a) + 16) 70 71 /* Port Station interface promiscuous VLAN mode register */ 72 #define ENETC4_PSIPVMR 0x204 73 74 /* Port RSS key register n. n = 0,1,2,...,9 */ 75 #define ENETC4_PRSSKR(n) ((n) * 0x4 + 0x250) 76 77 /* Port station interface MAC address filtering capability register */ 78 #define ENETC4_PSIMAFCAPR 0x280 79 #define PSIMAFCAPR_NUM_MAC_AFTE GENMASK(11, 0) 80 81 /* Port station interface VLAN filtering capability register */ 82 #define ENETC4_PSIVLANFCAPR 0x2c0 83 #define PSIVLANFCAPR_NUM_VLAN_FTE GENMASK(11, 0) 84 85 /* Port station interface VLAN filtering mode register */ 86 #define ENETC4_PSIVLANFMR 0x2c4 87 #define PSIVLANFMR_VS BIT(0) 88 89 /* Port Station interface a primary MAC address registers */ 90 #define ENETC4_PSIPMAR0(a) ((a) * 0x80 + 0x2000) 91 #define ENETC4_PSIPMAR1(a) ((a) * 0x80 + 0x2004) 92 93 /* Port station interface a configuration register 0/2 */ 94 #define ENETC4_PSICFGR0(a) ((a) * 0x80 + 0x2010) 95 #define PSICFGR0_VASE BIT(13) 96 #define PSICFGR0_ASE BIT(15) 97 #define PSICFGR0_ANTI_SPOOFING (PSICFGR0_VASE | PSICFGR0_ASE) 98 99 #define ENETC4_PSICFGR2(a) ((a) * 0x80 + 0x2018) 100 #define PSICFGR2_NUM_MSIX GENMASK(5, 0) 101 102 /* Port station interface a unicast MAC hash filter register 0/1 */ 103 #define ENETC4_PSIUMHFR0(a) ((a) * 0x80 + 0x2050) 104 #define ENETC4_PSIUMHFR1(a) ((a) * 0x80 + 0x2054) 105 106 /* Port station interface a multicast MAC hash filter register 0/1 */ 107 #define ENETC4_PSIMMHFR0(a) ((a) * 0x80 + 0x2058) 108 #define ENETC4_PSIMMHFR1(a) ((a) * 0x80 + 0x205c) 109 110 /* Port station interface a VLAN hash filter register 0/1 */ 111 #define ENETC4_PSIVHFR0(a) ((a) * 0x80 + 0x2060) 112 #define ENETC4_PSIVHFR1(a) ((a) * 0x80 + 0x2064) 113 114 #define ENETC4_PMCAPR 0x4004 115 #define PMCAPR_HD BIT(8) 116 #define PMCAPR_FP GENMASK(10, 9) 117 118 /* Port configuration register */ 119 #define ENETC4_PCR 0x4010 120 #define PCR_HDR_FMT BIT(0) 121 #define PCR_L2DOSE BIT(4) 122 #define PCR_TIMER_CS BIT(8) 123 #define PCR_PSPEED GENMASK(29, 16) 124 #define PCR_PSPEED_VAL(speed) (((speed) / 10 - 1) << 16) 125 126 /* Port MAC address register 0/1 */ 127 #define ENETC4_PMAR0 0x4020 128 #define ENETC4_PMAR1 0x4024 129 130 /* Port operational register */ 131 #define ENETC4_POR 0x4100 132 133 /* Port traffic class a transmit maximum SDU register */ 134 #define ENETC4_PTCTMSDUR(a) ((a) * 0x20 + 0x4208) 135 #define PTCTMSDUR_MAXSDU GENMASK(15, 0) 136 #define PTCTMSDUR_SDU_TYPE GENMASK(17, 16) 137 #define SDU_TYPE_PPDU 0 138 #define SDU_TYPE_MPDU 1 139 #define SDU_TYPE_MSDU 2 140 141 #define ENETC4_PMAC_OFFSET 0x400 142 #define ENETC4_PM_CMD_CFG(mac) (0x5008 + (mac) * 0x400) 143 #define PM_CMD_CFG_TX_EN BIT(0) 144 #define PM_CMD_CFG_RX_EN BIT(1) 145 #define PM_CMD_CFG_PAUSE_FWD BIT(7) 146 #define PM_CMD_CFG_PAUSE_IGN BIT(8) 147 #define PM_CMD_CFG_TX_ADDR_INS BIT(9) 148 #define PM_CMD_CFG_LOOP_EN BIT(10) 149 #define PM_CMD_CFG_LPBK_MODE GENMASK(12, 11) 150 #define LPBCK_MODE_EXT_TX_CLK 0 151 #define LPBCK_MODE_MAC_LEVEL 1 152 #define LPBCK_MODE_INT_TX_CLK 2 153 #define PM_CMD_CFG_CNT_FRM_EN BIT(13) 154 #define PM_CMD_CFG_TXP BIT(15) 155 #define PM_CMD_CFG_SEND_IDLE BIT(16) 156 #define PM_CMD_CFG_HD_FCEN BIT(18) 157 #define PM_CMD_CFG_SFD BIT(21) 158 #define PM_CMD_CFG_TX_FLUSH BIT(22) 159 #define PM_CMD_CFG_TX_LOWP_EN BIT(23) 160 #define PM_CMD_CFG_RX_LOWP_EMPTY BIT(24) 161 #define PM_CMD_CFG_SWR BIT(26) 162 #define PM_CMD_CFG_TS_MODE BIT(30) 163 #define PM_CMD_CFG_MG BIT(31) 164 165 /* Port MAC 0/1 Maximum Frame Length Register */ 166 #define ENETC4_PM_MAXFRM(mac) (0x5014 + (mac) * 0x400) 167 168 /* Port MAC 0/1 Pause Quanta Register */ 169 #define ENETC4_PM_PAUSE_QUANTA(mac) (0x5054 + (mac) * 0x400) 170 171 /* Port MAC 0/1 Pause Quanta Threshold Register */ 172 #define ENETC4_PM_PAUSE_THRESH(mac) (0x5064 + (mac) * 0x400) 173 174 /* Port MAC 0 Interface Mode Control Register */ 175 #define ENETC4_PM_IF_MODE(mac) (0x5300 + (mac) * 0x400) 176 #define PM_IF_MODE_IFMODE GENMASK(2, 0) 177 #define IFMODE_XGMII 0 178 #define IFMODE_RMII 3 179 #define IFMODE_RGMII 4 180 #define IFMODE_SGMII 5 181 #define PM_IF_MODE_REVMII BIT(3) 182 #define PM_IF_MODE_M10 BIT(4) 183 #define PM_IF_MODE_HD BIT(6) 184 #define PM_IF_MODE_SSP GENMASK(14, 13) 185 #define SSP_100M 0 186 #define SSP_10M 1 187 #define SSP_1G 2 188 #define PM_IF_MODE_ENA BIT(15) 189 190 #endif 191