1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2022 Intel Corporation */ 3 #ifndef _ICP_QAT_FW_COMP_H_ 4 #define _ICP_QAT_FW_COMP_H_ 5 #include "icp_qat_fw.h" 6 7 enum icp_qat_fw_comp_cmd_id { 8 ICP_QAT_FW_COMP_CMD_STATIC = 0, 9 ICP_QAT_FW_COMP_CMD_DYNAMIC = 1, 10 ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2, 11 ICP_QAT_FW_COMP_CMD_DELIMITER 12 }; 13 14 enum icp_qat_fw_comp_20_cmd_id { 15 ICP_QAT_FW_COMP_20_CMD_LZ4_COMPRESS = 3, 16 ICP_QAT_FW_COMP_20_CMD_LZ4_DECOMPRESS = 4, 17 ICP_QAT_FW_COMP_20_CMD_LZ4S_COMPRESS = 5, 18 ICP_QAT_FW_COMP_20_CMD_LZ4S_DECOMPRESS = 6, 19 ICP_QAT_FW_COMP_20_CMD_RESERVED_7 = 7, 20 ICP_QAT_FW_COMP_20_CMD_RESERVED_8 = 8, 21 ICP_QAT_FW_COMP_20_CMD_RESERVED_9 = 9, 22 ICP_QAT_FW_COMP_23_CMD_ZSTD_COMPRESS = 10, 23 ICP_QAT_FW_COMP_23_CMD_ZSTD_DECOMPRESS = 11, 24 ICP_QAT_FW_COMP_20_CMD_DELIMITER 25 }; 26 27 #define ICP_QAT_FW_COMP_STATELESS_SESSION 0 28 #define ICP_QAT_FW_COMP_STATEFUL_SESSION 1 29 #define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0 30 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1 31 #define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0 32 #define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1 33 #define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0 34 #define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1 35 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1 36 #define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0 37 #define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2 38 #define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1 39 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3 40 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1 41 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4 42 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1 43 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5 44 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1 45 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7 46 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1 47 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MAX_VALUE 0xFFFFFFFF 48 49 #define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \ 50 ret_uncomp, secure_ram) \ 51 ((((sesstype) & ICP_QAT_FW_COMP_SESSION_TYPE_MASK) << \ 52 ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \ 53 (((autoselect) & ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) << \ 54 ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \ 55 (((enhanced_asb) & ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) << \ 56 ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \ 57 (((ret_uncomp) & ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) << \ 58 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \ 59 (((secure_ram) & ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) << \ 60 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS)) 61 62 #define ICP_QAT_FW_COMP_SESSION_TYPE_GET(flags) \ 63 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS, \ 64 ICP_QAT_FW_COMP_SESSION_TYPE_MASK) 65 66 #define ICP_QAT_FW_COMP_SESSION_TYPE_SET(flags, val) \ 67 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS, \ 68 ICP_QAT_FW_COMP_SESSION_TYPE_MASK) 69 70 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_GET(flags) \ 71 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS, \ 72 ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) 73 74 #define ICP_QAT_FW_COMP_EN_ASB_GET(flags) \ 75 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS, \ 76 ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) 77 78 #define ICP_QAT_FW_COMP_RET_UNCOMP_GET(flags) \ 79 QAT_FIELD_GET(flags, \ 80 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS, \ 81 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) 82 83 #define ICP_QAT_FW_COMP_SECURE_RAM_USE_GET(flags) \ 84 QAT_FIELD_GET(flags, \ 85 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS, \ 86 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) 87 88 struct icp_qat_fw_comp_req_hdr_cd_pars { 89 union { 90 struct { 91 __u64 content_desc_addr; 92 __u16 content_desc_resrvd1; 93 __u8 content_desc_params_sz; 94 __u8 content_desc_hdr_resrvd2; 95 __u32 content_desc_resrvd3; 96 } s; 97 struct { 98 __u32 comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2]; 99 __u32 content_desc_resrvd4; 100 } sl; 101 } u; 102 }; 103 104 struct icp_qat_fw_comp_req_params { 105 __u32 comp_len; 106 __u32 out_buffer_sz; 107 union { 108 struct { 109 __u32 initial_crc32; 110 __u32 initial_adler; 111 } legacy; 112 __u64 crc_data_addr; 113 } crc; 114 __u32 req_par_flags; 115 __u32 rsrvd; 116 }; 117 118 #define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr, \ 119 cnvdfx, crc, xxhash_acc, \ 120 cnv_error_type, append_crc, \ 121 drop_data, partial_decomp) \ 122 ((((sop) & ICP_QAT_FW_COMP_SOP_MASK) << \ 123 ICP_QAT_FW_COMP_SOP_BITPOS) | \ 124 (((eop) & ICP_QAT_FW_COMP_EOP_MASK) << \ 125 ICP_QAT_FW_COMP_EOP_BITPOS) | \ 126 (((bfinal) & ICP_QAT_FW_COMP_BFINAL_MASK) \ 127 << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \ 128 (((cnv) & ICP_QAT_FW_COMP_CNV_MASK) << \ 129 ICP_QAT_FW_COMP_CNV_BITPOS) | \ 130 (((cnvnr) & ICP_QAT_FW_COMP_CNVNR_MASK) \ 131 << ICP_QAT_FW_COMP_CNVNR_BITPOS) | \ 132 (((cnvdfx) & ICP_QAT_FW_COMP_CNV_DFX_MASK) \ 133 << ICP_QAT_FW_COMP_CNV_DFX_BITPOS) | \ 134 (((crc) & ICP_QAT_FW_COMP_CRC_MODE_MASK) \ 135 << ICP_QAT_FW_COMP_CRC_MODE_BITPOS) | \ 136 (((xxhash_acc) & ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) \ 137 << ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS) | \ 138 (((cnv_error_type) & ICP_QAT_FW_COMP_CNV_ERROR_MASK) \ 139 << ICP_QAT_FW_COMP_CNV_ERROR_BITPOS) | \ 140 (((append_crc) & ICP_QAT_FW_COMP_APPEND_CRC_MASK) \ 141 << ICP_QAT_FW_COMP_APPEND_CRC_BITPOS) | \ 142 (((drop_data) & ICP_QAT_FW_COMP_DROP_DATA_MASK) \ 143 << ICP_QAT_FW_COMP_DROP_DATA_BITPOS) | \ 144 (((partial_decomp) & ICP_QAT_FW_COMP_PARTIAL_DECOMP_MASK) \ 145 << ICP_QAT_FW_COMP_PARTIAL_DECOMP_BITPOS)) 146 147 #define ICP_QAT_FW_COMP_NOT_SOP 0 148 #define ICP_QAT_FW_COMP_SOP 1 149 #define ICP_QAT_FW_COMP_NOT_EOP 0 150 #define ICP_QAT_FW_COMP_EOP 1 151 #define ICP_QAT_FW_COMP_NOT_BFINAL 0 152 #define ICP_QAT_FW_COMP_BFINAL 1 153 #define ICP_QAT_FW_COMP_NO_CNV 0 154 #define ICP_QAT_FW_COMP_CNV 1 155 #define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0 156 #define ICP_QAT_FW_COMP_CNV_RECOVERY 1 157 #define ICP_QAT_FW_COMP_NO_CNV_DFX 0 158 #define ICP_QAT_FW_COMP_CNV_DFX 1 159 #define ICP_QAT_FW_COMP_CRC_MODE_LEGACY 0 160 #define ICP_QAT_FW_COMP_CRC_MODE_E2E 1 161 #define ICP_QAT_FW_COMP_NO_XXHASH_ACC 0 162 #define ICP_QAT_FW_COMP_XXHASH_ACC 1 163 #define ICP_QAT_FW_COMP_APPEND_CRC 1 164 #define ICP_QAT_FW_COMP_NO_APPEND_CRC 0 165 #define ICP_QAT_FW_COMP_DROP_DATA 1 166 #define ICP_QAT_FW_COMP_NO_DROP_DATA 0 167 #define ICP_QAT_FW_COMP_PARTIAL_DECOMPRESS 1 168 #define ICP_QAT_FW_COMP_NO_PARTIAL_DECOMPRESS 0 169 #define ICP_QAT_FW_COMP_SOP_BITPOS 0 170 #define ICP_QAT_FW_COMP_SOP_MASK 0x1 171 #define ICP_QAT_FW_COMP_EOP_BITPOS 1 172 #define ICP_QAT_FW_COMP_EOP_MASK 0x1 173 #define ICP_QAT_FW_COMP_BFINAL_BITPOS 6 174 #define ICP_QAT_FW_COMP_BFINAL_MASK 0x1 175 #define ICP_QAT_FW_COMP_CNV_BITPOS 16 176 #define ICP_QAT_FW_COMP_CNV_MASK 0x1 177 #define ICP_QAT_FW_COMP_CNVNR_BITPOS 17 178 #define ICP_QAT_FW_COMP_CNVNR_MASK 0x1 179 #define ICP_QAT_FW_COMP_CNV_DFX_BITPOS 18 180 #define ICP_QAT_FW_COMP_CNV_DFX_MASK 0x1 181 #define ICP_QAT_FW_COMP_CRC_MODE_BITPOS 19 182 #define ICP_QAT_FW_COMP_CRC_MODE_MASK 0x1 183 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS 20 184 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK 0x1 185 #define ICP_QAT_FW_COMP_CNV_ERROR_BITPOS 21 186 #define ICP_QAT_FW_COMP_CNV_ERROR_MASK 0b111 187 #define ICP_QAT_FW_COMP_CNV_ERROR_NONE 0b000 188 #define ICP_QAT_FW_COMP_CNV_ERROR_CHECKSUM 0b001 189 #define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_OBC_DIFF 0b010 190 #define ICP_QAT_FW_COMP_CNV_ERROR_DCPR 0b011 191 #define ICP_QAT_FW_COMP_CNV_ERROR_XLT 0b100 192 #define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_IBC_DIFF 0b101 193 #define ICP_QAT_FW_COMP_APPEND_CRC_BITPOS 24 194 #define ICP_QAT_FW_COMP_APPEND_CRC_MASK 0x1 195 #define ICP_QAT_FW_COMP_DROP_DATA_BITPOS 25 196 #define ICP_QAT_FW_COMP_DROP_DATA_MASK 0x1 197 #define ICP_QAT_FW_COMP_PARTIAL_DECOMP_BITPOS 27 198 #define ICP_QAT_FW_COMP_PARTIAL_DECOMP_MASK 0x1 199 200 #define ICP_QAT_FW_COMP_SOP_GET(flags) \ 201 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_SOP_BITPOS, \ 202 ICP_QAT_FW_COMP_SOP_MASK) 203 204 #define ICP_QAT_FW_COMP_SOP_SET(flags, val) \ 205 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_SOP_BITPOS, \ 206 ICP_QAT_FW_COMP_SOP_MASK) 207 208 #define ICP_QAT_FW_COMP_EOP_GET(flags) \ 209 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_EOP_BITPOS, \ 210 ICP_QAT_FW_COMP_EOP_MASK) 211 212 #define ICP_QAT_FW_COMP_EOP_SET(flags, val) \ 213 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_EOP_BITPOS, \ 214 ICP_QAT_FW_COMP_EOP_MASK) 215 216 #define ICP_QAT_FW_COMP_BFINAL_GET(flags) \ 217 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_BFINAL_BITPOS, \ 218 ICP_QAT_FW_COMP_BFINAL_MASK) 219 220 #define ICP_QAT_FW_COMP_BFINAL_SET(flags, val) \ 221 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_BFINAL_BITPOS, \ 222 ICP_QAT_FW_COMP_BFINAL_MASK) 223 224 #define ICP_QAT_FW_COMP_CNV_GET(flags) \ 225 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_BITPOS, \ 226 ICP_QAT_FW_COMP_CNV_MASK) 227 228 #define ICP_QAT_FW_COMP_CNVNR_GET(flags) \ 229 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNVNR_BITPOS, \ 230 ICP_QAT_FW_COMP_CNVNR_MASK) 231 232 #define ICP_QAT_FW_COMP_CNV_DFX_GET(flags) \ 233 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_DFX_BITPOS, \ 234 ICP_QAT_FW_COMP_CNV_DFX_MASK) 235 236 #define ICP_QAT_FW_COMP_CNV_DFX_SET(flags, val) \ 237 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_CNV_DFX_BITPOS, \ 238 ICP_QAT_FW_COMP_CNV_DFX_MASK) 239 240 #define ICP_QAT_FW_COMP_CRC_MODE_GET(flags) \ 241 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CRC_MODE_BITPOS, \ 242 ICP_QAT_FW_COMP_CRC_MODE_MASK) 243 244 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_GET(flags) \ 245 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \ 246 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) 247 248 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_SET(flags, val) \ 249 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \ 250 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) 251 252 #define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_GET(flags) \ 253 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_ERROR_BITPOS, \ 254 ICP_QAT_FW_COMP_CNV_ERROR_MASK) 255 256 #define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_SET(flags, val) \ 257 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_CNV_ERROR_BITPOS, \ 258 ICP_QAT_FW_COMP_CNV_ERROR_MASK) 259 260 struct icp_qat_fw_xlt_req_params { 261 __u64 inter_buff_ptr; 262 }; 263 264 struct icp_qat_fw_comp_cd_hdr { 265 __u16 ram_bank_flags; 266 __u8 comp_cfg_offset; 267 __u8 next_curr_id; 268 __u32 resrvd; 269 __u64 comp_state_addr; 270 __u64 ram_banks_addr; 271 }; 272 273 #define COMP_CPR_INITIAL_CRC 0 274 #define COMP_CPR_INITIAL_ADLER 1 275 276 struct icp_qat_fw_xlt_cd_hdr { 277 __u16 resrvd1; 278 __u8 resrvd2; 279 __u8 next_curr_id; 280 __u32 resrvd3; 281 }; 282 283 struct icp_qat_fw_comp_req { 284 struct icp_qat_fw_comn_req_hdr comn_hdr; 285 struct icp_qat_fw_comp_req_hdr_cd_pars cd_pars; 286 struct icp_qat_fw_comn_req_mid comn_mid; 287 struct icp_qat_fw_comp_req_params comp_pars; 288 union { 289 struct icp_qat_fw_xlt_req_params xlt_pars; 290 __u32 resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2]; 291 struct { 292 __u32 partial_decompress_length; 293 __u32 partial_decompress_offset; 294 } partial_decompress; 295 } u1; 296 union { 297 __u32 resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2]; 298 struct { 299 __u32 asb_value; 300 __u32 reserved; 301 } asb_threshold; 302 } u3; 303 struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl; 304 union { 305 struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl; 306 __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2]; 307 } u2; 308 }; 309 310 struct icp_qat_fw_resp_comp_pars { 311 __u32 input_byte_counter; 312 __u32 output_byte_counter; 313 union { 314 struct { 315 __u32 curr_crc32; 316 __u32 curr_adler_32; 317 } legacy; 318 __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_2]; 319 } crc; 320 }; 321 322 struct icp_qat_fw_comp_state { 323 __u32 rd8_counter; 324 __u32 status_flags; 325 __u32 in_counter; 326 __u32 out_counter; 327 __u64 intermediate_state; 328 __u32 lobc; 329 __u32 replaybc; 330 __u64 pcrc64_poly; 331 __u32 crc32; 332 __u32 adler_xxhash32; 333 __u64 pcrc64_xorout; 334 __u32 out_buf_size; 335 __u32 in_buf_size; 336 __u64 in_pcrc64; 337 __u64 out_pcrc64; 338 __u32 lobs; 339 __u32 libc; 340 __u64 reserved; 341 __u32 xxhash_state[4]; 342 __u32 cleartext[4]; 343 }; 344 345 struct icp_qat_fw_comp_resp { 346 struct icp_qat_fw_comn_resp_hdr comn_resp; 347 __u64 opaque_data; 348 struct icp_qat_fw_resp_comp_pars comp_resp_pars; 349 }; 350 351 #define QAT_FW_COMP_BANK_FLAG_MASK 0x1 352 #define QAT_FW_COMP_BANK_I_BITPOS 8 353 #define QAT_FW_COMP_BANK_H_BITPOS 7 354 #define QAT_FW_COMP_BANK_G_BITPOS 6 355 #define QAT_FW_COMP_BANK_F_BITPOS 5 356 #define QAT_FW_COMP_BANK_E_BITPOS 4 357 #define QAT_FW_COMP_BANK_D_BITPOS 3 358 #define QAT_FW_COMP_BANK_C_BITPOS 2 359 #define QAT_FW_COMP_BANK_B_BITPOS 1 360 #define QAT_FW_COMP_BANK_A_BITPOS 0 361 362 enum icp_qat_fw_comp_bank_enabled { 363 ICP_QAT_FW_COMP_BANK_DISABLED = 0, 364 ICP_QAT_FW_COMP_BANK_ENABLED = 1, 365 ICP_QAT_FW_COMP_BANK_DELIMITER = 2 366 }; 367 368 #define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable, bank_h_enable, \ 369 bank_g_enable, bank_f_enable, \ 370 bank_e_enable, bank_d_enable, \ 371 bank_c_enable, bank_b_enable, \ 372 bank_a_enable) \ 373 ((((bank_i_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 374 QAT_FW_COMP_BANK_I_BITPOS) | \ 375 (((bank_h_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 376 QAT_FW_COMP_BANK_H_BITPOS) | \ 377 (((bank_g_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 378 QAT_FW_COMP_BANK_G_BITPOS) | \ 379 (((bank_f_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 380 QAT_FW_COMP_BANK_F_BITPOS) | \ 381 (((bank_e_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 382 QAT_FW_COMP_BANK_E_BITPOS) | \ 383 (((bank_d_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 384 QAT_FW_COMP_BANK_D_BITPOS) | \ 385 (((bank_c_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 386 QAT_FW_COMP_BANK_C_BITPOS) | \ 387 (((bank_b_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 388 QAT_FW_COMP_BANK_B_BITPOS) | \ 389 (((bank_a_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 390 QAT_FW_COMP_BANK_A_BITPOS)) 391 392 struct icp_qat_fw_comp_crc_data_struct { 393 __u32 crc32; 394 union { 395 __u32 adler; 396 __u32 xxhash; 397 } adler_xxhash_u; 398 __u32 cpr_in_crc_lo; 399 __u32 cpr_in_crc_hi; 400 __u32 cpr_out_crc_lo; 401 __u32 cpr_out_crc_hi; 402 __u32 xlt_in_crc_lo; 403 __u32 xlt_in_crc_hi; 404 __u32 xlt_out_crc_lo; 405 __u32 xlt_out_crc_hi; 406 __u32 prog_crc_poly_lo; 407 __u32 prog_crc_poly_hi; 408 __u32 xor_out_lo; 409 __u32 xor_out_hi; 410 __u32 append_crc_lo; 411 __u32 append_crc_hi; 412 }; 413 414 struct xxhash_acc_state_buff { 415 __u32 in_counter; 416 __u32 out_counter; 417 __u32 xxhash_state[4]; 418 __u32 clear_txt[4]; 419 }; 420 421 #endif 422