1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include <drv_types.h>
9 #include <hal_data.h>
10 #include <linux/kernel.h>
11
PHY_GetTxPowerByRateBase(struct adapter * Adapter,u8 RfPath,enum rate_section RateSection)12 u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
13 enum rate_section RateSection)
14 {
15 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
16 u8 value = 0;
17
18 if (RfPath >= RF_PATH_MAX)
19 return 0;
20
21 switch (RateSection) {
22 case CCK:
23 value = pHalData->TxPwrByRateBase2_4G[RfPath][0];
24 break;
25 case OFDM:
26 value = pHalData->TxPwrByRateBase2_4G[RfPath][1];
27 break;
28 case HT_MCS0_MCS7:
29 value = pHalData->TxPwrByRateBase2_4G[RfPath][2];
30 break;
31 default:
32 break;
33 }
34
35 return value;
36 }
37
38 static void
phy_SetTxPowerByRateBase(struct adapter * Adapter,u8 RfPath,enum rate_section RateSection,u8 Value)39 phy_SetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
40 enum rate_section RateSection, u8 Value)
41 {
42 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
43
44 if (RfPath >= RF_PATH_MAX)
45 return;
46
47 switch (RateSection) {
48 case CCK:
49 pHalData->TxPwrByRateBase2_4G[RfPath][0] = Value;
50 break;
51 case OFDM:
52 pHalData->TxPwrByRateBase2_4G[RfPath][1] = Value;
53 break;
54 case HT_MCS0_MCS7:
55 pHalData->TxPwrByRateBase2_4G[RfPath][2] = Value;
56 break;
57 default:
58 break;
59 }
60 }
61
phy_StoreTxPowerByRateBase(struct adapter * padapter)62 static void phy_StoreTxPowerByRateBase(struct adapter *padapter)
63 {
64 u8 path, base;
65
66 for (path = RF_PATH_A; path <= RF_PATH_B; ++path) {
67 base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
68 phy_SetTxPowerByRateBase(padapter, path, CCK, base);
69
70 base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
71 phy_SetTxPowerByRateBase(padapter, path, OFDM, base);
72
73 base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
74 phy_SetTxPowerByRateBase(padapter, path, HT_MCS0_MCS7, base);
75 }
76 }
77
PHY_GetRateSectionIndexOfTxPowerByRate(struct adapter * padapter,u32 RegAddr,u32 BitMask)78 u8 PHY_GetRateSectionIndexOfTxPowerByRate(
79 struct adapter *padapter, u32 RegAddr, u32 BitMask
80 )
81 {
82 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
83 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
84 u8 index = 0;
85
86 if (pDM_Odm->PhyRegPgVersion == 0) {
87 switch (RegAddr) {
88 case rTxAGC_A_Rate18_06:
89 index = 0;
90 break;
91 case rTxAGC_A_Rate54_24:
92 index = 1;
93 break;
94 case rTxAGC_A_CCK1_Mcs32:
95 index = 6;
96 break;
97 case rTxAGC_B_CCK11_A_CCK2_11:
98 if (BitMask == bMaskH3Bytes)
99 index = 7;
100 else if (BitMask == 0x000000ff)
101 index = 15;
102 break;
103
104 case rTxAGC_A_Mcs03_Mcs00:
105 index = 2;
106 break;
107 case rTxAGC_A_Mcs07_Mcs04:
108 index = 3;
109 break;
110 case rTxAGC_B_Rate18_06:
111 index = 8;
112 break;
113 case rTxAGC_B_Rate54_24:
114 index = 9;
115 break;
116 case rTxAGC_B_CCK1_55_Mcs32:
117 index = 14;
118 break;
119 case rTxAGC_B_Mcs03_Mcs00:
120 index = 10;
121 break;
122 case rTxAGC_B_Mcs07_Mcs04:
123 index = 11;
124 break;
125 default:
126 break;
127 }
128 }
129
130 return index;
131 }
132
133 void
PHY_GetRateValuesOfTxPowerByRate(struct adapter * padapter,u32 RegAddr,u32 BitMask,u32 Value,u8 * RateIndex,s8 * PwrByRateVal,u8 * RateNum)134 PHY_GetRateValuesOfTxPowerByRate(
135 struct adapter *padapter,
136 u32 RegAddr,
137 u32 BitMask,
138 u32 Value,
139 u8 *RateIndex,
140 s8 *PwrByRateVal,
141 u8 *RateNum
142 )
143 {
144 u8 i = 0;
145
146 switch (RegAddr) {
147 case rTxAGC_A_Rate18_06:
148 case rTxAGC_B_Rate18_06:
149 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
150 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
151 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
152 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
153 for (i = 0; i < 4; ++i) {
154 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
155 ((Value >> (i * 8)) & 0xF));
156 }
157 *RateNum = 4;
158 break;
159
160 case rTxAGC_A_Rate54_24:
161 case rTxAGC_B_Rate54_24:
162 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
163 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
164 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
165 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
166 for (i = 0; i < 4; ++i) {
167 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
168 ((Value >> (i * 8)) & 0xF));
169 }
170 *RateNum = 4;
171 break;
172
173 case rTxAGC_A_CCK1_Mcs32:
174 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
175 PwrByRateVal[0] = (s8) ((((Value >> (8 + 4)) & 0xF)) * 10 +
176 ((Value >> 8) & 0xF));
177 *RateNum = 1;
178 break;
179
180 case rTxAGC_B_CCK11_A_CCK2_11:
181 if (BitMask == 0xffffff00) {
182 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
183 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
184 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
185 for (i = 1; i < 4; ++i) {
186 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
187 ((Value >> (i * 8)) & 0xF));
188 }
189 *RateNum = 3;
190 } else if (BitMask == 0x000000ff) {
191 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
192 PwrByRateVal[0] = (s8) ((((Value >> 4) & 0xF)) * 10 + (Value & 0xF));
193 *RateNum = 1;
194 }
195 break;
196
197 case rTxAGC_A_Mcs03_Mcs00:
198 case rTxAGC_B_Mcs03_Mcs00:
199 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
200 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
201 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
202 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
203 for (i = 0; i < 4; ++i) {
204 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
205 ((Value >> (i * 8)) & 0xF));
206 }
207 *RateNum = 4;
208 break;
209
210 case rTxAGC_A_Mcs07_Mcs04:
211 case rTxAGC_B_Mcs07_Mcs04:
212 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
213 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
214 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
215 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
216 for (i = 0; i < 4; ++i) {
217 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
218 ((Value >> (i * 8)) & 0xF));
219 }
220 *RateNum = 4;
221 break;
222
223 case rTxAGC_B_CCK1_55_Mcs32:
224 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
225 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
226 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
227 for (i = 1; i < 4; ++i) {
228 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
229 ((Value >> (i * 8)) & 0xF));
230 }
231 *RateNum = 3;
232 break;
233
234 case 0xC20:
235 case 0xE20:
236 case 0x1820:
237 case 0x1a20:
238 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
239 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
240 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
241 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
242 for (i = 0; i < 4; ++i) {
243 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
244 ((Value >> (i * 8)) & 0xF));
245 }
246 *RateNum = 4;
247 break;
248
249 case 0xC24:
250 case 0xE24:
251 case 0x1824:
252 case 0x1a24:
253 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
254 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
255 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
256 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
257 for (i = 0; i < 4; ++i) {
258 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
259 ((Value >> (i * 8)) & 0xF));
260 }
261 *RateNum = 4;
262 break;
263
264 case 0xC28:
265 case 0xE28:
266 case 0x1828:
267 case 0x1a28:
268 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
269 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
270 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
271 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
272 for (i = 0; i < 4; ++i) {
273 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
274 ((Value >> (i * 8)) & 0xF));
275 }
276 *RateNum = 4;
277 break;
278
279 case 0xC2C:
280 case 0xE2C:
281 case 0x182C:
282 case 0x1a2C:
283 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
284 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
285 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
286 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
287 for (i = 0; i < 4; ++i) {
288 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
289 ((Value >> (i * 8)) & 0xF));
290 }
291 *RateNum = 4;
292 break;
293
294 case 0xC30:
295 case 0xE30:
296 case 0x1830:
297 case 0x1a30:
298 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
299 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
300 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
301 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
302 for (i = 0; i < 4; ++i) {
303 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
304 ((Value >> (i * 8)) & 0xF));
305 }
306 *RateNum = 4;
307 break;
308
309 default:
310 break;
311 }
312 }
313
PHY_StoreTxPowerByRateNew(struct adapter * padapter,u32 RfPath,u32 RegAddr,u32 BitMask,u32 Data)314 static void PHY_StoreTxPowerByRateNew(struct adapter *padapter, u32 RfPath,
315 u32 RegAddr, u32 BitMask, u32 Data)
316 {
317 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
318 u8 i = 0, rateIndex[4] = {0}, rateNum = 0;
319 s8 PwrByRateVal[4] = {0};
320
321 PHY_GetRateValuesOfTxPowerByRate(padapter, RegAddr, BitMask, Data, rateIndex, PwrByRateVal, &rateNum);
322
323 if (RfPath >= RF_PATH_MAX)
324 return;
325
326 for (i = 0; i < rateNum; ++i) {
327 pHalData->TxPwrByRateOffset[RfPath][rateIndex[i]] = PwrByRateVal[i];
328 }
329 }
330
PHY_StoreTxPowerByRateOld(struct adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)331 static void PHY_StoreTxPowerByRateOld(
332 struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data
333 )
334 {
335 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
336 u8 index = PHY_GetRateSectionIndexOfTxPowerByRate(padapter, RegAddr, BitMask);
337
338 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][index] = Data;
339 }
340
PHY_InitTxPowerByRate(struct adapter * padapter)341 void PHY_InitTxPowerByRate(struct adapter *padapter)
342 {
343 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
344 u8 rfPath, rate;
345
346 for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath)
347 for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
348 pHalData->TxPwrByRateOffset[rfPath][rate] = 0;
349 }
350
PHY_StoreTxPowerByRate(struct adapter * padapter,u32 RfPath,u32 RegAddr,u32 BitMask,u32 Data)351 void PHY_StoreTxPowerByRate(
352 struct adapter *padapter,
353 u32 RfPath,
354 u32 RegAddr,
355 u32 BitMask,
356 u32 Data
357 )
358 {
359 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
360 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
361
362 if (pDM_Odm->PhyRegPgVersion > 0)
363 PHY_StoreTxPowerByRateNew(padapter, RfPath, RegAddr, BitMask, Data);
364 else if (pDM_Odm->PhyRegPgVersion == 0) {
365 PHY_StoreTxPowerByRateOld(padapter, RegAddr, BitMask, Data);
366 }
367 }
368
369 static void
phy_ConvertTxPowerByRateInDbmToRelativeValues(struct adapter * padapter)370 phy_ConvertTxPowerByRateInDbmToRelativeValues(
371 struct adapter *padapter
372 )
373 {
374 u8 base = 0, i = 0, value = 0, path = 0;
375 u8 cckRates[4] = {
376 MGN_1M, MGN_2M, MGN_5_5M, MGN_11M
377 };
378 u8 ofdmRates[8] = {
379 MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M
380 };
381 u8 mcs0_7Rates[8] = {
382 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7
383 };
384 for (path = RF_PATH_A; path < RF_PATH_MAX; ++path) {
385 /* CCK */
386 base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
387 for (i = 0; i < ARRAY_SIZE(cckRates); ++i) {
388 value = PHY_GetTxPowerByRate(padapter, path, cckRates[i]);
389 PHY_SetTxPowerByRate(padapter, path, cckRates[i], value - base);
390 }
391
392 /* OFDM */
393 base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
394 for (i = 0; i < sizeof(ofdmRates); ++i) {
395 value = PHY_GetTxPowerByRate(padapter, path, ofdmRates[i]);
396 PHY_SetTxPowerByRate(padapter, path, ofdmRates[i], value - base);
397 }
398
399 /* HT MCS0~7 */
400 base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
401 for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
402 value = PHY_GetTxPowerByRate(padapter, path, mcs0_7Rates[i]);
403 PHY_SetTxPowerByRate(padapter, path, mcs0_7Rates[i], value - base);
404 }
405 }
406 }
407
408 /*
409 * This function must be called if the value in the PHY_REG_PG.txt(or header)
410 * is exact dBm values
411 */
PHY_TxPowerByRateConfiguration(struct adapter * padapter)412 void PHY_TxPowerByRateConfiguration(struct adapter *padapter)
413 {
414 phy_StoreTxPowerByRateBase(padapter);
415 phy_ConvertTxPowerByRateInDbmToRelativeValues(padapter);
416 }
417
PHY_SetTxPowerIndexByRateSection(struct adapter * padapter,u8 RFPath,u8 Channel,u8 RateSection)418 void PHY_SetTxPowerIndexByRateSection(
419 struct adapter *padapter, u8 RFPath, u8 Channel, u8 RateSection
420 )
421 {
422 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
423
424 if (RateSection == CCK) {
425 u8 cckRates[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
426 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
427 pHalData->CurrentChannelBW,
428 Channel, cckRates,
429 ARRAY_SIZE(cckRates));
430
431 } else if (RateSection == OFDM) {
432 u8 ofdmRates[] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
433 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
434 pHalData->CurrentChannelBW,
435 Channel, ofdmRates,
436 ARRAY_SIZE(ofdmRates));
437
438 } else if (RateSection == HT_MCS0_MCS7) {
439 u8 htRates1T[] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};
440 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
441 pHalData->CurrentChannelBW,
442 Channel, htRates1T,
443 ARRAY_SIZE(htRates1T));
444
445 }
446 }
447
PHY_GetTxPowerIndexBase(struct adapter * padapter,u8 RFPath,u8 Rate,enum channel_width BandWidth,u8 Channel)448 u8 PHY_GetTxPowerIndexBase(
449 struct adapter *padapter,
450 u8 RFPath,
451 u8 Rate,
452 enum channel_width BandWidth,
453 u8 Channel
454 )
455 {
456 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
457 u8 txPower = 0;
458 u8 chnlIdx = (Channel-1);
459
460 if (HAL_IsLegalChannel(padapter, Channel) == false)
461 chnlIdx = 0;
462
463 if (IS_CCK_RATE(Rate))
464 txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
465 else if (MGN_6M <= Rate)
466 txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
467
468 /* OFDM-1T */
469 if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate))
470 txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S];
471
472 if (BandWidth == CHANNEL_WIDTH_20) { /* BW20-1S, BW20-2S */
473 if (MGN_MCS0 <= Rate && Rate <= MGN_MCS7)
474 txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S];
475 } else if (BandWidth == CHANNEL_WIDTH_40) { /* BW40-1S, BW40-2S */
476 if (MGN_MCS0 <= Rate && Rate <= MGN_MCS7)
477 txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];
478 }
479
480 return txPower;
481 }
482
PHY_GetTxPowerTrackingOffset(struct adapter * padapter,u8 RFPath,u8 Rate)483 s8 PHY_GetTxPowerTrackingOffset(struct adapter *padapter, u8 RFPath, u8 Rate)
484 {
485 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
486 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
487 s8 offset = 0;
488
489 if (pDM_Odm->RFCalibrateInfo.TxPowerTrackControl == false)
490 return offset;
491
492 if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M))
493 offset = pDM_Odm->Remnant_CCKSwingIdx;
494 else
495 offset = pDM_Odm->Remnant_OFDMSwingIdx[RFPath];
496
497 return offset;
498 }
499
PHY_GetRateIndexOfTxPowerByRate(u8 Rate)500 u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate)
501 {
502 u8 index = 0;
503 switch (Rate) {
504 case MGN_1M:
505 index = 0;
506 break;
507 case MGN_2M:
508 index = 1;
509 break;
510 case MGN_5_5M:
511 index = 2;
512 break;
513 case MGN_11M:
514 index = 3;
515 break;
516 case MGN_6M:
517 index = 4;
518 break;
519 case MGN_9M:
520 index = 5;
521 break;
522 case MGN_12M:
523 index = 6;
524 break;
525 case MGN_18M:
526 index = 7;
527 break;
528 case MGN_24M:
529 index = 8;
530 break;
531 case MGN_36M:
532 index = 9;
533 break;
534 case MGN_48M:
535 index = 10;
536 break;
537 case MGN_54M:
538 index = 11;
539 break;
540 case MGN_MCS0:
541 index = 12;
542 break;
543 case MGN_MCS1:
544 index = 13;
545 break;
546 case MGN_MCS2:
547 index = 14;
548 break;
549 case MGN_MCS3:
550 index = 15;
551 break;
552 case MGN_MCS4:
553 index = 16;
554 break;
555 case MGN_MCS5:
556 index = 17;
557 break;
558 case MGN_MCS6:
559 index = 18;
560 break;
561 case MGN_MCS7:
562 index = 19;
563 break;
564 default:
565 break;
566 }
567 return index;
568 }
569
PHY_GetTxPowerByRate(struct adapter * padapter,u8 RFPath,u8 Rate)570 s8 PHY_GetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 Rate)
571 {
572 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
573 s8 value = 0;
574 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
575
576 if ((padapter->registrypriv.reg_enable_tx_power_by_rate == 2 &&
577 pHalData->EEPROMRegulatory == 2) ||
578 padapter->registrypriv.reg_enable_tx_power_by_rate == 0)
579 return 0;
580
581 if (RFPath >= RF_PATH_MAX)
582 return value;
583
584 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
585 return value;
586
587 return pHalData->TxPwrByRateOffset[RFPath][rateIndex];
588
589 }
590
PHY_SetTxPowerByRate(struct adapter * padapter,u8 RFPath,u8 Rate,s8 Value)591 void PHY_SetTxPowerByRate(
592 struct adapter *padapter,
593 u8 RFPath,
594 u8 Rate,
595 s8 Value
596 )
597 {
598 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
599 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
600
601 if (RFPath >= RF_PATH_MAX)
602 return;
603
604 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
605 return;
606
607 pHalData->TxPwrByRateOffset[RFPath][rateIndex] = Value;
608 }
609
PHY_SetTxPowerLevelByPath(struct adapter * Adapter,u8 channel,u8 path)610 void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path)
611 {
612 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, CCK);
613
614 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, OFDM);
615 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS0_MCS7);
616 }
617
PHY_SetTxPowerIndexByRateArray(struct adapter * padapter,u8 RFPath,enum channel_width BandWidth,u8 Channel,u8 * Rates,u8 RateArraySize)618 void PHY_SetTxPowerIndexByRateArray(
619 struct adapter *padapter,
620 u8 RFPath,
621 enum channel_width BandWidth,
622 u8 Channel,
623 u8 *Rates,
624 u8 RateArraySize
625 )
626 {
627 u32 powerIndex = 0;
628 int i = 0;
629
630 for (i = 0; i < RateArraySize; ++i) {
631 powerIndex = PHY_GetTxPowerIndex(padapter, RFPath, Rates[i], BandWidth, Channel);
632 PHY_SetTxPowerIndex(padapter, powerIndex, RFPath, Rates[i]);
633 }
634 }
635
phy_GetWorldWideLimit(s8 * LimitTable)636 static s8 phy_GetWorldWideLimit(s8 *LimitTable)
637 {
638 s8 min = LimitTable[0];
639 u8 i = 0;
640
641 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
642 if (LimitTable[i] < min)
643 min = LimitTable[i];
644 }
645
646 return min;
647 }
648
phy_GetChannelIndexOfTxPowerLimit(u8 Channel)649 static s8 phy_GetChannelIndexOfTxPowerLimit(u8 Channel)
650 {
651 return Channel - 1;
652 }
653
get_bandwidth_idx(const enum channel_width bandwidth)654 static s16 get_bandwidth_idx(const enum channel_width bandwidth)
655 {
656 switch (bandwidth) {
657 case CHANNEL_WIDTH_20:
658 return 0;
659 case CHANNEL_WIDTH_40:
660 return 1;
661 default:
662 return -1;
663 }
664 }
665
get_rate_sctn_idx(const u8 rate)666 static s16 get_rate_sctn_idx(const u8 rate)
667 {
668 switch (rate) {
669 case MGN_1M: case MGN_2M: case MGN_5_5M: case MGN_11M:
670 return 0;
671 case MGN_6M: case MGN_9M: case MGN_12M: case MGN_18M:
672 case MGN_24M: case MGN_36M: case MGN_48M: case MGN_54M:
673 return 1;
674 case MGN_MCS0: case MGN_MCS1: case MGN_MCS2: case MGN_MCS3:
675 case MGN_MCS4: case MGN_MCS5: case MGN_MCS6: case MGN_MCS7:
676 return 2;
677 default:
678 return -1;
679 }
680 }
681
phy_get_tx_pwr_lmt(struct adapter * adapter,u32 reg_pwr_tbl_sel,enum channel_width bandwidth,u8 rf_path,u8 data_rate,u8 channel)682 s8 phy_get_tx_pwr_lmt(struct adapter *adapter, u32 reg_pwr_tbl_sel,
683 enum channel_width bandwidth,
684 u8 rf_path, u8 data_rate, u8 channel)
685 {
686 s16 idx_regulation = -1;
687 s16 idx_bandwidth = -1;
688 s16 idx_rate_sctn = -1;
689 s16 idx_channel = -1;
690 s8 pwr_lmt = MAX_POWER_INDEX;
691 struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
692 s8 limits[10] = {0}; u8 i = 0;
693
694 if (((adapter->registrypriv.reg_enable_tx_power_limit == 2) &&
695 (hal_data->EEPROMRegulatory != 1)) ||
696 (adapter->registrypriv.reg_enable_tx_power_limit == 0))
697 return MAX_POWER_INDEX;
698
699 switch (adapter->registrypriv.reg_pwr_tbl_sel) {
700 case 1:
701 idx_regulation = TXPWR_LMT_ETSI;
702 break;
703 case 2:
704 idx_regulation = TXPWR_LMT_MKK;
705 break;
706 case 3:
707 idx_regulation = TXPWR_LMT_FCC;
708 break;
709 case 4:
710 idx_regulation = TXPWR_LMT_WW;
711 break;
712 default:
713 idx_regulation = hal_data->Regulation2_4G;
714 break;
715 }
716
717 idx_bandwidth = get_bandwidth_idx(bandwidth);
718 idx_rate_sctn = get_rate_sctn_idx(data_rate);
719
720 /* workaround for wrong index combination to obtain tx power limit, */
721 /* OFDM only exists in BW 20M */
722 /* CCK table will only be given in BW 20M */
723 /* HT on 80M will reference to HT on 40M */
724 if (idx_rate_sctn == 0 || idx_rate_sctn == 1)
725 idx_bandwidth = 0;
726
727 channel = phy_GetChannelIndexOfTxPowerLimit(channel);
728
729 if (idx_regulation == -1 || idx_bandwidth == -1 ||
730 idx_rate_sctn == -1 || idx_channel == -1)
731 return MAX_POWER_INDEX;
732
733
734 for (i = 0; i < MAX_REGULATION_NUM; i++)
735 limits[i] = hal_data->TxPwrLimit_2_4G[i]
736 [idx_bandwidth]
737 [idx_rate_sctn]
738 [idx_channel]
739 [rf_path];
740
741 pwr_lmt = (idx_regulation == TXPWR_LMT_WW) ?
742 phy_GetWorldWideLimit(limits) :
743 hal_data->TxPwrLimit_2_4G[idx_regulation]
744 [idx_bandwidth]
745 [idx_rate_sctn]
746 [idx_channel]
747 [rf_path];
748
749 return pwr_lmt;
750 }
751
PHY_ConvertTxPowerLimitToPowerIndex(struct adapter * Adapter)752 void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter)
753 {
754 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
755 struct registry_priv *r = &Adapter->registrypriv;
756 u8 BW40PwrBasedBm2_4G = 0x2E;
757 u8 regulation, bw, channel, rateSection;
758 s8 tempValue = 0, tempPwrLmt = 0;
759 u8 rfPath = 0;
760
761 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
762 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
763 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {
764 for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {
765 tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A];
766
767 for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) {
768 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) {
769 if (rateSection == 2) /* HT 1T */
770 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, HT_MCS0_MCS7);
771 else if (rateSection == 1) /* OFDM */
772 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, OFDM);
773 else if (rateSection == 0) /* CCK */
774 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, CCK);
775 } else
776 BW40PwrBasedBm2_4G = r->reg_power_base * 2;
777
778 if (tempPwrLmt != MAX_POWER_INDEX) {
779 tempValue = tempPwrLmt - BW40PwrBasedBm2_4G;
780 pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue;
781 }
782 }
783 }
784 }
785 }
786 }
787 }
788
PHY_InitTxPowerLimit(struct adapter * Adapter)789 void PHY_InitTxPowerLimit(struct adapter *Adapter)
790 {
791 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
792 u8 i, j, k, l, m;
793
794 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
795 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
796 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
797 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
798 for (l = 0; l < MAX_RF_PATH_NUM; ++l)
799 pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX;
800 }
801 }
802
PHY_SetTxPowerLimit(struct adapter * Adapter,u8 * Regulation,u8 * Bandwidth,u8 * RateSection,u8 * RfPath,u8 * Channel,u8 * PowerLimit)803 void PHY_SetTxPowerLimit(
804 struct adapter *Adapter,
805 u8 *Regulation,
806 u8 *Bandwidth,
807 u8 *RateSection,
808 u8 *RfPath,
809 u8 *Channel,
810 u8 *PowerLimit
811 )
812 {
813 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
814 u8 regulation = 0, bandwidth = 0, rateSection = 0, channel;
815 s8 powerLimit = 0, prevPowerLimit, channelIndex;
816
817 GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel);
818 GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit);
819
820 powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit;
821
822 if (eqNByte(Regulation, (u8 *)("FCC"), 3))
823 regulation = 0;
824 else if (eqNByte(Regulation, (u8 *)("MKK"), 3))
825 regulation = 1;
826 else if (eqNByte(Regulation, (u8 *)("ETSI"), 4))
827 regulation = 2;
828 else if (eqNByte(Regulation, (u8 *)("WW13"), 4))
829 regulation = 3;
830
831 if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2))
832 rateSection = 0;
833 else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2))
834 rateSection = 1;
835 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2))
836 rateSection = 2;
837 else
838 return;
839
840 if (eqNByte(Bandwidth, (u8 *)("20M"), 3))
841 bandwidth = 0;
842 else if (eqNByte(Bandwidth, (u8 *)("40M"), 3))
843 bandwidth = 1;
844
845 channelIndex = phy_GetChannelIndexOfTxPowerLimit(channel);
846
847 if (channelIndex == -1)
848 return;
849
850 prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A];
851
852 if (powerLimit < prevPowerLimit)
853 pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit;
854 }
855
Hal_ChannelPlanToRegulation(struct adapter * Adapter,u16 ChannelPlan)856 void Hal_ChannelPlanToRegulation(struct adapter *Adapter, u16 ChannelPlan)
857 {
858 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
859 pHalData->Regulation2_4G = TXPWR_LMT_WW;
860
861 switch (ChannelPlan) {
862 case RT_CHANNEL_DOMAIN_WORLD_NULL:
863 pHalData->Regulation2_4G = TXPWR_LMT_WW;
864 break;
865 case RT_CHANNEL_DOMAIN_ETSI1_NULL:
866 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
867 break;
868 case RT_CHANNEL_DOMAIN_FCC1_NULL:
869 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
870 break;
871 case RT_CHANNEL_DOMAIN_MKK1_NULL:
872 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
873 break;
874 case RT_CHANNEL_DOMAIN_ETSI2_NULL:
875 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
876 break;
877 case RT_CHANNEL_DOMAIN_FCC1_FCC1:
878 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
879 break;
880 case RT_CHANNEL_DOMAIN_WORLD_ETSI1:
881 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
882 break;
883 case RT_CHANNEL_DOMAIN_MKK1_MKK1:
884 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
885 break;
886 case RT_CHANNEL_DOMAIN_WORLD_KCC1:
887 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
888 break;
889 case RT_CHANNEL_DOMAIN_WORLD_FCC2:
890 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
891 break;
892 case RT_CHANNEL_DOMAIN_WORLD_FCC3:
893 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
894 break;
895 case RT_CHANNEL_DOMAIN_WORLD_FCC4:
896 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
897 break;
898 case RT_CHANNEL_DOMAIN_WORLD_FCC5:
899 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
900 break;
901 case RT_CHANNEL_DOMAIN_WORLD_FCC6:
902 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
903 break;
904 case RT_CHANNEL_DOMAIN_FCC1_FCC7:
905 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
906 break;
907 case RT_CHANNEL_DOMAIN_WORLD_ETSI2:
908 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
909 break;
910 case RT_CHANNEL_DOMAIN_WORLD_ETSI3:
911 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
912 break;
913 case RT_CHANNEL_DOMAIN_MKK1_MKK2:
914 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
915 break;
916 case RT_CHANNEL_DOMAIN_MKK1_MKK3:
917 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
918 break;
919 case RT_CHANNEL_DOMAIN_FCC1_NCC1:
920 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
921 break;
922 case RT_CHANNEL_DOMAIN_FCC1_NCC2:
923 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
924 break;
925 case RT_CHANNEL_DOMAIN_GLOBAL_NULL:
926 pHalData->Regulation2_4G = TXPWR_LMT_WW;
927 break;
928 case RT_CHANNEL_DOMAIN_ETSI1_ETSI4:
929 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
930 break;
931 case RT_CHANNEL_DOMAIN_FCC1_FCC2:
932 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
933 break;
934 case RT_CHANNEL_DOMAIN_FCC1_NCC3:
935 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
936 break;
937 case RT_CHANNEL_DOMAIN_WORLD_ETSI5:
938 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
939 break;
940 case RT_CHANNEL_DOMAIN_FCC1_FCC8:
941 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
942 break;
943 case RT_CHANNEL_DOMAIN_WORLD_ETSI6:
944 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
945 break;
946 case RT_CHANNEL_DOMAIN_WORLD_ETSI7:
947 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
948 break;
949 case RT_CHANNEL_DOMAIN_WORLD_ETSI8:
950 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
951 break;
952 case RT_CHANNEL_DOMAIN_WORLD_ETSI9:
953 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
954 break;
955 case RT_CHANNEL_DOMAIN_WORLD_ETSI10:
956 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
957 break;
958 case RT_CHANNEL_DOMAIN_WORLD_ETSI11:
959 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
960 break;
961 case RT_CHANNEL_DOMAIN_FCC1_NCC4:
962 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
963 break;
964 case RT_CHANNEL_DOMAIN_WORLD_ETSI12:
965 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
966 break;
967 case RT_CHANNEL_DOMAIN_FCC1_FCC9:
968 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
969 break;
970 case RT_CHANNEL_DOMAIN_WORLD_ETSI13:
971 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
972 break;
973 case RT_CHANNEL_DOMAIN_FCC1_FCC10:
974 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
975 break;
976 case RT_CHANNEL_DOMAIN_REALTEK_DEFINE: /* Realtek Reserve */
977 pHalData->Regulation2_4G = TXPWR_LMT_WW;
978 break;
979 default:
980 break;
981 }
982 }
983