1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
3
4 #ifndef _HINIC3_NIC_IO_H_
5 #define _HINIC3_NIC_IO_H_
6
7 #include <linux/bitfield.h>
8
9 #include "hinic3_wq.h"
10
11 struct hinic3_nic_dev;
12
13 #define HINIC3_SQ_WQEBB_SHIFT 4
14 #define HINIC3_RQ_WQEBB_SHIFT 3
15 #define HINIC3_SQ_WQEBB_SIZE BIT(HINIC3_SQ_WQEBB_SHIFT)
16
17 /* ******************** RQ_CTRL ******************** */
18 enum hinic3_rq_wqe_type {
19 HINIC3_NORMAL_RQ_WQE = 1,
20 };
21
22 /* ******************** SQ_CTRL ******************** */
23 #define HINIC3_TX_MSS_DEFAULT 0x3E00
24 #define HINIC3_TX_MSS_MIN 0x50
25 #define HINIC3_MAX_SQ_SGE 18
26
27 struct hinic3_io_queue {
28 struct hinic3_wq wq;
29 u8 owner;
30 u16 q_id;
31 u16 msix_entry_idx;
32 u8 __iomem *db_addr;
33 u16 *cons_idx_addr;
34 } ____cacheline_aligned;
35
hinic3_get_sq_local_ci(const struct hinic3_io_queue * sq)36 static inline u16 hinic3_get_sq_local_ci(const struct hinic3_io_queue *sq)
37 {
38 const struct hinic3_wq *wq = &sq->wq;
39
40 return wq->cons_idx & wq->idx_mask;
41 }
42
hinic3_get_sq_local_pi(const struct hinic3_io_queue * sq)43 static inline u16 hinic3_get_sq_local_pi(const struct hinic3_io_queue *sq)
44 {
45 const struct hinic3_wq *wq = &sq->wq;
46
47 return wq->prod_idx & wq->idx_mask;
48 }
49
hinic3_get_sq_hw_ci(const struct hinic3_io_queue * sq)50 static inline u16 hinic3_get_sq_hw_ci(const struct hinic3_io_queue *sq)
51 {
52 const struct hinic3_wq *wq = &sq->wq;
53
54 return READ_ONCE(*sq->cons_idx_addr) & wq->idx_mask;
55 }
56
57 /* ******************** DB INFO ******************** */
58 #define DB_INFO_QID_MASK GENMASK(12, 0)
59 #define DB_INFO_CFLAG_MASK BIT(23)
60 #define DB_INFO_COS_MASK GENMASK(26, 24)
61 #define DB_INFO_TYPE_MASK GENMASK(31, 27)
62 #define DB_INFO_SET(val, member) \
63 FIELD_PREP(DB_INFO_##member##_MASK, val)
64
65 #define DB_PI_LOW_MASK 0xFFU
66 #define DB_PI_HIGH_MASK 0xFFU
67 #define DB_PI_HI_SHIFT 8
68 #define DB_PI_LOW(pi) ((pi) & DB_PI_LOW_MASK)
69 #define DB_PI_HIGH(pi) (((pi) >> DB_PI_HI_SHIFT) & DB_PI_HIGH_MASK)
70 #define DB_ADDR(q, pi) ((u64 __iomem *)((q)->db_addr) + DB_PI_LOW(pi))
71 #define DB_SRC_TYPE 1
72
73 /* CFLAG_DATA_PATH */
74 #define DB_CFLAG_DP_SQ 0
75 #define DB_CFLAG_DP_RQ 1
76
77 struct hinic3_nic_db {
78 u32 db_info;
79 u32 pi_hi;
80 };
81
hinic3_write_db(struct hinic3_io_queue * queue,int cos,u8 cflag,u16 pi)82 static inline void hinic3_write_db(struct hinic3_io_queue *queue, int cos,
83 u8 cflag, u16 pi)
84 {
85 struct hinic3_nic_db db;
86
87 db.db_info = DB_INFO_SET(DB_SRC_TYPE, TYPE) |
88 DB_INFO_SET(cflag, CFLAG) |
89 DB_INFO_SET(cos, COS) |
90 DB_INFO_SET(queue->q_id, QID);
91 db.pi_hi = DB_PI_HIGH(pi);
92
93 writeq(*((u64 *)&db), DB_ADDR(queue, pi));
94 }
95
96 struct hinic3_nic_io {
97 struct hinic3_io_queue *sq;
98 struct hinic3_io_queue *rq;
99
100 u16 num_qps;
101 u16 max_qps;
102
103 /* Base address for consumer index of all tx queues. Each queue is
104 * given a full cache line to hold its consumer index. HW updates
105 * current consumer index as it consumes tx WQEs.
106 */
107 void *ci_vaddr_base;
108 dma_addr_t ci_dma_base;
109
110 u8 __iomem *sqs_db_addr;
111 u8 __iomem *rqs_db_addr;
112
113 u16 rx_buf_len;
114 u64 feature_cap;
115 };
116
117 int hinic3_init_nic_io(struct hinic3_nic_dev *nic_dev);
118 void hinic3_free_nic_io(struct hinic3_nic_dev *nic_dev);
119
120 #endif
121