1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Copyright (c) 2024 Hisilicon Limited. */ 3 4 #ifndef DP_REG_H 5 #define DP_REG_H 6 7 #define HIBMC_DP_AUX_CMD_ADDR 0x50 8 9 #define HIBMC_DP_AUX_WR_DATA0 0x54 10 #define HIBMC_DP_AUX_WR_DATA1 0x58 11 #define HIBMC_DP_AUX_WR_DATA2 0x5c 12 #define HIBMC_DP_AUX_WR_DATA3 0x60 13 #define HIBMC_DP_AUX_RD_DATA0 0x64 14 15 #define HIBMC_DP_AUX_REQ 0x74 16 #define HIBMC_DP_CFG_AUX_REQ BIT(0) 17 #define HIBMC_DP_CFG_AUX_SYNC_LEN_SEL BIT(1) 18 #define HIBMC_DP_CFG_AUX_TIMER_TIMEOUT BIT(2) 19 #define HIBMC_DP_CFG_AUX_MIN_PULSE_NUM GENMASK(13, 9) 20 21 #define HIBMC_DP_AUX_STATUS 0x78 22 #define HIBMC_DP_CFG_AUX_TIMEOUT BIT(0) 23 #define HIBMC_DP_CFG_AUX_STATUS GENMASK(11, 4) 24 #define HIBMC_DP_CFG_AUX_READY_DATA_BYTE GENMASK(16, 12) 25 #define HIBMC_DP_CFG_AUX GENMASK(24, 17) 26 27 #define HIBMC_DP_PHYIF_CTRL0 0xa0 28 #define HIBMC_DP_CFG_SCRAMBLE_EN BIT(0) 29 #define HIBMC_DP_CFG_PAT_SEL GENMASK(7, 4) 30 #define HIBMC_DP_CFG_LANE_DATA_EN GENMASK(11, 8) 31 32 #define HIBMC_DP_VIDEO_CTRL 0x100 33 #define HIBMC_DP_CFG_STREAM_RGB_ENABLE BIT(1) 34 #define HIBMC_DP_CFG_STREAM_VIDEO_MAPPING GENMASK(5, 2) 35 #define HIBMC_DP_CFG_STREAM_FRAME_MODE BIT(6) 36 #define HIBMC_DP_CFG_STREAM_HSYNC_POLARITY BIT(7) 37 #define HIBMC_DP_CFG_STREAM_VSYNC_POLARITY BIT(8) 38 39 #define HIBMC_DP_VIDEO_CONFIG0 0x104 40 #define HIBMC_DP_CFG_STREAM_HACTIVE GENMASK(31, 16) 41 #define HIBMC_DP_CFG_STREAM_HBLANK GENMASK(15, 0) 42 43 #define HIBMC_DP_VIDEO_CONFIG1 0x108 44 #define HIBMC_DP_CFG_STREAM_VACTIVE GENMASK(31, 16) 45 #define HIBMC_DP_CFG_STREAM_VBLANK GENMASK(15, 0) 46 47 #define HIBMC_DP_VIDEO_CONFIG2 0x10c 48 #define HIBMC_DP_CFG_STREAM_HSYNC_WIDTH GENMASK(15, 0) 49 50 #define HIBMC_DP_VIDEO_CONFIG3 0x110 51 #define HIBMC_DP_CFG_STREAM_VSYNC_WIDTH GENMASK(15, 0) 52 #define HIBMC_DP_CFG_STREAM_VFRONT_PORCH GENMASK(31, 16) 53 54 #define HIBMC_DP_VIDEO_PACKET 0x114 55 #define HIBMC_DP_CFG_STREAM_TU_SYMBOL_SIZE GENMASK(5, 0) 56 #define HIBMC_DP_CFG_STREAM_TU_SYMBOL_FRAC_SIZE GENMASK(9, 6) 57 #define HIBMC_DP_CFG_STREAM_SYNC_CALIBRATION GENMASK(31, 20) 58 59 #define HIBMC_DP_VIDEO_MSA0 0x118 60 #define HIBMC_DP_CFG_STREAM_VSTART GENMASK(31, 16) 61 #define HIBMC_DP_CFG_STREAM_HSTART GENMASK(15, 0) 62 63 #define HIBMC_DP_VIDEO_MSA1 0x11c 64 #define HIBMC_DP_VIDEO_MSA2 0x120 65 66 #define HIBMC_DP_VIDEO_HORIZONTAL_SIZE 0X124 67 #define HIBMC_DP_CFG_STREAM_HTOTAL_SIZE GENMASK(31, 16) 68 #define HIBMC_DP_CFG_STREAM_HBLANK_SIZE GENMASK(15, 0) 69 70 #define HIBMC_DP_COLOR_BAR_CTRL 0x260 71 #define HIBMC_DP_COLOR_BAR_CTRL1 0x264 72 73 #define HIBMC_DP_TIMING_GEN_CONFIG0 0x26c 74 #define HIBMC_DP_CFG_TIMING_GEN0_HACTIVE GENMASK(31, 16) 75 #define HIBMC_DP_CFG_TIMING_GEN0_HBLANK GENMASK(15, 0) 76 77 #define HIBMC_DP_TIMING_GEN_CONFIG2 0x274 78 #define HIBMC_DP_CFG_TIMING_GEN0_VACTIVE GENMASK(31, 16) 79 #define HIBMC_DP_CFG_TIMING_GEN0_VBLANK GENMASK(15, 0) 80 81 #define HIBMC_DP_TIMING_GEN_CONFIG3 0x278 82 #define HIBMC_DP_CFG_TIMING_GEN0_VFRONT_PORCH GENMASK(31, 16) 83 84 #define HIBMC_DP_HDCP_CFG 0x600 85 86 #define HIBMC_DP_DPTX_RST_CTRL 0x700 87 #define HIBMC_DP_CFG_AUX_RST_N BIT(4) 88 89 #define HIBMC_DP_DPTX_CLK_CTRL 0x704 90 91 #define HIBMC_DP_DPTX_GCTL0 0x708 92 #define HIBMC_DP_CFG_PHY_LANE_NUM GENMASK(2, 1) 93 94 #define HIBMC_DP_INTR_ENABLE 0x720 95 #define HIBMC_DP_INTR_ORIGINAL_STATUS 0x728 96 97 #define HIBMC_DP_TIMING_MODEL_CTRL 0x884 98 #define HIBMC_DP_CFG_PIXEL_NUM_TIMING_MODE_SEL1 GENMASK(31, 16) 99 100 #define HIBMC_DP_TIMING_SYNC_CTRL 0xFF0 101 102 #define HIBMC_DP_INTSTAT 0x1e0724 103 #define HIBMC_DP_INTCLR 0x1e0728 104 105 /* dp serdes reg */ 106 #define HIBMC_DP_HOST_OFFSET 0x10000 107 #define HIBMC_DP_LANE0_RATE_OFFSET 0x4 108 #define HIBMC_DP_LANE1_RATE_OFFSET 0xc 109 #define HIBMC_DP_LANE_STATUS_OFFSET 0x10 110 #define HIBMC_DP_PMA_LANE0_OFFSET 0x18 111 #define HIBMC_DP_PMA_LANE1_OFFSET 0x1c 112 #define HIBMC_DP_HOST_SERDES_CTRL 0x1f001c 113 #define HIBMC_DP_PMA_TXDEEMPH GENMASK(18, 1) 114 #define DP_SERDES_DONE 0x3 115 116 /* dp serdes TX-Deempth Configuration */ 117 #define DP_SERDES_VOL0_PRE0 0x280 118 #define DP_SERDES_VOL0_PRE1 0x2300 119 #define DP_SERDES_VOL0_PRE2 0x53c0 120 #define DP_SERDES_VOL0_PRE3 0x8400 121 #define DP_SERDES_VOL1_PRE0 0x380 122 #define DP_SERDES_VOL1_PRE1 0x3440 123 #define DP_SERDES_VOL1_PRE2 0x6480 124 #define DP_SERDES_VOL2_PRE0 0x4c1 125 #define DP_SERDES_VOL2_PRE1 0x4500 126 #define DP_SERDES_VOL3_PRE0 0x600 127 #define DP_SERDES_BW_8_1 0x3 128 #define DP_SERDES_BW_5_4 0x2 129 #define DP_SERDES_BW_2_7 0x1 130 #define DP_SERDES_BW_1_62 0x0 131 132 #endif 133