1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 AmLogic, Inc. 4 * Michael Turquette <mturquette@baylibre.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/init.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/platform_device.h> 11 #include <linux/module.h> 12 13 #include "clk-regmap.h" 14 #include "clk-pll.h" 15 #include "clk-mpll.h" 16 #include "meson-eeclk.h" 17 #include "vid-pll-div.h" 18 19 #include <dt-bindings/clock/gxbb-clkc.h> 20 21 #define SCR 0x2c 22 #define TIMEOUT_VALUE 0x3c 23 24 #define HHI_GP0_PLL_CNTL 0x40 25 #define HHI_GP0_PLL_CNTL2 0x44 26 #define HHI_GP0_PLL_CNTL3 0x48 27 #define HHI_GP0_PLL_CNTL4 0x4c 28 #define HHI_GP0_PLL_CNTL5 0x50 29 #define HHI_GP0_PLL_CNTL1 0x58 30 31 #define HHI_XTAL_DIVN_CNTL 0xbc 32 #define HHI_TIMER90K 0xec 33 34 #define HHI_MEM_PD_REG0 0x100 35 #define HHI_MEM_PD_REG1 0x104 36 #define HHI_VPU_MEM_PD_REG1 0x108 37 #define HHI_VIID_CLK_DIV 0x128 38 #define HHI_VIID_CLK_CNTL 0x12c 39 40 #define HHI_GCLK_MPEG0 0x140 41 #define HHI_GCLK_MPEG1 0x144 42 #define HHI_GCLK_MPEG2 0x148 43 #define HHI_GCLK_OTHER 0x150 44 #define HHI_GCLK_AO 0x154 45 #define HHI_SYS_OSCIN_CNTL 0x158 46 #define HHI_SYS_CPU_CLK_CNTL1 0x15c 47 #define HHI_SYS_CPU_RESET_CNTL 0x160 48 #define HHI_VID_CLK_DIV 0x164 49 50 #define HHI_MPEG_CLK_CNTL 0x174 51 #define HHI_AUD_CLK_CNTL 0x178 52 #define HHI_VID_CLK_CNTL 0x17c 53 #define HHI_AUD_CLK_CNTL2 0x190 54 #define HHI_VID_CLK_CNTL2 0x194 55 #define HHI_SYS_CPU_CLK_CNTL0 0x19c 56 #define HHI_VID_PLL_CLK_DIV 0x1a0 57 #define HHI_AUD_CLK_CNTL3 0x1a4 58 #define HHI_MALI_CLK_CNTL 0x1b0 59 #define HHI_VPU_CLK_CNTL 0x1bc 60 61 #define HHI_HDMI_CLK_CNTL 0x1cc 62 #define HHI_VDEC_CLK_CNTL 0x1e0 63 #define HHI_VDEC2_CLK_CNTL 0x1e4 64 #define HHI_VDEC3_CLK_CNTL 0x1e8 65 #define HHI_VDEC4_CLK_CNTL 0x1ec 66 #define HHI_HDCP22_CLK_CNTL 0x1f0 67 #define HHI_VAPBCLK_CNTL 0x1f4 68 69 #define HHI_VPU_CLKB_CNTL 0x20c 70 #define HHI_USB_CLK_CNTL 0x220 71 #define HHI_32K_CLK_CNTL 0x224 72 #define HHI_GEN_CLK_CNTL 0x228 73 74 #define HHI_PCM_CLK_CNTL 0x258 75 #define HHI_NAND_CLK_CNTL 0x25c 76 #define HHI_SD_EMMC_CLK_CNTL 0x264 77 78 #define HHI_MPLL_CNTL 0x280 79 #define HHI_MPLL_CNTL2 0x284 80 #define HHI_MPLL_CNTL3 0x288 81 #define HHI_MPLL_CNTL4 0x28c 82 #define HHI_MPLL_CNTL5 0x290 83 #define HHI_MPLL_CNTL6 0x294 84 #define HHI_MPLL_CNTL7 0x298 85 #define HHI_MPLL_CNTL8 0x29c 86 #define HHI_MPLL_CNTL9 0x2a0 87 #define HHI_MPLL_CNTL10 0x2a4 88 89 #define HHI_MPLL3_CNTL0 0x2e0 90 #define HHI_MPLL3_CNTL1 0x2e4 91 #define HHI_VDAC_CNTL0 0x2f4 92 #define HHI_VDAC_CNTL1 0x2f8 93 94 #define HHI_SYS_PLL_CNTL 0x300 95 #define HHI_SYS_PLL_CNTL2 0x304 96 #define HHI_SYS_PLL_CNTL3 0x308 97 #define HHI_SYS_PLL_CNTL4 0x30c 98 #define HHI_SYS_PLL_CNTL5 0x310 99 #define HHI_DPLL_TOP_I 0x318 100 #define HHI_DPLL_TOP2_I 0x31c 101 #define HHI_HDMI_PLL_CNTL 0x320 102 #define HHI_HDMI_PLL_CNTL2 0x324 103 #define HHI_HDMI_PLL_CNTL3 0x328 104 #define HHI_HDMI_PLL_CNTL4 0x32c 105 #define HHI_HDMI_PLL_CNTL5 0x330 106 #define HHI_HDMI_PLL_CNTL6 0x334 107 #define HHI_HDMI_PLL_CNTL_I 0x338 108 #define HHI_HDMI_PLL_CNTL7 0x33c 109 110 #define HHI_HDMI_PHY_CNTL0 0x3a0 111 #define HHI_HDMI_PHY_CNTL1 0x3a4 112 #define HHI_HDMI_PHY_CNTL2 0x3a8 113 #define HHI_HDMI_PHY_CNTL3 0x3ac 114 115 #define HHI_VID_LOCK_CLK_CNTL 0x3c8 116 #define HHI_BT656_CLK_CNTL 0x3d4 117 #define HHI_SAR_CLK_CNTL 0x3d8 118 119 static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 120 PLL_PARAMS(32, 1), 121 PLL_PARAMS(33, 1), 122 PLL_PARAMS(34, 1), 123 PLL_PARAMS(35, 1), 124 PLL_PARAMS(36, 1), 125 PLL_PARAMS(37, 1), 126 PLL_PARAMS(38, 1), 127 PLL_PARAMS(39, 1), 128 PLL_PARAMS(40, 1), 129 PLL_PARAMS(41, 1), 130 PLL_PARAMS(42, 1), 131 PLL_PARAMS(43, 1), 132 PLL_PARAMS(44, 1), 133 PLL_PARAMS(45, 1), 134 PLL_PARAMS(46, 1), 135 PLL_PARAMS(47, 1), 136 PLL_PARAMS(48, 1), 137 PLL_PARAMS(49, 1), 138 PLL_PARAMS(50, 1), 139 PLL_PARAMS(51, 1), 140 PLL_PARAMS(52, 1), 141 PLL_PARAMS(53, 1), 142 PLL_PARAMS(54, 1), 143 PLL_PARAMS(55, 1), 144 PLL_PARAMS(56, 1), 145 PLL_PARAMS(57, 1), 146 PLL_PARAMS(58, 1), 147 PLL_PARAMS(59, 1), 148 PLL_PARAMS(60, 1), 149 PLL_PARAMS(61, 1), 150 PLL_PARAMS(62, 1), 151 { /* sentinel */ }, 152 }; 153 154 static const struct pll_params_table gxl_gp0_pll_params_table[] = { 155 PLL_PARAMS(42, 1), 156 PLL_PARAMS(43, 1), 157 PLL_PARAMS(44, 1), 158 PLL_PARAMS(45, 1), 159 PLL_PARAMS(46, 1), 160 PLL_PARAMS(47, 1), 161 PLL_PARAMS(48, 1), 162 PLL_PARAMS(49, 1), 163 PLL_PARAMS(50, 1), 164 PLL_PARAMS(51, 1), 165 PLL_PARAMS(52, 1), 166 PLL_PARAMS(53, 1), 167 PLL_PARAMS(54, 1), 168 PLL_PARAMS(55, 1), 169 PLL_PARAMS(56, 1), 170 PLL_PARAMS(57, 1), 171 PLL_PARAMS(58, 1), 172 PLL_PARAMS(59, 1), 173 PLL_PARAMS(60, 1), 174 PLL_PARAMS(61, 1), 175 PLL_PARAMS(62, 1), 176 PLL_PARAMS(63, 1), 177 PLL_PARAMS(64, 1), 178 PLL_PARAMS(65, 1), 179 PLL_PARAMS(66, 1), 180 { /* sentinel */ }, 181 }; 182 183 static struct clk_regmap gxbb_fixed_pll_dco = { 184 .data = &(struct meson_clk_pll_data){ 185 .en = { 186 .reg_off = HHI_MPLL_CNTL, 187 .shift = 30, 188 .width = 1, 189 }, 190 .m = { 191 .reg_off = HHI_MPLL_CNTL, 192 .shift = 0, 193 .width = 9, 194 }, 195 .n = { 196 .reg_off = HHI_MPLL_CNTL, 197 .shift = 9, 198 .width = 5, 199 }, 200 .frac = { 201 .reg_off = HHI_MPLL_CNTL2, 202 .shift = 0, 203 .width = 12, 204 }, 205 .l = { 206 .reg_off = HHI_MPLL_CNTL, 207 .shift = 31, 208 .width = 1, 209 }, 210 .rst = { 211 .reg_off = HHI_MPLL_CNTL, 212 .shift = 29, 213 .width = 1, 214 }, 215 }, 216 .hw.init = &(struct clk_init_data){ 217 .name = "fixed_pll_dco", 218 .ops = &meson_clk_pll_ro_ops, 219 .parent_data = &(const struct clk_parent_data) { 220 .fw_name = "xtal", 221 }, 222 .num_parents = 1, 223 }, 224 }; 225 226 static struct clk_regmap gxbb_fixed_pll = { 227 .data = &(struct clk_regmap_div_data){ 228 .offset = HHI_MPLL_CNTL, 229 .shift = 16, 230 .width = 2, 231 .flags = CLK_DIVIDER_POWER_OF_TWO, 232 }, 233 .hw.init = &(struct clk_init_data){ 234 .name = "fixed_pll", 235 .ops = &clk_regmap_divider_ro_ops, 236 .parent_hws = (const struct clk_hw *[]) { 237 &gxbb_fixed_pll_dco.hw 238 }, 239 .num_parents = 1, 240 /* 241 * This clock won't ever change at runtime so 242 * CLK_SET_RATE_PARENT is not required 243 */ 244 }, 245 }; 246 247 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 248 .mult = 2, 249 .div = 1, 250 .hw.init = &(struct clk_init_data){ 251 .name = "hdmi_pll_pre_mult", 252 .ops = &clk_fixed_factor_ops, 253 .parent_data = &(const struct clk_parent_data) { 254 .fw_name = "xtal", 255 }, 256 .num_parents = 1, 257 }, 258 }; 259 260 static struct clk_regmap gxbb_hdmi_pll_dco = { 261 .data = &(struct meson_clk_pll_data){ 262 .en = { 263 .reg_off = HHI_HDMI_PLL_CNTL, 264 .shift = 30, 265 .width = 1, 266 }, 267 .m = { 268 .reg_off = HHI_HDMI_PLL_CNTL, 269 .shift = 0, 270 .width = 9, 271 }, 272 .n = { 273 .reg_off = HHI_HDMI_PLL_CNTL, 274 .shift = 9, 275 .width = 5, 276 }, 277 .frac = { 278 .reg_off = HHI_HDMI_PLL_CNTL2, 279 .shift = 0, 280 .width = 12, 281 }, 282 .l = { 283 .reg_off = HHI_HDMI_PLL_CNTL, 284 .shift = 31, 285 .width = 1, 286 }, 287 .rst = { 288 .reg_off = HHI_HDMI_PLL_CNTL, 289 .shift = 28, 290 .width = 1, 291 }, 292 }, 293 .hw.init = &(struct clk_init_data){ 294 .name = "hdmi_pll_dco", 295 .ops = &meson_clk_pll_ro_ops, 296 .parent_hws = (const struct clk_hw *[]) { 297 &gxbb_hdmi_pll_pre_mult.hw 298 }, 299 .num_parents = 1, 300 /* 301 * Display directly handle hdmi pll registers ATM, we need 302 * NOCACHE to keep our view of the clock as accurate as possible 303 */ 304 .flags = CLK_GET_RATE_NOCACHE, 305 }, 306 }; 307 308 static struct clk_regmap gxl_hdmi_pll_dco = { 309 .data = &(struct meson_clk_pll_data){ 310 .en = { 311 .reg_off = HHI_HDMI_PLL_CNTL, 312 .shift = 30, 313 .width = 1, 314 }, 315 .m = { 316 .reg_off = HHI_HDMI_PLL_CNTL, 317 .shift = 0, 318 .width = 9, 319 }, 320 .n = { 321 .reg_off = HHI_HDMI_PLL_CNTL, 322 .shift = 9, 323 .width = 5, 324 }, 325 /* 326 * On gxl, there is a register shift due to 327 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 328 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB 329 * instead which is defined at the same offset. 330 */ 331 .frac = { 332 .reg_off = HHI_HDMI_PLL_CNTL2, 333 .shift = 0, 334 .width = 10, 335 }, 336 .l = { 337 .reg_off = HHI_HDMI_PLL_CNTL, 338 .shift = 31, 339 .width = 1, 340 }, 341 .rst = { 342 .reg_off = HHI_HDMI_PLL_CNTL, 343 .shift = 28, 344 .width = 1, 345 }, 346 }, 347 .hw.init = &(struct clk_init_data){ 348 .name = "hdmi_pll_dco", 349 .ops = &meson_clk_pll_ro_ops, 350 .parent_data = &(const struct clk_parent_data) { 351 .fw_name = "xtal", 352 }, 353 .num_parents = 1, 354 /* 355 * Display directly handle hdmi pll registers ATM, we need 356 * NOCACHE to keep our view of the clock as accurate as possible 357 */ 358 .flags = CLK_GET_RATE_NOCACHE, 359 }, 360 }; 361 362 static struct clk_regmap gxbb_hdmi_pll_od = { 363 .data = &(struct clk_regmap_div_data){ 364 .offset = HHI_HDMI_PLL_CNTL2, 365 .shift = 16, 366 .width = 2, 367 .flags = CLK_DIVIDER_POWER_OF_TWO, 368 }, 369 .hw.init = &(struct clk_init_data){ 370 .name = "hdmi_pll_od", 371 .ops = &clk_regmap_divider_ro_ops, 372 .parent_hws = (const struct clk_hw *[]) { 373 &gxbb_hdmi_pll_dco.hw 374 }, 375 .num_parents = 1, 376 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 377 }, 378 }; 379 380 static struct clk_regmap gxbb_hdmi_pll_od2 = { 381 .data = &(struct clk_regmap_div_data){ 382 .offset = HHI_HDMI_PLL_CNTL2, 383 .shift = 22, 384 .width = 2, 385 .flags = CLK_DIVIDER_POWER_OF_TWO, 386 }, 387 .hw.init = &(struct clk_init_data){ 388 .name = "hdmi_pll_od2", 389 .ops = &clk_regmap_divider_ro_ops, 390 .parent_hws = (const struct clk_hw *[]) { 391 &gxbb_hdmi_pll_od.hw 392 }, 393 .num_parents = 1, 394 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 395 }, 396 }; 397 398 static struct clk_regmap gxbb_hdmi_pll = { 399 .data = &(struct clk_regmap_div_data){ 400 .offset = HHI_HDMI_PLL_CNTL2, 401 .shift = 18, 402 .width = 2, 403 .flags = CLK_DIVIDER_POWER_OF_TWO, 404 }, 405 .hw.init = &(struct clk_init_data){ 406 .name = "hdmi_pll", 407 .ops = &clk_regmap_divider_ro_ops, 408 .parent_hws = (const struct clk_hw *[]) { 409 &gxbb_hdmi_pll_od2.hw 410 }, 411 .num_parents = 1, 412 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 413 }, 414 }; 415 416 static struct clk_regmap gxl_hdmi_pll_od = { 417 .data = &(struct clk_regmap_div_data){ 418 .offset = HHI_HDMI_PLL_CNTL + 8, 419 .shift = 21, 420 .width = 2, 421 .flags = CLK_DIVIDER_POWER_OF_TWO, 422 }, 423 .hw.init = &(struct clk_init_data){ 424 .name = "hdmi_pll_od", 425 .ops = &clk_regmap_divider_ro_ops, 426 .parent_hws = (const struct clk_hw *[]) { 427 &gxl_hdmi_pll_dco.hw 428 }, 429 .num_parents = 1, 430 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 431 }, 432 }; 433 434 static struct clk_regmap gxl_hdmi_pll_od2 = { 435 .data = &(struct clk_regmap_div_data){ 436 .offset = HHI_HDMI_PLL_CNTL + 8, 437 .shift = 23, 438 .width = 2, 439 .flags = CLK_DIVIDER_POWER_OF_TWO, 440 }, 441 .hw.init = &(struct clk_init_data){ 442 .name = "hdmi_pll_od2", 443 .ops = &clk_regmap_divider_ro_ops, 444 .parent_hws = (const struct clk_hw *[]) { 445 &gxl_hdmi_pll_od.hw 446 }, 447 .num_parents = 1, 448 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 449 }, 450 }; 451 452 static struct clk_regmap gxl_hdmi_pll = { 453 .data = &(struct clk_regmap_div_data){ 454 .offset = HHI_HDMI_PLL_CNTL + 8, 455 .shift = 19, 456 .width = 2, 457 .flags = CLK_DIVIDER_POWER_OF_TWO, 458 }, 459 .hw.init = &(struct clk_init_data){ 460 .name = "hdmi_pll", 461 .ops = &clk_regmap_divider_ro_ops, 462 .parent_hws = (const struct clk_hw *[]) { 463 &gxl_hdmi_pll_od2.hw 464 }, 465 .num_parents = 1, 466 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 467 }, 468 }; 469 470 static struct clk_regmap gxbb_sys_pll_dco = { 471 .data = &(struct meson_clk_pll_data){ 472 .en = { 473 .reg_off = HHI_SYS_PLL_CNTL, 474 .shift = 30, 475 .width = 1, 476 }, 477 .m = { 478 .reg_off = HHI_SYS_PLL_CNTL, 479 .shift = 0, 480 .width = 9, 481 }, 482 .n = { 483 .reg_off = HHI_SYS_PLL_CNTL, 484 .shift = 9, 485 .width = 5, 486 }, 487 .l = { 488 .reg_off = HHI_SYS_PLL_CNTL, 489 .shift = 31, 490 .width = 1, 491 }, 492 .rst = { 493 .reg_off = HHI_SYS_PLL_CNTL, 494 .shift = 29, 495 .width = 1, 496 }, 497 }, 498 .hw.init = &(struct clk_init_data){ 499 .name = "sys_pll_dco", 500 .ops = &meson_clk_pll_ro_ops, 501 .parent_data = &(const struct clk_parent_data) { 502 .fw_name = "xtal", 503 }, 504 .num_parents = 1, 505 }, 506 }; 507 508 static struct clk_regmap gxbb_sys_pll = { 509 .data = &(struct clk_regmap_div_data){ 510 .offset = HHI_SYS_PLL_CNTL, 511 .shift = 10, 512 .width = 2, 513 .flags = CLK_DIVIDER_POWER_OF_TWO, 514 }, 515 .hw.init = &(struct clk_init_data){ 516 .name = "sys_pll", 517 .ops = &clk_regmap_divider_ro_ops, 518 .parent_hws = (const struct clk_hw *[]) { 519 &gxbb_sys_pll_dco.hw 520 }, 521 .num_parents = 1, 522 .flags = CLK_SET_RATE_PARENT, 523 }, 524 }; 525 526 static const struct reg_sequence gxbb_gp0_init_regs[] = { 527 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 528 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 529 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 530 }; 531 532 static struct clk_regmap gxbb_gp0_pll_dco = { 533 .data = &(struct meson_clk_pll_data){ 534 .en = { 535 .reg_off = HHI_GP0_PLL_CNTL, 536 .shift = 30, 537 .width = 1, 538 }, 539 .m = { 540 .reg_off = HHI_GP0_PLL_CNTL, 541 .shift = 0, 542 .width = 9, 543 }, 544 .n = { 545 .reg_off = HHI_GP0_PLL_CNTL, 546 .shift = 9, 547 .width = 5, 548 }, 549 .l = { 550 .reg_off = HHI_GP0_PLL_CNTL, 551 .shift = 31, 552 .width = 1, 553 }, 554 .rst = { 555 .reg_off = HHI_GP0_PLL_CNTL, 556 .shift = 29, 557 .width = 1, 558 }, 559 .table = gxbb_gp0_pll_params_table, 560 .init_regs = gxbb_gp0_init_regs, 561 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), 562 }, 563 .hw.init = &(struct clk_init_data){ 564 .name = "gp0_pll_dco", 565 .ops = &meson_clk_pll_ops, 566 .parent_data = &(const struct clk_parent_data) { 567 .fw_name = "xtal", 568 }, 569 .num_parents = 1, 570 }, 571 }; 572 573 static const struct reg_sequence gxl_gp0_init_regs[] = { 574 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 575 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 576 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 577 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 578 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 579 }; 580 581 static struct clk_regmap gxl_gp0_pll_dco = { 582 .data = &(struct meson_clk_pll_data){ 583 .en = { 584 .reg_off = HHI_GP0_PLL_CNTL, 585 .shift = 30, 586 .width = 1, 587 }, 588 .m = { 589 .reg_off = HHI_GP0_PLL_CNTL, 590 .shift = 0, 591 .width = 9, 592 }, 593 .n = { 594 .reg_off = HHI_GP0_PLL_CNTL, 595 .shift = 9, 596 .width = 5, 597 }, 598 .frac = { 599 .reg_off = HHI_GP0_PLL_CNTL1, 600 .shift = 0, 601 .width = 10, 602 }, 603 .l = { 604 .reg_off = HHI_GP0_PLL_CNTL, 605 .shift = 31, 606 .width = 1, 607 }, 608 .rst = { 609 .reg_off = HHI_GP0_PLL_CNTL, 610 .shift = 29, 611 .width = 1, 612 }, 613 .table = gxl_gp0_pll_params_table, 614 .init_regs = gxl_gp0_init_regs, 615 .init_count = ARRAY_SIZE(gxl_gp0_init_regs), 616 }, 617 .hw.init = &(struct clk_init_data){ 618 .name = "gp0_pll_dco", 619 .ops = &meson_clk_pll_ops, 620 .parent_data = &(const struct clk_parent_data) { 621 .fw_name = "xtal", 622 }, 623 .num_parents = 1, 624 }, 625 }; 626 627 static struct clk_regmap gxbb_gp0_pll = { 628 .data = &(struct clk_regmap_div_data){ 629 .offset = HHI_GP0_PLL_CNTL, 630 .shift = 16, 631 .width = 2, 632 .flags = CLK_DIVIDER_POWER_OF_TWO, 633 }, 634 .hw.init = &(struct clk_init_data){ 635 .name = "gp0_pll", 636 .ops = &clk_regmap_divider_ops, 637 .parent_data = &(const struct clk_parent_data) { 638 /* 639 * Note: 640 * GXL and GXBB have different gp0_pll_dco (with 641 * different struct clk_hw). We fallback to the global 642 * naming string mechanism so gp0_pll picks up the 643 * appropriate one. 644 */ 645 .name = "gp0_pll_dco", 646 .index = -1, 647 }, 648 .num_parents = 1, 649 .flags = CLK_SET_RATE_PARENT, 650 }, 651 }; 652 653 static struct clk_fixed_factor gxbb_fclk_div2_div = { 654 .mult = 1, 655 .div = 2, 656 .hw.init = &(struct clk_init_data){ 657 .name = "fclk_div2_div", 658 .ops = &clk_fixed_factor_ops, 659 .parent_hws = (const struct clk_hw *[]) { 660 &gxbb_fixed_pll.hw 661 }, 662 .num_parents = 1, 663 }, 664 }; 665 666 static struct clk_regmap gxbb_fclk_div2 = { 667 .data = &(struct clk_regmap_gate_data){ 668 .offset = HHI_MPLL_CNTL6, 669 .bit_idx = 27, 670 }, 671 .hw.init = &(struct clk_init_data){ 672 .name = "fclk_div2", 673 .ops = &clk_regmap_gate_ops, 674 .parent_hws = (const struct clk_hw *[]) { 675 &gxbb_fclk_div2_div.hw 676 }, 677 .num_parents = 1, 678 .flags = CLK_IS_CRITICAL, 679 }, 680 }; 681 682 static struct clk_fixed_factor gxbb_fclk_div3_div = { 683 .mult = 1, 684 .div = 3, 685 .hw.init = &(struct clk_init_data){ 686 .name = "fclk_div3_div", 687 .ops = &clk_fixed_factor_ops, 688 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 689 .num_parents = 1, 690 }, 691 }; 692 693 static struct clk_regmap gxbb_fclk_div3 = { 694 .data = &(struct clk_regmap_gate_data){ 695 .offset = HHI_MPLL_CNTL6, 696 .bit_idx = 28, 697 }, 698 .hw.init = &(struct clk_init_data){ 699 .name = "fclk_div3", 700 .ops = &clk_regmap_gate_ops, 701 .parent_hws = (const struct clk_hw *[]) { 702 &gxbb_fclk_div3_div.hw 703 }, 704 .num_parents = 1, 705 /* 706 * FIXME: 707 * This clock, as fdiv2, is used by the SCPI FW and is required 708 * by the platform to operate correctly. 709 * Until the following condition are met, we need this clock to 710 * be marked as critical: 711 * a) The SCPI generic driver claims and enable all the clocks 712 * it needs 713 * b) CCF has a clock hand-off mechanism to make the sure the 714 * clock stays on until the proper driver comes along 715 */ 716 .flags = CLK_IS_CRITICAL, 717 }, 718 }; 719 720 static struct clk_fixed_factor gxbb_fclk_div4_div = { 721 .mult = 1, 722 .div = 4, 723 .hw.init = &(struct clk_init_data){ 724 .name = "fclk_div4_div", 725 .ops = &clk_fixed_factor_ops, 726 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 727 .num_parents = 1, 728 }, 729 }; 730 731 static struct clk_regmap gxbb_fclk_div4 = { 732 .data = &(struct clk_regmap_gate_data){ 733 .offset = HHI_MPLL_CNTL6, 734 .bit_idx = 29, 735 }, 736 .hw.init = &(struct clk_init_data){ 737 .name = "fclk_div4", 738 .ops = &clk_regmap_gate_ops, 739 .parent_hws = (const struct clk_hw *[]) { 740 &gxbb_fclk_div4_div.hw 741 }, 742 .num_parents = 1, 743 }, 744 }; 745 746 static struct clk_fixed_factor gxbb_fclk_div5_div = { 747 .mult = 1, 748 .div = 5, 749 .hw.init = &(struct clk_init_data){ 750 .name = "fclk_div5_div", 751 .ops = &clk_fixed_factor_ops, 752 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 753 .num_parents = 1, 754 }, 755 }; 756 757 static struct clk_regmap gxbb_fclk_div5 = { 758 .data = &(struct clk_regmap_gate_data){ 759 .offset = HHI_MPLL_CNTL6, 760 .bit_idx = 30, 761 }, 762 .hw.init = &(struct clk_init_data){ 763 .name = "fclk_div5", 764 .ops = &clk_regmap_gate_ops, 765 .parent_hws = (const struct clk_hw *[]) { 766 &gxbb_fclk_div5_div.hw 767 }, 768 .num_parents = 1, 769 }, 770 }; 771 772 static struct clk_fixed_factor gxbb_fclk_div7_div = { 773 .mult = 1, 774 .div = 7, 775 .hw.init = &(struct clk_init_data){ 776 .name = "fclk_div7_div", 777 .ops = &clk_fixed_factor_ops, 778 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 779 .num_parents = 1, 780 }, 781 }; 782 783 static struct clk_regmap gxbb_fclk_div7 = { 784 .data = &(struct clk_regmap_gate_data){ 785 .offset = HHI_MPLL_CNTL6, 786 .bit_idx = 31, 787 }, 788 .hw.init = &(struct clk_init_data){ 789 .name = "fclk_div7", 790 .ops = &clk_regmap_gate_ops, 791 .parent_hws = (const struct clk_hw *[]) { 792 &gxbb_fclk_div7_div.hw 793 }, 794 .num_parents = 1, 795 }, 796 }; 797 798 static struct clk_regmap gxbb_mpll_prediv = { 799 .data = &(struct clk_regmap_div_data){ 800 .offset = HHI_MPLL_CNTL5, 801 .shift = 12, 802 .width = 1, 803 }, 804 .hw.init = &(struct clk_init_data){ 805 .name = "mpll_prediv", 806 .ops = &clk_regmap_divider_ro_ops, 807 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 808 .num_parents = 1, 809 }, 810 }; 811 812 static struct clk_regmap gxbb_mpll0_div = { 813 .data = &(struct meson_clk_mpll_data){ 814 .sdm = { 815 .reg_off = HHI_MPLL_CNTL7, 816 .shift = 0, 817 .width = 14, 818 }, 819 .sdm_en = { 820 .reg_off = HHI_MPLL_CNTL, 821 .shift = 25, 822 .width = 1, 823 }, 824 .n2 = { 825 .reg_off = HHI_MPLL_CNTL7, 826 .shift = 16, 827 .width = 9, 828 }, 829 }, 830 .hw.init = &(struct clk_init_data){ 831 .name = "mpll0_div", 832 .ops = &meson_clk_mpll_ops, 833 .parent_hws = (const struct clk_hw *[]) { 834 &gxbb_mpll_prediv.hw 835 }, 836 .num_parents = 1, 837 }, 838 }; 839 840 static struct clk_regmap gxl_mpll0_div = { 841 .data = &(struct meson_clk_mpll_data){ 842 .sdm = { 843 .reg_off = HHI_MPLL_CNTL7, 844 .shift = 0, 845 .width = 14, 846 }, 847 .sdm_en = { 848 .reg_off = HHI_MPLL_CNTL7, 849 .shift = 15, 850 .width = 1, 851 }, 852 .n2 = { 853 .reg_off = HHI_MPLL_CNTL7, 854 .shift = 16, 855 .width = 9, 856 }, 857 }, 858 .hw.init = &(struct clk_init_data){ 859 .name = "mpll0_div", 860 .ops = &meson_clk_mpll_ops, 861 .parent_hws = (const struct clk_hw *[]) { 862 &gxbb_mpll_prediv.hw 863 }, 864 .num_parents = 1, 865 }, 866 }; 867 868 static struct clk_regmap gxbb_mpll0 = { 869 .data = &(struct clk_regmap_gate_data){ 870 .offset = HHI_MPLL_CNTL7, 871 .bit_idx = 14, 872 }, 873 .hw.init = &(struct clk_init_data){ 874 .name = "mpll0", 875 .ops = &clk_regmap_gate_ops, 876 .parent_data = &(const struct clk_parent_data) { 877 /* 878 * Note: 879 * GXL and GXBB have different SDM_EN registers. We 880 * fallback to the global naming string mechanism so 881 * mpll0_div picks up the appropriate one. 882 */ 883 .name = "mpll0_div", 884 .index = -1, 885 }, 886 .num_parents = 1, 887 .flags = CLK_SET_RATE_PARENT, 888 }, 889 }; 890 891 static struct clk_regmap gxbb_mpll1_div = { 892 .data = &(struct meson_clk_mpll_data){ 893 .sdm = { 894 .reg_off = HHI_MPLL_CNTL8, 895 .shift = 0, 896 .width = 14, 897 }, 898 .sdm_en = { 899 .reg_off = HHI_MPLL_CNTL8, 900 .shift = 15, 901 .width = 1, 902 }, 903 .n2 = { 904 .reg_off = HHI_MPLL_CNTL8, 905 .shift = 16, 906 .width = 9, 907 }, 908 }, 909 .hw.init = &(struct clk_init_data){ 910 .name = "mpll1_div", 911 .ops = &meson_clk_mpll_ops, 912 .parent_hws = (const struct clk_hw *[]) { 913 &gxbb_mpll_prediv.hw 914 }, 915 .num_parents = 1, 916 }, 917 }; 918 919 static struct clk_regmap gxbb_mpll1 = { 920 .data = &(struct clk_regmap_gate_data){ 921 .offset = HHI_MPLL_CNTL8, 922 .bit_idx = 14, 923 }, 924 .hw.init = &(struct clk_init_data){ 925 .name = "mpll1", 926 .ops = &clk_regmap_gate_ops, 927 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw }, 928 .num_parents = 1, 929 .flags = CLK_SET_RATE_PARENT, 930 }, 931 }; 932 933 static struct clk_regmap gxbb_mpll2_div = { 934 .data = &(struct meson_clk_mpll_data){ 935 .sdm = { 936 .reg_off = HHI_MPLL_CNTL9, 937 .shift = 0, 938 .width = 14, 939 }, 940 .sdm_en = { 941 .reg_off = HHI_MPLL_CNTL9, 942 .shift = 15, 943 .width = 1, 944 }, 945 .n2 = { 946 .reg_off = HHI_MPLL_CNTL9, 947 .shift = 16, 948 .width = 9, 949 }, 950 }, 951 .hw.init = &(struct clk_init_data){ 952 .name = "mpll2_div", 953 .ops = &meson_clk_mpll_ops, 954 .parent_hws = (const struct clk_hw *[]) { 955 &gxbb_mpll_prediv.hw 956 }, 957 .num_parents = 1, 958 }, 959 }; 960 961 static struct clk_regmap gxbb_mpll2 = { 962 .data = &(struct clk_regmap_gate_data){ 963 .offset = HHI_MPLL_CNTL9, 964 .bit_idx = 14, 965 }, 966 .hw.init = &(struct clk_init_data){ 967 .name = "mpll2", 968 .ops = &clk_regmap_gate_ops, 969 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw }, 970 .num_parents = 1, 971 .flags = CLK_SET_RATE_PARENT, 972 }, 973 }; 974 975 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 976 static const struct clk_parent_data clk81_parent_data[] = { 977 { .fw_name = "xtal", }, 978 { .hw = &gxbb_fclk_div7.hw }, 979 { .hw = &gxbb_mpll1.hw }, 980 { .hw = &gxbb_mpll2.hw }, 981 { .hw = &gxbb_fclk_div4.hw }, 982 { .hw = &gxbb_fclk_div3.hw }, 983 { .hw = &gxbb_fclk_div5.hw }, 984 }; 985 986 static struct clk_regmap gxbb_mpeg_clk_sel = { 987 .data = &(struct clk_regmap_mux_data){ 988 .offset = HHI_MPEG_CLK_CNTL, 989 .mask = 0x7, 990 .shift = 12, 991 .table = mux_table_clk81, 992 }, 993 .hw.init = &(struct clk_init_data){ 994 .name = "mpeg_clk_sel", 995 .ops = &clk_regmap_mux_ro_ops, 996 /* 997 * bits 14:12 selects from 8 possible parents: 998 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 999 * fclk_div4, fclk_div3, fclk_div5 1000 */ 1001 .parent_data = clk81_parent_data, 1002 .num_parents = ARRAY_SIZE(clk81_parent_data), 1003 }, 1004 }; 1005 1006 static struct clk_regmap gxbb_mpeg_clk_div = { 1007 .data = &(struct clk_regmap_div_data){ 1008 .offset = HHI_MPEG_CLK_CNTL, 1009 .shift = 0, 1010 .width = 7, 1011 }, 1012 .hw.init = &(struct clk_init_data){ 1013 .name = "mpeg_clk_div", 1014 .ops = &clk_regmap_divider_ro_ops, 1015 .parent_hws = (const struct clk_hw *[]) { 1016 &gxbb_mpeg_clk_sel.hw 1017 }, 1018 .num_parents = 1, 1019 }, 1020 }; 1021 1022 /* the mother of dragons gates */ 1023 static struct clk_regmap gxbb_clk81 = { 1024 .data = &(struct clk_regmap_gate_data){ 1025 .offset = HHI_MPEG_CLK_CNTL, 1026 .bit_idx = 7, 1027 }, 1028 .hw.init = &(struct clk_init_data){ 1029 .name = "clk81", 1030 .ops = &clk_regmap_gate_ops, 1031 .parent_hws = (const struct clk_hw *[]) { 1032 &gxbb_mpeg_clk_div.hw 1033 }, 1034 .num_parents = 1, 1035 .flags = CLK_IS_CRITICAL, 1036 }, 1037 }; 1038 1039 static struct clk_regmap gxbb_sar_adc_clk_sel = { 1040 .data = &(struct clk_regmap_mux_data){ 1041 .offset = HHI_SAR_CLK_CNTL, 1042 .mask = 0x3, 1043 .shift = 9, 1044 }, 1045 .hw.init = &(struct clk_init_data){ 1046 .name = "sar_adc_clk_sel", 1047 .ops = &clk_regmap_mux_ops, 1048 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 1049 .parent_data = (const struct clk_parent_data []) { 1050 { .fw_name = "xtal", }, 1051 { .hw = &gxbb_clk81.hw }, 1052 }, 1053 .num_parents = 2, 1054 }, 1055 }; 1056 1057 static struct clk_regmap gxbb_sar_adc_clk_div = { 1058 .data = &(struct clk_regmap_div_data){ 1059 .offset = HHI_SAR_CLK_CNTL, 1060 .shift = 0, 1061 .width = 8, 1062 }, 1063 .hw.init = &(struct clk_init_data){ 1064 .name = "sar_adc_clk_div", 1065 .ops = &clk_regmap_divider_ops, 1066 .parent_hws = (const struct clk_hw *[]) { 1067 &gxbb_sar_adc_clk_sel.hw 1068 }, 1069 .num_parents = 1, 1070 .flags = CLK_SET_RATE_PARENT, 1071 }, 1072 }; 1073 1074 static struct clk_regmap gxbb_sar_adc_clk = { 1075 .data = &(struct clk_regmap_gate_data){ 1076 .offset = HHI_SAR_CLK_CNTL, 1077 .bit_idx = 8, 1078 }, 1079 .hw.init = &(struct clk_init_data){ 1080 .name = "sar_adc_clk", 1081 .ops = &clk_regmap_gate_ops, 1082 .parent_hws = (const struct clk_hw *[]) { 1083 &gxbb_sar_adc_clk_div.hw 1084 }, 1085 .num_parents = 1, 1086 .flags = CLK_SET_RATE_PARENT, 1087 }, 1088 }; 1089 1090 /* 1091 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 1092 * muxed by a glitch-free switch. The CCF can manage this glitch-free 1093 * mux because it does top-to-bottom updates the each clock tree and 1094 * switches to the "inactive" one when CLK_SET_RATE_GATE is set. 1095 */ 1096 1097 static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = { 1098 { .fw_name = "xtal", }, 1099 { .hw = &gxbb_gp0_pll.hw }, 1100 { .hw = &gxbb_mpll2.hw }, 1101 { .hw = &gxbb_mpll1.hw }, 1102 { .hw = &gxbb_fclk_div7.hw }, 1103 { .hw = &gxbb_fclk_div4.hw }, 1104 { .hw = &gxbb_fclk_div3.hw }, 1105 { .hw = &gxbb_fclk_div5.hw }, 1106 }; 1107 1108 static struct clk_regmap gxbb_mali_0_sel = { 1109 .data = &(struct clk_regmap_mux_data){ 1110 .offset = HHI_MALI_CLK_CNTL, 1111 .mask = 0x7, 1112 .shift = 9, 1113 }, 1114 .hw.init = &(struct clk_init_data){ 1115 .name = "mali_0_sel", 1116 .ops = &clk_regmap_mux_ops, 1117 .parent_data = gxbb_mali_0_1_parent_data, 1118 .num_parents = 8, 1119 /* 1120 * Don't request the parent to change the rate because 1121 * all GPU frequencies can be derived from the fclk_* 1122 * clocks and one special GP0_PLL setting. This is 1123 * important because we need the MPLL clocks for audio. 1124 */ 1125 .flags = 0, 1126 }, 1127 }; 1128 1129 static struct clk_regmap gxbb_mali_0_div = { 1130 .data = &(struct clk_regmap_div_data){ 1131 .offset = HHI_MALI_CLK_CNTL, 1132 .shift = 0, 1133 .width = 7, 1134 }, 1135 .hw.init = &(struct clk_init_data){ 1136 .name = "mali_0_div", 1137 .ops = &clk_regmap_divider_ops, 1138 .parent_hws = (const struct clk_hw *[]) { 1139 &gxbb_mali_0_sel.hw 1140 }, 1141 .num_parents = 1, 1142 .flags = CLK_SET_RATE_PARENT, 1143 }, 1144 }; 1145 1146 static struct clk_regmap gxbb_mali_0 = { 1147 .data = &(struct clk_regmap_gate_data){ 1148 .offset = HHI_MALI_CLK_CNTL, 1149 .bit_idx = 8, 1150 }, 1151 .hw.init = &(struct clk_init_data){ 1152 .name = "mali_0", 1153 .ops = &clk_regmap_gate_ops, 1154 .parent_hws = (const struct clk_hw *[]) { 1155 &gxbb_mali_0_div.hw 1156 }, 1157 .num_parents = 1, 1158 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1159 }, 1160 }; 1161 1162 static struct clk_regmap gxbb_mali_1_sel = { 1163 .data = &(struct clk_regmap_mux_data){ 1164 .offset = HHI_MALI_CLK_CNTL, 1165 .mask = 0x7, 1166 .shift = 25, 1167 }, 1168 .hw.init = &(struct clk_init_data){ 1169 .name = "mali_1_sel", 1170 .ops = &clk_regmap_mux_ops, 1171 .parent_data = gxbb_mali_0_1_parent_data, 1172 .num_parents = 8, 1173 /* 1174 * Don't request the parent to change the rate because 1175 * all GPU frequencies can be derived from the fclk_* 1176 * clocks and one special GP0_PLL setting. This is 1177 * important because we need the MPLL clocks for audio. 1178 */ 1179 .flags = 0, 1180 }, 1181 }; 1182 1183 static struct clk_regmap gxbb_mali_1_div = { 1184 .data = &(struct clk_regmap_div_data){ 1185 .offset = HHI_MALI_CLK_CNTL, 1186 .shift = 16, 1187 .width = 7, 1188 }, 1189 .hw.init = &(struct clk_init_data){ 1190 .name = "mali_1_div", 1191 .ops = &clk_regmap_divider_ops, 1192 .parent_hws = (const struct clk_hw *[]) { 1193 &gxbb_mali_1_sel.hw 1194 }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 }, 1198 }; 1199 1200 static struct clk_regmap gxbb_mali_1 = { 1201 .data = &(struct clk_regmap_gate_data){ 1202 .offset = HHI_MALI_CLK_CNTL, 1203 .bit_idx = 24, 1204 }, 1205 .hw.init = &(struct clk_init_data){ 1206 .name = "mali_1", 1207 .ops = &clk_regmap_gate_ops, 1208 .parent_hws = (const struct clk_hw *[]) { 1209 &gxbb_mali_1_div.hw 1210 }, 1211 .num_parents = 1, 1212 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1213 }, 1214 }; 1215 1216 static const struct clk_hw *gxbb_mali_parent_hws[] = { 1217 &gxbb_mali_0.hw, 1218 &gxbb_mali_1.hw, 1219 }; 1220 1221 static struct clk_regmap gxbb_mali = { 1222 .data = &(struct clk_regmap_mux_data){ 1223 .offset = HHI_MALI_CLK_CNTL, 1224 .mask = 1, 1225 .shift = 31, 1226 }, 1227 .hw.init = &(struct clk_init_data){ 1228 .name = "mali", 1229 .ops = &clk_regmap_mux_ops, 1230 .parent_hws = gxbb_mali_parent_hws, 1231 .num_parents = 2, 1232 .flags = CLK_SET_RATE_PARENT, 1233 }, 1234 }; 1235 1236 static struct clk_regmap gxbb_cts_amclk_sel = { 1237 .data = &(struct clk_regmap_mux_data){ 1238 .offset = HHI_AUD_CLK_CNTL, 1239 .mask = 0x3, 1240 .shift = 9, 1241 .table = (u32[]){ 1, 2, 3 }, 1242 .flags = CLK_MUX_ROUND_CLOSEST, 1243 }, 1244 .hw.init = &(struct clk_init_data){ 1245 .name = "cts_amclk_sel", 1246 .ops = &clk_regmap_mux_ops, 1247 .parent_hws = (const struct clk_hw *[]) { 1248 &gxbb_mpll0.hw, 1249 &gxbb_mpll1.hw, 1250 &gxbb_mpll2.hw, 1251 }, 1252 .num_parents = 3, 1253 }, 1254 }; 1255 1256 static struct clk_regmap gxbb_cts_amclk_div = { 1257 .data = &(struct clk_regmap_div_data) { 1258 .offset = HHI_AUD_CLK_CNTL, 1259 .shift = 0, 1260 .width = 8, 1261 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1262 }, 1263 .hw.init = &(struct clk_init_data){ 1264 .name = "cts_amclk_div", 1265 .ops = &clk_regmap_divider_ops, 1266 .parent_hws = (const struct clk_hw *[]) { 1267 &gxbb_cts_amclk_sel.hw 1268 }, 1269 .num_parents = 1, 1270 .flags = CLK_SET_RATE_PARENT, 1271 }, 1272 }; 1273 1274 static struct clk_regmap gxbb_cts_amclk = { 1275 .data = &(struct clk_regmap_gate_data){ 1276 .offset = HHI_AUD_CLK_CNTL, 1277 .bit_idx = 8, 1278 }, 1279 .hw.init = &(struct clk_init_data){ 1280 .name = "cts_amclk", 1281 .ops = &clk_regmap_gate_ops, 1282 .parent_hws = (const struct clk_hw *[]) { 1283 &gxbb_cts_amclk_div.hw 1284 }, 1285 .num_parents = 1, 1286 .flags = CLK_SET_RATE_PARENT, 1287 }, 1288 }; 1289 1290 static struct clk_regmap gxbb_cts_mclk_i958_sel = { 1291 .data = &(struct clk_regmap_mux_data){ 1292 .offset = HHI_AUD_CLK_CNTL2, 1293 .mask = 0x3, 1294 .shift = 25, 1295 .table = (u32[]){ 1, 2, 3 }, 1296 .flags = CLK_MUX_ROUND_CLOSEST, 1297 }, 1298 .hw.init = &(struct clk_init_data) { 1299 .name = "cts_mclk_i958_sel", 1300 .ops = &clk_regmap_mux_ops, 1301 .parent_hws = (const struct clk_hw *[]) { 1302 &gxbb_mpll0.hw, 1303 &gxbb_mpll1.hw, 1304 &gxbb_mpll2.hw, 1305 }, 1306 .num_parents = 3, 1307 }, 1308 }; 1309 1310 static struct clk_regmap gxbb_cts_mclk_i958_div = { 1311 .data = &(struct clk_regmap_div_data){ 1312 .offset = HHI_AUD_CLK_CNTL2, 1313 .shift = 16, 1314 .width = 8, 1315 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1316 }, 1317 .hw.init = &(struct clk_init_data) { 1318 .name = "cts_mclk_i958_div", 1319 .ops = &clk_regmap_divider_ops, 1320 .parent_hws = (const struct clk_hw *[]) { 1321 &gxbb_cts_mclk_i958_sel.hw 1322 }, 1323 .num_parents = 1, 1324 .flags = CLK_SET_RATE_PARENT, 1325 }, 1326 }; 1327 1328 static struct clk_regmap gxbb_cts_mclk_i958 = { 1329 .data = &(struct clk_regmap_gate_data){ 1330 .offset = HHI_AUD_CLK_CNTL2, 1331 .bit_idx = 24, 1332 }, 1333 .hw.init = &(struct clk_init_data){ 1334 .name = "cts_mclk_i958", 1335 .ops = &clk_regmap_gate_ops, 1336 .parent_hws = (const struct clk_hw *[]) { 1337 &gxbb_cts_mclk_i958_div.hw 1338 }, 1339 .num_parents = 1, 1340 .flags = CLK_SET_RATE_PARENT, 1341 }, 1342 }; 1343 1344 static struct clk_regmap gxbb_cts_i958 = { 1345 .data = &(struct clk_regmap_mux_data){ 1346 .offset = HHI_AUD_CLK_CNTL2, 1347 .mask = 0x1, 1348 .shift = 27, 1349 }, 1350 .hw.init = &(struct clk_init_data){ 1351 .name = "cts_i958", 1352 .ops = &clk_regmap_mux_ops, 1353 .parent_hws = (const struct clk_hw *[]) { 1354 &gxbb_cts_amclk.hw, 1355 &gxbb_cts_mclk_i958.hw 1356 }, 1357 .num_parents = 2, 1358 /* 1359 *The parent is specific to origin of the audio data. Let the 1360 * consumer choose the appropriate parent 1361 */ 1362 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1363 }, 1364 }; 1365 1366 /* 1367 * This table skips a clock named 'cts_slow_oscin' in the documentation 1368 * This clock does not exist yet in this controller or the AO one 1369 */ 1370 static u32 gxbb_32k_clk_parents_val_table[] = { 0, 2, 3 }; 1371 static const struct clk_parent_data gxbb_32k_clk_parent_data[] = { 1372 { .fw_name = "xtal", }, 1373 { .hw = &gxbb_fclk_div3.hw }, 1374 { .hw = &gxbb_fclk_div5.hw }, 1375 }; 1376 1377 static struct clk_regmap gxbb_32k_clk_sel = { 1378 .data = &(struct clk_regmap_mux_data){ 1379 .offset = HHI_32K_CLK_CNTL, 1380 .mask = 0x3, 1381 .shift = 16, 1382 .table = gxbb_32k_clk_parents_val_table, 1383 }, 1384 .hw.init = &(struct clk_init_data){ 1385 .name = "32k_clk_sel", 1386 .ops = &clk_regmap_mux_ops, 1387 .parent_data = gxbb_32k_clk_parent_data, 1388 .num_parents = 4, 1389 .flags = CLK_SET_RATE_PARENT, 1390 }, 1391 }; 1392 1393 static struct clk_regmap gxbb_32k_clk_div = { 1394 .data = &(struct clk_regmap_div_data){ 1395 .offset = HHI_32K_CLK_CNTL, 1396 .shift = 0, 1397 .width = 14, 1398 }, 1399 .hw.init = &(struct clk_init_data){ 1400 .name = "32k_clk_div", 1401 .ops = &clk_regmap_divider_ops, 1402 .parent_hws = (const struct clk_hw *[]) { 1403 &gxbb_32k_clk_sel.hw 1404 }, 1405 .num_parents = 1, 1406 .flags = CLK_SET_RATE_PARENT, 1407 }, 1408 }; 1409 1410 static struct clk_regmap gxbb_32k_clk = { 1411 .data = &(struct clk_regmap_gate_data){ 1412 .offset = HHI_32K_CLK_CNTL, 1413 .bit_idx = 15, 1414 }, 1415 .hw.init = &(struct clk_init_data){ 1416 .name = "32k_clk", 1417 .ops = &clk_regmap_gate_ops, 1418 .parent_hws = (const struct clk_hw *[]) { 1419 &gxbb_32k_clk_div.hw 1420 }, 1421 .num_parents = 1, 1422 .flags = CLK_SET_RATE_PARENT, 1423 }, 1424 }; 1425 1426 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = { 1427 { .fw_name = "xtal", }, 1428 { .hw = &gxbb_fclk_div2.hw }, 1429 { .hw = &gxbb_fclk_div3.hw }, 1430 { .hw = &gxbb_fclk_div5.hw }, 1431 { .hw = &gxbb_fclk_div7.hw }, 1432 /* 1433 * Following these parent clocks, we should also have had mpll2, mpll3 1434 * and gp0_pll but these clocks are too precious to be used here. All 1435 * the necessary rates for MMC and NAND operation can be achieved using 1436 * xtal or fclk_div clocks 1437 */ 1438 }; 1439 1440 /* SDIO clock */ 1441 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 1442 .data = &(struct clk_regmap_mux_data){ 1443 .offset = HHI_SD_EMMC_CLK_CNTL, 1444 .mask = 0x7, 1445 .shift = 9, 1446 }, 1447 .hw.init = &(struct clk_init_data) { 1448 .name = "sd_emmc_a_clk0_sel", 1449 .ops = &clk_regmap_mux_ops, 1450 .parent_data = gxbb_sd_emmc_clk0_parent_data, 1451 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1452 .flags = CLK_SET_RATE_PARENT, 1453 }, 1454 }; 1455 1456 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1457 .data = &(struct clk_regmap_div_data){ 1458 .offset = HHI_SD_EMMC_CLK_CNTL, 1459 .shift = 0, 1460 .width = 7, 1461 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1462 }, 1463 .hw.init = &(struct clk_init_data) { 1464 .name = "sd_emmc_a_clk0_div", 1465 .ops = &clk_regmap_divider_ops, 1466 .parent_hws = (const struct clk_hw *[]) { 1467 &gxbb_sd_emmc_a_clk0_sel.hw 1468 }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 }, 1472 }; 1473 1474 static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 1475 .data = &(struct clk_regmap_gate_data){ 1476 .offset = HHI_SD_EMMC_CLK_CNTL, 1477 .bit_idx = 7, 1478 }, 1479 .hw.init = &(struct clk_init_data){ 1480 .name = "sd_emmc_a_clk0", 1481 .ops = &clk_regmap_gate_ops, 1482 .parent_hws = (const struct clk_hw *[]) { 1483 &gxbb_sd_emmc_a_clk0_div.hw 1484 }, 1485 .num_parents = 1, 1486 .flags = CLK_SET_RATE_PARENT, 1487 }, 1488 }; 1489 1490 /* SDcard clock */ 1491 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 1492 .data = &(struct clk_regmap_mux_data){ 1493 .offset = HHI_SD_EMMC_CLK_CNTL, 1494 .mask = 0x7, 1495 .shift = 25, 1496 }, 1497 .hw.init = &(struct clk_init_data) { 1498 .name = "sd_emmc_b_clk0_sel", 1499 .ops = &clk_regmap_mux_ops, 1500 .parent_data = gxbb_sd_emmc_clk0_parent_data, 1501 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1502 .flags = CLK_SET_RATE_PARENT, 1503 }, 1504 }; 1505 1506 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1507 .data = &(struct clk_regmap_div_data){ 1508 .offset = HHI_SD_EMMC_CLK_CNTL, 1509 .shift = 16, 1510 .width = 7, 1511 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1512 }, 1513 .hw.init = &(struct clk_init_data) { 1514 .name = "sd_emmc_b_clk0_div", 1515 .ops = &clk_regmap_divider_ops, 1516 .parent_hws = (const struct clk_hw *[]) { 1517 &gxbb_sd_emmc_b_clk0_sel.hw 1518 }, 1519 .num_parents = 1, 1520 .flags = CLK_SET_RATE_PARENT, 1521 }, 1522 }; 1523 1524 static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 1525 .data = &(struct clk_regmap_gate_data){ 1526 .offset = HHI_SD_EMMC_CLK_CNTL, 1527 .bit_idx = 23, 1528 }, 1529 .hw.init = &(struct clk_init_data){ 1530 .name = "sd_emmc_b_clk0", 1531 .ops = &clk_regmap_gate_ops, 1532 .parent_hws = (const struct clk_hw *[]) { 1533 &gxbb_sd_emmc_b_clk0_div.hw 1534 }, 1535 .num_parents = 1, 1536 .flags = CLK_SET_RATE_PARENT, 1537 }, 1538 }; 1539 1540 /* EMMC/NAND clock */ 1541 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 1542 .data = &(struct clk_regmap_mux_data){ 1543 .offset = HHI_NAND_CLK_CNTL, 1544 .mask = 0x7, 1545 .shift = 9, 1546 }, 1547 .hw.init = &(struct clk_init_data) { 1548 .name = "sd_emmc_c_clk0_sel", 1549 .ops = &clk_regmap_mux_ops, 1550 .parent_data = gxbb_sd_emmc_clk0_parent_data, 1551 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1552 .flags = CLK_SET_RATE_PARENT, 1553 }, 1554 }; 1555 1556 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1557 .data = &(struct clk_regmap_div_data){ 1558 .offset = HHI_NAND_CLK_CNTL, 1559 .shift = 0, 1560 .width = 7, 1561 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1562 }, 1563 .hw.init = &(struct clk_init_data) { 1564 .name = "sd_emmc_c_clk0_div", 1565 .ops = &clk_regmap_divider_ops, 1566 .parent_hws = (const struct clk_hw *[]) { 1567 &gxbb_sd_emmc_c_clk0_sel.hw 1568 }, 1569 .num_parents = 1, 1570 .flags = CLK_SET_RATE_PARENT, 1571 }, 1572 }; 1573 1574 static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 1575 .data = &(struct clk_regmap_gate_data){ 1576 .offset = HHI_NAND_CLK_CNTL, 1577 .bit_idx = 7, 1578 }, 1579 .hw.init = &(struct clk_init_data){ 1580 .name = "sd_emmc_c_clk0", 1581 .ops = &clk_regmap_gate_ops, 1582 .parent_hws = (const struct clk_hw *[]) { 1583 &gxbb_sd_emmc_c_clk0_div.hw 1584 }, 1585 .num_parents = 1, 1586 .flags = CLK_SET_RATE_PARENT, 1587 }, 1588 }; 1589 1590 /* VPU Clock */ 1591 1592 static const struct clk_hw *gxbb_vpu_parent_hws[] = { 1593 &gxbb_fclk_div4.hw, 1594 &gxbb_fclk_div3.hw, 1595 &gxbb_fclk_div5.hw, 1596 &gxbb_fclk_div7.hw, 1597 }; 1598 1599 static struct clk_regmap gxbb_vpu_0_sel = { 1600 .data = &(struct clk_regmap_mux_data){ 1601 .offset = HHI_VPU_CLK_CNTL, 1602 .mask = 0x3, 1603 .shift = 9, 1604 }, 1605 .hw.init = &(struct clk_init_data){ 1606 .name = "vpu_0_sel", 1607 .ops = &clk_regmap_mux_ops, 1608 /* 1609 * bits 9:10 selects from 4 possible parents: 1610 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1611 */ 1612 .parent_hws = gxbb_vpu_parent_hws, 1613 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws), 1614 .flags = CLK_SET_RATE_NO_REPARENT, 1615 }, 1616 }; 1617 1618 static struct clk_regmap gxbb_vpu_0_div = { 1619 .data = &(struct clk_regmap_div_data){ 1620 .offset = HHI_VPU_CLK_CNTL, 1621 .shift = 0, 1622 .width = 7, 1623 }, 1624 .hw.init = &(struct clk_init_data){ 1625 .name = "vpu_0_div", 1626 .ops = &clk_regmap_divider_ops, 1627 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw }, 1628 .num_parents = 1, 1629 .flags = CLK_SET_RATE_PARENT, 1630 }, 1631 }; 1632 1633 static struct clk_regmap gxbb_vpu_0 = { 1634 .data = &(struct clk_regmap_gate_data){ 1635 .offset = HHI_VPU_CLK_CNTL, 1636 .bit_idx = 8, 1637 }, 1638 .hw.init = &(struct clk_init_data) { 1639 .name = "vpu_0", 1640 .ops = &clk_regmap_gate_ops, 1641 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw }, 1642 .num_parents = 1, 1643 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1644 }, 1645 }; 1646 1647 static struct clk_regmap gxbb_vpu_1_sel = { 1648 .data = &(struct clk_regmap_mux_data){ 1649 .offset = HHI_VPU_CLK_CNTL, 1650 .mask = 0x3, 1651 .shift = 25, 1652 }, 1653 .hw.init = &(struct clk_init_data){ 1654 .name = "vpu_1_sel", 1655 .ops = &clk_regmap_mux_ops, 1656 /* 1657 * bits 25:26 selects from 4 possible parents: 1658 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1659 */ 1660 .parent_hws = gxbb_vpu_parent_hws, 1661 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws), 1662 .flags = CLK_SET_RATE_NO_REPARENT, 1663 }, 1664 }; 1665 1666 static struct clk_regmap gxbb_vpu_1_div = { 1667 .data = &(struct clk_regmap_div_data){ 1668 .offset = HHI_VPU_CLK_CNTL, 1669 .shift = 16, 1670 .width = 7, 1671 }, 1672 .hw.init = &(struct clk_init_data){ 1673 .name = "vpu_1_div", 1674 .ops = &clk_regmap_divider_ops, 1675 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw }, 1676 .num_parents = 1, 1677 .flags = CLK_SET_RATE_PARENT, 1678 }, 1679 }; 1680 1681 static struct clk_regmap gxbb_vpu_1 = { 1682 .data = &(struct clk_regmap_gate_data){ 1683 .offset = HHI_VPU_CLK_CNTL, 1684 .bit_idx = 24, 1685 }, 1686 .hw.init = &(struct clk_init_data) { 1687 .name = "vpu_1", 1688 .ops = &clk_regmap_gate_ops, 1689 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw }, 1690 .num_parents = 1, 1691 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1692 }, 1693 }; 1694 1695 static struct clk_regmap gxbb_vpu = { 1696 .data = &(struct clk_regmap_mux_data){ 1697 .offset = HHI_VPU_CLK_CNTL, 1698 .mask = 1, 1699 .shift = 31, 1700 }, 1701 .hw.init = &(struct clk_init_data){ 1702 .name = "vpu", 1703 .ops = &clk_regmap_mux_ops, 1704 /* 1705 * bit 31 selects from 2 possible parents: 1706 * vpu_0 or vpu_1 1707 */ 1708 .parent_hws = (const struct clk_hw *[]) { 1709 &gxbb_vpu_0.hw, 1710 &gxbb_vpu_1.hw 1711 }, 1712 .num_parents = 2, 1713 .flags = CLK_SET_RATE_NO_REPARENT, 1714 }, 1715 }; 1716 1717 /* VAPB Clock */ 1718 1719 static const struct clk_hw *gxbb_vapb_parent_hws[] = { 1720 &gxbb_fclk_div4.hw, 1721 &gxbb_fclk_div3.hw, 1722 &gxbb_fclk_div5.hw, 1723 &gxbb_fclk_div7.hw, 1724 }; 1725 1726 static struct clk_regmap gxbb_vapb_0_sel = { 1727 .data = &(struct clk_regmap_mux_data){ 1728 .offset = HHI_VAPBCLK_CNTL, 1729 .mask = 0x3, 1730 .shift = 9, 1731 }, 1732 .hw.init = &(struct clk_init_data){ 1733 .name = "vapb_0_sel", 1734 .ops = &clk_regmap_mux_ops, 1735 /* 1736 * bits 9:10 selects from 4 possible parents: 1737 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1738 */ 1739 .parent_hws = gxbb_vapb_parent_hws, 1740 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws), 1741 .flags = CLK_SET_RATE_NO_REPARENT, 1742 }, 1743 }; 1744 1745 static struct clk_regmap gxbb_vapb_0_div = { 1746 .data = &(struct clk_regmap_div_data){ 1747 .offset = HHI_VAPBCLK_CNTL, 1748 .shift = 0, 1749 .width = 7, 1750 }, 1751 .hw.init = &(struct clk_init_data){ 1752 .name = "vapb_0_div", 1753 .ops = &clk_regmap_divider_ops, 1754 .parent_hws = (const struct clk_hw *[]) { 1755 &gxbb_vapb_0_sel.hw 1756 }, 1757 .num_parents = 1, 1758 .flags = CLK_SET_RATE_PARENT, 1759 }, 1760 }; 1761 1762 static struct clk_regmap gxbb_vapb_0 = { 1763 .data = &(struct clk_regmap_gate_data){ 1764 .offset = HHI_VAPBCLK_CNTL, 1765 .bit_idx = 8, 1766 }, 1767 .hw.init = &(struct clk_init_data) { 1768 .name = "vapb_0", 1769 .ops = &clk_regmap_gate_ops, 1770 .parent_hws = (const struct clk_hw *[]) { 1771 &gxbb_vapb_0_div.hw 1772 }, 1773 .num_parents = 1, 1774 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1775 }, 1776 }; 1777 1778 static struct clk_regmap gxbb_vapb_1_sel = { 1779 .data = &(struct clk_regmap_mux_data){ 1780 .offset = HHI_VAPBCLK_CNTL, 1781 .mask = 0x3, 1782 .shift = 25, 1783 }, 1784 .hw.init = &(struct clk_init_data){ 1785 .name = "vapb_1_sel", 1786 .ops = &clk_regmap_mux_ops, 1787 /* 1788 * bits 25:26 selects from 4 possible parents: 1789 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1790 */ 1791 .parent_hws = gxbb_vapb_parent_hws, 1792 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws), 1793 .flags = CLK_SET_RATE_NO_REPARENT, 1794 }, 1795 }; 1796 1797 static struct clk_regmap gxbb_vapb_1_div = { 1798 .data = &(struct clk_regmap_div_data){ 1799 .offset = HHI_VAPBCLK_CNTL, 1800 .shift = 16, 1801 .width = 7, 1802 }, 1803 .hw.init = &(struct clk_init_data){ 1804 .name = "vapb_1_div", 1805 .ops = &clk_regmap_divider_ops, 1806 .parent_hws = (const struct clk_hw *[]) { 1807 &gxbb_vapb_1_sel.hw 1808 }, 1809 .num_parents = 1, 1810 .flags = CLK_SET_RATE_PARENT, 1811 }, 1812 }; 1813 1814 static struct clk_regmap gxbb_vapb_1 = { 1815 .data = &(struct clk_regmap_gate_data){ 1816 .offset = HHI_VAPBCLK_CNTL, 1817 .bit_idx = 24, 1818 }, 1819 .hw.init = &(struct clk_init_data) { 1820 .name = "vapb_1", 1821 .ops = &clk_regmap_gate_ops, 1822 .parent_hws = (const struct clk_hw *[]) { 1823 &gxbb_vapb_1_div.hw 1824 }, 1825 .num_parents = 1, 1826 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1827 }, 1828 }; 1829 1830 static struct clk_regmap gxbb_vapb_sel = { 1831 .data = &(struct clk_regmap_mux_data){ 1832 .offset = HHI_VAPBCLK_CNTL, 1833 .mask = 1, 1834 .shift = 31, 1835 }, 1836 .hw.init = &(struct clk_init_data){ 1837 .name = "vapb_sel", 1838 .ops = &clk_regmap_mux_ops, 1839 /* 1840 * bit 31 selects from 2 possible parents: 1841 * vapb_0 or vapb_1 1842 */ 1843 .parent_hws = (const struct clk_hw *[]) { 1844 &gxbb_vapb_0.hw, 1845 &gxbb_vapb_1.hw 1846 }, 1847 .num_parents = 2, 1848 .flags = CLK_SET_RATE_NO_REPARENT, 1849 }, 1850 }; 1851 1852 static struct clk_regmap gxbb_vapb = { 1853 .data = &(struct clk_regmap_gate_data){ 1854 .offset = HHI_VAPBCLK_CNTL, 1855 .bit_idx = 30, 1856 }, 1857 .hw.init = &(struct clk_init_data) { 1858 .name = "vapb", 1859 .ops = &clk_regmap_gate_ops, 1860 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw }, 1861 .num_parents = 1, 1862 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1863 }, 1864 }; 1865 1866 /* Video Clocks */ 1867 1868 static struct clk_regmap gxbb_vid_pll_div = { 1869 .data = &(struct meson_vid_pll_div_data){ 1870 .val = { 1871 .reg_off = HHI_VID_PLL_CLK_DIV, 1872 .shift = 0, 1873 .width = 15, 1874 }, 1875 .sel = { 1876 .reg_off = HHI_VID_PLL_CLK_DIV, 1877 .shift = 16, 1878 .width = 2, 1879 }, 1880 }, 1881 .hw.init = &(struct clk_init_data) { 1882 .name = "vid_pll_div", 1883 .ops = &meson_vid_pll_div_ro_ops, 1884 .parent_data = &(const struct clk_parent_data) { 1885 /* 1886 * Note: 1887 * GXL and GXBB have different hdmi_plls (with 1888 * different struct clk_hw). We fallback to the global 1889 * naming string mechanism so vid_pll_div picks up the 1890 * appropriate one. 1891 */ 1892 .name = "hdmi_pll", 1893 .index = -1, 1894 }, 1895 .num_parents = 1, 1896 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1897 }, 1898 }; 1899 1900 static const struct clk_parent_data gxbb_vid_pll_parent_data[] = { 1901 { .hw = &gxbb_vid_pll_div.hw }, 1902 /* 1903 * Note: 1904 * GXL and GXBB have different hdmi_plls (with 1905 * different struct clk_hw). We fallback to the global 1906 * naming string mechanism so vid_pll_div picks up the 1907 * appropriate one. 1908 */ 1909 { .name = "hdmi_pll", .index = -1 }, 1910 }; 1911 1912 static struct clk_regmap gxbb_vid_pll_sel = { 1913 .data = &(struct clk_regmap_mux_data){ 1914 .offset = HHI_VID_PLL_CLK_DIV, 1915 .mask = 0x1, 1916 .shift = 18, 1917 }, 1918 .hw.init = &(struct clk_init_data){ 1919 .name = "vid_pll_sel", 1920 .ops = &clk_regmap_mux_ops, 1921 /* 1922 * bit 18 selects from 2 possible parents: 1923 * vid_pll_div or hdmi_pll 1924 */ 1925 .parent_data = gxbb_vid_pll_parent_data, 1926 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data), 1927 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1928 }, 1929 }; 1930 1931 static struct clk_regmap gxbb_vid_pll = { 1932 .data = &(struct clk_regmap_gate_data){ 1933 .offset = HHI_VID_PLL_CLK_DIV, 1934 .bit_idx = 19, 1935 }, 1936 .hw.init = &(struct clk_init_data) { 1937 .name = "vid_pll", 1938 .ops = &clk_regmap_gate_ops, 1939 .parent_hws = (const struct clk_hw *[]) { 1940 &gxbb_vid_pll_sel.hw 1941 }, 1942 .num_parents = 1, 1943 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1944 }, 1945 }; 1946 1947 static const struct clk_hw *gxbb_vclk_parent_hws[] = { 1948 &gxbb_vid_pll.hw, 1949 &gxbb_fclk_div4.hw, 1950 &gxbb_fclk_div3.hw, 1951 &gxbb_fclk_div5.hw, 1952 &gxbb_vid_pll.hw, 1953 &gxbb_fclk_div7.hw, 1954 &gxbb_mpll1.hw, 1955 }; 1956 1957 static struct clk_regmap gxbb_vclk_sel = { 1958 .data = &(struct clk_regmap_mux_data){ 1959 .offset = HHI_VID_CLK_CNTL, 1960 .mask = 0x7, 1961 .shift = 16, 1962 }, 1963 .hw.init = &(struct clk_init_data){ 1964 .name = "vclk_sel", 1965 .ops = &clk_regmap_mux_ops, 1966 /* 1967 * bits 16:18 selects from 8 possible parents: 1968 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1969 * vid_pll, fclk_div7, mp1 1970 */ 1971 .parent_hws = gxbb_vclk_parent_hws, 1972 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws), 1973 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1974 }, 1975 }; 1976 1977 static struct clk_regmap gxbb_vclk2_sel = { 1978 .data = &(struct clk_regmap_mux_data){ 1979 .offset = HHI_VIID_CLK_CNTL, 1980 .mask = 0x7, 1981 .shift = 16, 1982 }, 1983 .hw.init = &(struct clk_init_data){ 1984 .name = "vclk2_sel", 1985 .ops = &clk_regmap_mux_ops, 1986 /* 1987 * bits 16:18 selects from 8 possible parents: 1988 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1989 * vid_pll, fclk_div7, mp1 1990 */ 1991 .parent_hws = gxbb_vclk_parent_hws, 1992 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws), 1993 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1994 }, 1995 }; 1996 1997 static struct clk_regmap gxbb_vclk_input = { 1998 .data = &(struct clk_regmap_gate_data){ 1999 .offset = HHI_VID_CLK_DIV, 2000 .bit_idx = 16, 2001 }, 2002 .hw.init = &(struct clk_init_data) { 2003 .name = "vclk_input", 2004 .ops = &clk_regmap_gate_ops, 2005 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw }, 2006 .num_parents = 1, 2007 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2008 }, 2009 }; 2010 2011 static struct clk_regmap gxbb_vclk2_input = { 2012 .data = &(struct clk_regmap_gate_data){ 2013 .offset = HHI_VIID_CLK_DIV, 2014 .bit_idx = 16, 2015 }, 2016 .hw.init = &(struct clk_init_data) { 2017 .name = "vclk2_input", 2018 .ops = &clk_regmap_gate_ops, 2019 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw }, 2020 .num_parents = 1, 2021 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2022 }, 2023 }; 2024 2025 static struct clk_regmap gxbb_vclk_div = { 2026 .data = &(struct clk_regmap_div_data){ 2027 .offset = HHI_VID_CLK_DIV, 2028 .shift = 0, 2029 .width = 8, 2030 }, 2031 .hw.init = &(struct clk_init_data){ 2032 .name = "vclk_div", 2033 .ops = &clk_regmap_divider_ops, 2034 .parent_hws = (const struct clk_hw *[]) { 2035 &gxbb_vclk_input.hw 2036 }, 2037 .num_parents = 1, 2038 .flags = CLK_GET_RATE_NOCACHE, 2039 }, 2040 }; 2041 2042 static struct clk_regmap gxbb_vclk2_div = { 2043 .data = &(struct clk_regmap_div_data){ 2044 .offset = HHI_VIID_CLK_DIV, 2045 .shift = 0, 2046 .width = 8, 2047 }, 2048 .hw.init = &(struct clk_init_data){ 2049 .name = "vclk2_div", 2050 .ops = &clk_regmap_divider_ops, 2051 .parent_hws = (const struct clk_hw *[]) { 2052 &gxbb_vclk2_input.hw 2053 }, 2054 .num_parents = 1, 2055 .flags = CLK_GET_RATE_NOCACHE, 2056 }, 2057 }; 2058 2059 static struct clk_regmap gxbb_vclk = { 2060 .data = &(struct clk_regmap_gate_data){ 2061 .offset = HHI_VID_CLK_CNTL, 2062 .bit_idx = 19, 2063 }, 2064 .hw.init = &(struct clk_init_data) { 2065 .name = "vclk", 2066 .ops = &clk_regmap_gate_ops, 2067 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw }, 2068 .num_parents = 1, 2069 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2070 }, 2071 }; 2072 2073 static struct clk_regmap gxbb_vclk2 = { 2074 .data = &(struct clk_regmap_gate_data){ 2075 .offset = HHI_VIID_CLK_CNTL, 2076 .bit_idx = 19, 2077 }, 2078 .hw.init = &(struct clk_init_data) { 2079 .name = "vclk2", 2080 .ops = &clk_regmap_gate_ops, 2081 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw }, 2082 .num_parents = 1, 2083 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2084 }, 2085 }; 2086 2087 static struct clk_regmap gxbb_vclk_div1 = { 2088 .data = &(struct clk_regmap_gate_data){ 2089 .offset = HHI_VID_CLK_CNTL, 2090 .bit_idx = 0, 2091 }, 2092 .hw.init = &(struct clk_init_data) { 2093 .name = "vclk_div1", 2094 .ops = &clk_regmap_gate_ops, 2095 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2096 .num_parents = 1, 2097 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2098 }, 2099 }; 2100 2101 static struct clk_regmap gxbb_vclk_div2_en = { 2102 .data = &(struct clk_regmap_gate_data){ 2103 .offset = HHI_VID_CLK_CNTL, 2104 .bit_idx = 1, 2105 }, 2106 .hw.init = &(struct clk_init_data) { 2107 .name = "vclk_div2_en", 2108 .ops = &clk_regmap_gate_ops, 2109 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2110 .num_parents = 1, 2111 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2112 }, 2113 }; 2114 2115 static struct clk_regmap gxbb_vclk_div4_en = { 2116 .data = &(struct clk_regmap_gate_data){ 2117 .offset = HHI_VID_CLK_CNTL, 2118 .bit_idx = 2, 2119 }, 2120 .hw.init = &(struct clk_init_data) { 2121 .name = "vclk_div4_en", 2122 .ops = &clk_regmap_gate_ops, 2123 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2124 .num_parents = 1, 2125 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2126 }, 2127 }; 2128 2129 static struct clk_regmap gxbb_vclk_div6_en = { 2130 .data = &(struct clk_regmap_gate_data){ 2131 .offset = HHI_VID_CLK_CNTL, 2132 .bit_idx = 3, 2133 }, 2134 .hw.init = &(struct clk_init_data) { 2135 .name = "vclk_div6_en", 2136 .ops = &clk_regmap_gate_ops, 2137 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2138 .num_parents = 1, 2139 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2140 }, 2141 }; 2142 2143 static struct clk_regmap gxbb_vclk_div12_en = { 2144 .data = &(struct clk_regmap_gate_data){ 2145 .offset = HHI_VID_CLK_CNTL, 2146 .bit_idx = 4, 2147 }, 2148 .hw.init = &(struct clk_init_data) { 2149 .name = "vclk_div12_en", 2150 .ops = &clk_regmap_gate_ops, 2151 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2152 .num_parents = 1, 2153 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2154 }, 2155 }; 2156 2157 static struct clk_regmap gxbb_vclk2_div1 = { 2158 .data = &(struct clk_regmap_gate_data){ 2159 .offset = HHI_VIID_CLK_CNTL, 2160 .bit_idx = 0, 2161 }, 2162 .hw.init = &(struct clk_init_data) { 2163 .name = "vclk2_div1", 2164 .ops = &clk_regmap_gate_ops, 2165 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2166 .num_parents = 1, 2167 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2168 }, 2169 }; 2170 2171 static struct clk_regmap gxbb_vclk2_div2_en = { 2172 .data = &(struct clk_regmap_gate_data){ 2173 .offset = HHI_VIID_CLK_CNTL, 2174 .bit_idx = 1, 2175 }, 2176 .hw.init = &(struct clk_init_data) { 2177 .name = "vclk2_div2_en", 2178 .ops = &clk_regmap_gate_ops, 2179 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2180 .num_parents = 1, 2181 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2182 }, 2183 }; 2184 2185 static struct clk_regmap gxbb_vclk2_div4_en = { 2186 .data = &(struct clk_regmap_gate_data){ 2187 .offset = HHI_VIID_CLK_CNTL, 2188 .bit_idx = 2, 2189 }, 2190 .hw.init = &(struct clk_init_data) { 2191 .name = "vclk2_div4_en", 2192 .ops = &clk_regmap_gate_ops, 2193 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2194 .num_parents = 1, 2195 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2196 }, 2197 }; 2198 2199 static struct clk_regmap gxbb_vclk2_div6_en = { 2200 .data = &(struct clk_regmap_gate_data){ 2201 .offset = HHI_VIID_CLK_CNTL, 2202 .bit_idx = 3, 2203 }, 2204 .hw.init = &(struct clk_init_data) { 2205 .name = "vclk2_div6_en", 2206 .ops = &clk_regmap_gate_ops, 2207 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2208 .num_parents = 1, 2209 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2210 }, 2211 }; 2212 2213 static struct clk_regmap gxbb_vclk2_div12_en = { 2214 .data = &(struct clk_regmap_gate_data){ 2215 .offset = HHI_VIID_CLK_CNTL, 2216 .bit_idx = 4, 2217 }, 2218 .hw.init = &(struct clk_init_data) { 2219 .name = "vclk2_div12_en", 2220 .ops = &clk_regmap_gate_ops, 2221 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2222 .num_parents = 1, 2223 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2224 }, 2225 }; 2226 2227 static struct clk_fixed_factor gxbb_vclk_div2 = { 2228 .mult = 1, 2229 .div = 2, 2230 .hw.init = &(struct clk_init_data){ 2231 .name = "vclk_div2", 2232 .ops = &clk_fixed_factor_ops, 2233 .parent_hws = (const struct clk_hw *[]) { 2234 &gxbb_vclk_div2_en.hw 2235 }, 2236 .num_parents = 1, 2237 }, 2238 }; 2239 2240 static struct clk_fixed_factor gxbb_vclk_div4 = { 2241 .mult = 1, 2242 .div = 4, 2243 .hw.init = &(struct clk_init_data){ 2244 .name = "vclk_div4", 2245 .ops = &clk_fixed_factor_ops, 2246 .parent_hws = (const struct clk_hw *[]) { 2247 &gxbb_vclk_div4_en.hw 2248 }, 2249 .num_parents = 1, 2250 }, 2251 }; 2252 2253 static struct clk_fixed_factor gxbb_vclk_div6 = { 2254 .mult = 1, 2255 .div = 6, 2256 .hw.init = &(struct clk_init_data){ 2257 .name = "vclk_div6", 2258 .ops = &clk_fixed_factor_ops, 2259 .parent_hws = (const struct clk_hw *[]) { 2260 &gxbb_vclk_div6_en.hw 2261 }, 2262 .num_parents = 1, 2263 }, 2264 }; 2265 2266 static struct clk_fixed_factor gxbb_vclk_div12 = { 2267 .mult = 1, 2268 .div = 12, 2269 .hw.init = &(struct clk_init_data){ 2270 .name = "vclk_div12", 2271 .ops = &clk_fixed_factor_ops, 2272 .parent_hws = (const struct clk_hw *[]) { 2273 &gxbb_vclk_div12_en.hw 2274 }, 2275 .num_parents = 1, 2276 }, 2277 }; 2278 2279 static struct clk_fixed_factor gxbb_vclk2_div2 = { 2280 .mult = 1, 2281 .div = 2, 2282 .hw.init = &(struct clk_init_data){ 2283 .name = "vclk2_div2", 2284 .ops = &clk_fixed_factor_ops, 2285 .parent_hws = (const struct clk_hw *[]) { 2286 &gxbb_vclk2_div2_en.hw 2287 }, 2288 .num_parents = 1, 2289 }, 2290 }; 2291 2292 static struct clk_fixed_factor gxbb_vclk2_div4 = { 2293 .mult = 1, 2294 .div = 4, 2295 .hw.init = &(struct clk_init_data){ 2296 .name = "vclk2_div4", 2297 .ops = &clk_fixed_factor_ops, 2298 .parent_hws = (const struct clk_hw *[]) { 2299 &gxbb_vclk2_div4_en.hw 2300 }, 2301 .num_parents = 1, 2302 }, 2303 }; 2304 2305 static struct clk_fixed_factor gxbb_vclk2_div6 = { 2306 .mult = 1, 2307 .div = 6, 2308 .hw.init = &(struct clk_init_data){ 2309 .name = "vclk2_div6", 2310 .ops = &clk_fixed_factor_ops, 2311 .parent_hws = (const struct clk_hw *[]) { 2312 &gxbb_vclk2_div6_en.hw 2313 }, 2314 .num_parents = 1, 2315 }, 2316 }; 2317 2318 static struct clk_fixed_factor gxbb_vclk2_div12 = { 2319 .mult = 1, 2320 .div = 12, 2321 .hw.init = &(struct clk_init_data){ 2322 .name = "vclk2_div12", 2323 .ops = &clk_fixed_factor_ops, 2324 .parent_hws = (const struct clk_hw *[]) { 2325 &gxbb_vclk2_div12_en.hw 2326 }, 2327 .num_parents = 1, 2328 }, 2329 }; 2330 2331 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2332 static const struct clk_hw *gxbb_cts_parent_hws[] = { 2333 &gxbb_vclk_div1.hw, 2334 &gxbb_vclk_div2.hw, 2335 &gxbb_vclk_div4.hw, 2336 &gxbb_vclk_div6.hw, 2337 &gxbb_vclk_div12.hw, 2338 &gxbb_vclk2_div1.hw, 2339 &gxbb_vclk2_div2.hw, 2340 &gxbb_vclk2_div4.hw, 2341 &gxbb_vclk2_div6.hw, 2342 &gxbb_vclk2_div12.hw, 2343 }; 2344 2345 static struct clk_regmap gxbb_cts_enci_sel = { 2346 .data = &(struct clk_regmap_mux_data){ 2347 .offset = HHI_VID_CLK_DIV, 2348 .mask = 0xf, 2349 .shift = 28, 2350 .table = mux_table_cts_sel, 2351 }, 2352 .hw.init = &(struct clk_init_data){ 2353 .name = "cts_enci_sel", 2354 .ops = &clk_regmap_mux_ops, 2355 .parent_hws = gxbb_cts_parent_hws, 2356 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2357 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2358 }, 2359 }; 2360 2361 static struct clk_regmap gxbb_cts_encp_sel = { 2362 .data = &(struct clk_regmap_mux_data){ 2363 .offset = HHI_VID_CLK_DIV, 2364 .mask = 0xf, 2365 .shift = 20, 2366 .table = mux_table_cts_sel, 2367 }, 2368 .hw.init = &(struct clk_init_data){ 2369 .name = "cts_encp_sel", 2370 .ops = &clk_regmap_mux_ops, 2371 .parent_hws = gxbb_cts_parent_hws, 2372 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2373 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2374 }, 2375 }; 2376 2377 static struct clk_regmap gxbb_cts_vdac_sel = { 2378 .data = &(struct clk_regmap_mux_data){ 2379 .offset = HHI_VIID_CLK_DIV, 2380 .mask = 0xf, 2381 .shift = 28, 2382 .table = mux_table_cts_sel, 2383 }, 2384 .hw.init = &(struct clk_init_data){ 2385 .name = "cts_vdac_sel", 2386 .ops = &clk_regmap_mux_ops, 2387 .parent_hws = gxbb_cts_parent_hws, 2388 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2389 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2390 }, 2391 }; 2392 2393 /* TOFIX: add support for cts_tcon */ 2394 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2395 static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = { 2396 &gxbb_vclk_div1.hw, 2397 &gxbb_vclk_div2.hw, 2398 &gxbb_vclk_div4.hw, 2399 &gxbb_vclk_div6.hw, 2400 &gxbb_vclk_div12.hw, 2401 &gxbb_vclk2_div1.hw, 2402 &gxbb_vclk2_div2.hw, 2403 &gxbb_vclk2_div4.hw, 2404 &gxbb_vclk2_div6.hw, 2405 &gxbb_vclk2_div12.hw, 2406 }; 2407 2408 static struct clk_regmap gxbb_hdmi_tx_sel = { 2409 .data = &(struct clk_regmap_mux_data){ 2410 .offset = HHI_HDMI_CLK_CNTL, 2411 .mask = 0xf, 2412 .shift = 16, 2413 .table = mux_table_hdmi_tx_sel, 2414 }, 2415 .hw.init = &(struct clk_init_data){ 2416 .name = "hdmi_tx_sel", 2417 .ops = &clk_regmap_mux_ops, 2418 /* 2419 * bits 31:28 selects from 12 possible parents: 2420 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 2421 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, 2422 * cts_tcon 2423 */ 2424 .parent_hws = gxbb_cts_hdmi_tx_parent_hws, 2425 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws), 2426 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2427 }, 2428 }; 2429 2430 static struct clk_regmap gxbb_cts_enci = { 2431 .data = &(struct clk_regmap_gate_data){ 2432 .offset = HHI_VID_CLK_CNTL2, 2433 .bit_idx = 0, 2434 }, 2435 .hw.init = &(struct clk_init_data) { 2436 .name = "cts_enci", 2437 .ops = &clk_regmap_gate_ops, 2438 .parent_hws = (const struct clk_hw *[]) { 2439 &gxbb_cts_enci_sel.hw 2440 }, 2441 .num_parents = 1, 2442 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2443 }, 2444 }; 2445 2446 static struct clk_regmap gxbb_cts_encp = { 2447 .data = &(struct clk_regmap_gate_data){ 2448 .offset = HHI_VID_CLK_CNTL2, 2449 .bit_idx = 2, 2450 }, 2451 .hw.init = &(struct clk_init_data) { 2452 .name = "cts_encp", 2453 .ops = &clk_regmap_gate_ops, 2454 .parent_hws = (const struct clk_hw *[]) { 2455 &gxbb_cts_encp_sel.hw 2456 }, 2457 .num_parents = 1, 2458 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2459 }, 2460 }; 2461 2462 static struct clk_regmap gxbb_cts_vdac = { 2463 .data = &(struct clk_regmap_gate_data){ 2464 .offset = HHI_VID_CLK_CNTL2, 2465 .bit_idx = 4, 2466 }, 2467 .hw.init = &(struct clk_init_data) { 2468 .name = "cts_vdac", 2469 .ops = &clk_regmap_gate_ops, 2470 .parent_hws = (const struct clk_hw *[]) { 2471 &gxbb_cts_vdac_sel.hw 2472 }, 2473 .num_parents = 1, 2474 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2475 }, 2476 }; 2477 2478 static struct clk_regmap gxbb_hdmi_tx = { 2479 .data = &(struct clk_regmap_gate_data){ 2480 .offset = HHI_VID_CLK_CNTL2, 2481 .bit_idx = 5, 2482 }, 2483 .hw.init = &(struct clk_init_data) { 2484 .name = "hdmi_tx", 2485 .ops = &clk_regmap_gate_ops, 2486 .parent_hws = (const struct clk_hw *[]) { 2487 &gxbb_hdmi_tx_sel.hw 2488 }, 2489 .num_parents = 1, 2490 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2491 }, 2492 }; 2493 2494 /* HDMI Clocks */ 2495 2496 static const struct clk_parent_data gxbb_hdmi_parent_data[] = { 2497 { .fw_name = "xtal", }, 2498 { .hw = &gxbb_fclk_div4.hw }, 2499 { .hw = &gxbb_fclk_div3.hw }, 2500 { .hw = &gxbb_fclk_div5.hw }, 2501 }; 2502 2503 static struct clk_regmap gxbb_hdmi_sel = { 2504 .data = &(struct clk_regmap_mux_data){ 2505 .offset = HHI_HDMI_CLK_CNTL, 2506 .mask = 0x3, 2507 .shift = 9, 2508 .flags = CLK_MUX_ROUND_CLOSEST, 2509 }, 2510 .hw.init = &(struct clk_init_data){ 2511 .name = "hdmi_sel", 2512 .ops = &clk_regmap_mux_ops, 2513 .parent_data = gxbb_hdmi_parent_data, 2514 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data), 2515 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2516 }, 2517 }; 2518 2519 static struct clk_regmap gxbb_hdmi_div = { 2520 .data = &(struct clk_regmap_div_data){ 2521 .offset = HHI_HDMI_CLK_CNTL, 2522 .shift = 0, 2523 .width = 7, 2524 }, 2525 .hw.init = &(struct clk_init_data){ 2526 .name = "hdmi_div", 2527 .ops = &clk_regmap_divider_ops, 2528 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw }, 2529 .num_parents = 1, 2530 .flags = CLK_GET_RATE_NOCACHE, 2531 }, 2532 }; 2533 2534 static struct clk_regmap gxbb_hdmi = { 2535 .data = &(struct clk_regmap_gate_data){ 2536 .offset = HHI_HDMI_CLK_CNTL, 2537 .bit_idx = 8, 2538 }, 2539 .hw.init = &(struct clk_init_data) { 2540 .name = "hdmi", 2541 .ops = &clk_regmap_gate_ops, 2542 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw }, 2543 .num_parents = 1, 2544 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2545 }, 2546 }; 2547 2548 /* VDEC clocks */ 2549 2550 static const struct clk_hw *gxbb_vdec_parent_hws[] = { 2551 &gxbb_fclk_div4.hw, 2552 &gxbb_fclk_div3.hw, 2553 &gxbb_fclk_div5.hw, 2554 &gxbb_fclk_div7.hw, 2555 }; 2556 2557 static struct clk_regmap gxbb_vdec_1_sel = { 2558 .data = &(struct clk_regmap_mux_data){ 2559 .offset = HHI_VDEC_CLK_CNTL, 2560 .mask = 0x3, 2561 .shift = 9, 2562 .flags = CLK_MUX_ROUND_CLOSEST, 2563 }, 2564 .hw.init = &(struct clk_init_data){ 2565 .name = "vdec_1_sel", 2566 .ops = &clk_regmap_mux_ops, 2567 .parent_hws = gxbb_vdec_parent_hws, 2568 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws), 2569 .flags = CLK_SET_RATE_PARENT, 2570 }, 2571 }; 2572 2573 static struct clk_regmap gxbb_vdec_1_div = { 2574 .data = &(struct clk_regmap_div_data){ 2575 .offset = HHI_VDEC_CLK_CNTL, 2576 .shift = 0, 2577 .width = 7, 2578 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2579 }, 2580 .hw.init = &(struct clk_init_data){ 2581 .name = "vdec_1_div", 2582 .ops = &clk_regmap_divider_ops, 2583 .parent_hws = (const struct clk_hw *[]) { 2584 &gxbb_vdec_1_sel.hw 2585 }, 2586 .num_parents = 1, 2587 .flags = CLK_SET_RATE_PARENT, 2588 }, 2589 }; 2590 2591 static struct clk_regmap gxbb_vdec_1 = { 2592 .data = &(struct clk_regmap_gate_data){ 2593 .offset = HHI_VDEC_CLK_CNTL, 2594 .bit_idx = 8, 2595 }, 2596 .hw.init = &(struct clk_init_data) { 2597 .name = "vdec_1", 2598 .ops = &clk_regmap_gate_ops, 2599 .parent_hws = (const struct clk_hw *[]) { 2600 &gxbb_vdec_1_div.hw 2601 }, 2602 .num_parents = 1, 2603 .flags = CLK_SET_RATE_PARENT, 2604 }, 2605 }; 2606 2607 static struct clk_regmap gxbb_vdec_hevc_sel = { 2608 .data = &(struct clk_regmap_mux_data){ 2609 .offset = HHI_VDEC2_CLK_CNTL, 2610 .mask = 0x3, 2611 .shift = 25, 2612 .flags = CLK_MUX_ROUND_CLOSEST, 2613 }, 2614 .hw.init = &(struct clk_init_data){ 2615 .name = "vdec_hevc_sel", 2616 .ops = &clk_regmap_mux_ops, 2617 .parent_hws = gxbb_vdec_parent_hws, 2618 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws), 2619 .flags = CLK_SET_RATE_PARENT, 2620 }, 2621 }; 2622 2623 static struct clk_regmap gxbb_vdec_hevc_div = { 2624 .data = &(struct clk_regmap_div_data){ 2625 .offset = HHI_VDEC2_CLK_CNTL, 2626 .shift = 16, 2627 .width = 7, 2628 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2629 }, 2630 .hw.init = &(struct clk_init_data){ 2631 .name = "vdec_hevc_div", 2632 .ops = &clk_regmap_divider_ops, 2633 .parent_hws = (const struct clk_hw *[]) { 2634 &gxbb_vdec_hevc_sel.hw 2635 }, 2636 .num_parents = 1, 2637 .flags = CLK_SET_RATE_PARENT, 2638 }, 2639 }; 2640 2641 static struct clk_regmap gxbb_vdec_hevc = { 2642 .data = &(struct clk_regmap_gate_data){ 2643 .offset = HHI_VDEC2_CLK_CNTL, 2644 .bit_idx = 24, 2645 }, 2646 .hw.init = &(struct clk_init_data) { 2647 .name = "vdec_hevc", 2648 .ops = &clk_regmap_gate_ops, 2649 .parent_hws = (const struct clk_hw *[]) { 2650 &gxbb_vdec_hevc_div.hw 2651 }, 2652 .num_parents = 1, 2653 .flags = CLK_SET_RATE_PARENT, 2654 }, 2655 }; 2656 2657 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 2658 9, 10, 11, 13, 14, }; 2659 static const struct clk_parent_data gen_clk_parent_data[] = { 2660 { .fw_name = "xtal", }, 2661 { .hw = &gxbb_vdec_1.hw }, 2662 { .hw = &gxbb_vdec_hevc.hw }, 2663 { .hw = &gxbb_mpll0.hw }, 2664 { .hw = &gxbb_mpll1.hw }, 2665 { .hw = &gxbb_mpll2.hw }, 2666 { .hw = &gxbb_fclk_div4.hw }, 2667 { .hw = &gxbb_fclk_div3.hw }, 2668 { .hw = &gxbb_fclk_div5.hw }, 2669 { .hw = &gxbb_fclk_div7.hw }, 2670 { .hw = &gxbb_gp0_pll.hw }, 2671 }; 2672 2673 static struct clk_regmap gxbb_gen_clk_sel = { 2674 .data = &(struct clk_regmap_mux_data){ 2675 .offset = HHI_GEN_CLK_CNTL, 2676 .mask = 0xf, 2677 .shift = 12, 2678 .table = mux_table_gen_clk, 2679 }, 2680 .hw.init = &(struct clk_init_data){ 2681 .name = "gen_clk_sel", 2682 .ops = &clk_regmap_mux_ops, 2683 /* 2684 * bits 15:12 selects from 14 possible parents: 2685 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 2686 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 2687 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 2688 */ 2689 .parent_data = gen_clk_parent_data, 2690 .num_parents = ARRAY_SIZE(gen_clk_parent_data), 2691 }, 2692 }; 2693 2694 static struct clk_regmap gxbb_gen_clk_div = { 2695 .data = &(struct clk_regmap_div_data){ 2696 .offset = HHI_GEN_CLK_CNTL, 2697 .shift = 0, 2698 .width = 11, 2699 }, 2700 .hw.init = &(struct clk_init_data){ 2701 .name = "gen_clk_div", 2702 .ops = &clk_regmap_divider_ops, 2703 .parent_hws = (const struct clk_hw *[]) { 2704 &gxbb_gen_clk_sel.hw 2705 }, 2706 .num_parents = 1, 2707 .flags = CLK_SET_RATE_PARENT, 2708 }, 2709 }; 2710 2711 static struct clk_regmap gxbb_gen_clk = { 2712 .data = &(struct clk_regmap_gate_data){ 2713 .offset = HHI_GEN_CLK_CNTL, 2714 .bit_idx = 7, 2715 }, 2716 .hw.init = &(struct clk_init_data){ 2717 .name = "gen_clk", 2718 .ops = &clk_regmap_gate_ops, 2719 .parent_hws = (const struct clk_hw *[]) { 2720 &gxbb_gen_clk_div.hw 2721 }, 2722 .num_parents = 1, 2723 .flags = CLK_SET_RATE_PARENT, 2724 }, 2725 }; 2726 2727 #define MESON_GATE(_name, _reg, _bit) \ 2728 MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw) 2729 2730 /* Everything Else (EE) domain gates */ 2731 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 2732 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 2733 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 2734 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 2735 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 2736 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 2737 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 2738 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); 2739 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 2740 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 2741 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 2742 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 2743 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 2744 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 2745 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 2746 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 2747 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 2748 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 2749 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 2750 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 2751 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 2752 static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28); 2753 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 2754 2755 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 2756 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 2757 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 2758 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 2759 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 2760 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 2761 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 2762 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 2763 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 2764 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 2765 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 2766 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 2767 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 2768 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 2769 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 2770 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 2771 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 2772 2773 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 2774 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 2775 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 2776 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 2777 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 2778 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 2779 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 2780 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 2781 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 2782 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); 2783 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 2784 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 2785 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 2786 2787 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 2788 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 2789 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 2790 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 2791 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 2792 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 2793 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 2794 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 2795 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 2796 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 2797 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 2798 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 2799 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 2800 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 2801 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 2802 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 2803 2804 /* Always On (AO) domain gates */ 2805 2806 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 2807 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 2808 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 2809 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 2810 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 2811 2812 /* AIU gates */ 2813 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw); 2814 static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw); 2815 static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw); 2816 static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw); 2817 static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw); 2818 static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw); 2819 static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw); 2820 static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw); 2821 2822 /* Array of all clocks provided by this provider */ 2823 2824 static struct clk_hw *gxbb_hw_clks[] = { 2825 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2826 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2827 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2828 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2829 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2830 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2831 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2832 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2833 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2834 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2835 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2836 [CLKID_CLK81] = &gxbb_clk81.hw, 2837 [CLKID_MPLL0] = &gxbb_mpll0.hw, 2838 [CLKID_MPLL1] = &gxbb_mpll1.hw, 2839 [CLKID_MPLL2] = &gxbb_mpll2.hw, 2840 [CLKID_DDR] = &gxbb_ddr.hw, 2841 [CLKID_DOS] = &gxbb_dos.hw, 2842 [CLKID_ISA] = &gxbb_isa.hw, 2843 [CLKID_PL301] = &gxbb_pl301.hw, 2844 [CLKID_PERIPHS] = &gxbb_periphs.hw, 2845 [CLKID_SPICC] = &gxbb_spicc.hw, 2846 [CLKID_I2C] = &gxbb_i2c.hw, 2847 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2848 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2849 [CLKID_RNG0] = &gxbb_rng0.hw, 2850 [CLKID_UART0] = &gxbb_uart0.hw, 2851 [CLKID_SDHC] = &gxbb_sdhc.hw, 2852 [CLKID_STREAM] = &gxbb_stream.hw, 2853 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2854 [CLKID_SDIO] = &gxbb_sdio.hw, 2855 [CLKID_ABUF] = &gxbb_abuf.hw, 2856 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2857 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2858 [CLKID_SPI] = &gxbb_spi.hw, 2859 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2860 [CLKID_ETH] = &gxbb_eth.hw, 2861 [CLKID_DEMUX] = &gxbb_demux.hw, 2862 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2863 [CLKID_IEC958] = &gxbb_iec958.hw, 2864 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2865 [CLKID_AMCLK] = &gxbb_amclk.hw, 2866 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2867 [CLKID_MIXER] = &gxbb_mixer.hw, 2868 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2869 [CLKID_ADC] = &gxbb_adc.hw, 2870 [CLKID_BLKMV] = &gxbb_blkmv.hw, 2871 [CLKID_AIU] = &gxbb_aiu.hw, 2872 [CLKID_UART1] = &gxbb_uart1.hw, 2873 [CLKID_G2D] = &gxbb_g2d.hw, 2874 [CLKID_USB0] = &gxbb_usb0.hw, 2875 [CLKID_USB1] = &gxbb_usb1.hw, 2876 [CLKID_RESET] = &gxbb_reset.hw, 2877 [CLKID_NAND] = &gxbb_nand.hw, 2878 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2879 [CLKID_USB] = &gxbb_usb.hw, 2880 [CLKID_VDIN1] = &gxbb_vdin1.hw, 2881 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2882 [CLKID_EFUSE] = &gxbb_efuse.hw, 2883 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2884 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2885 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2886 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2887 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2888 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2889 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2890 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2891 [CLKID_DVIN] = &gxbb_dvin.hw, 2892 [CLKID_UART2] = &gxbb_uart2.hw, 2893 [CLKID_SANA] = &gxbb_sana.hw, 2894 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2895 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2896 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2897 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2898 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2899 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2900 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2901 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2902 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2903 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2904 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2905 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2906 [CLKID_ENC480P] = &gxbb_enc480p.hw, 2907 [CLKID_RNG1] = &gxbb_rng1.hw, 2908 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2909 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2910 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2911 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2912 [CLKID_EDP] = &gxbb_edp.hw, 2913 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2914 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2915 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2916 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2917 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2918 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2919 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2920 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2921 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2922 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2923 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2924 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2925 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2926 [CLKID_MALI_0] = &gxbb_mali_0.hw, 2927 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2928 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2929 [CLKID_MALI_1] = &gxbb_mali_1.hw, 2930 [CLKID_MALI] = &gxbb_mali.hw, 2931 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2932 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2933 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2934 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2935 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2936 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2937 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2938 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2939 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2940 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2941 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2942 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2943 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2944 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2945 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2946 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2947 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2948 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2949 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2950 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2951 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2952 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2953 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2954 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2955 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2956 [CLKID_VPU] = &gxbb_vpu.hw, 2957 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2958 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2959 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2960 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2961 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2962 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2963 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2964 [CLKID_VAPB] = &gxbb_vapb.hw, 2965 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2966 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2967 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2968 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2969 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2970 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2971 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2972 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2973 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2974 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2975 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2976 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2977 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2978 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2979 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2980 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 2981 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 2982 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 2983 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 2984 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 2985 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 2986 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 2987 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 2988 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 2989 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 2990 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 2991 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 2992 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 2993 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 2994 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 2995 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 2996 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 2997 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 2998 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 2999 [CLKID_VCLK] = &gxbb_vclk.hw, 3000 [CLKID_VCLK2] = &gxbb_vclk2.hw, 3001 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3002 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3003 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3004 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3005 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3006 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3007 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3008 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3009 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3010 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3011 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3012 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3013 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3014 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3015 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3016 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3017 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3018 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3019 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3020 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3021 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3022 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3023 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3024 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3025 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3026 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3027 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3028 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3029 [CLKID_HDMI] = &gxbb_hdmi.hw, 3030 }; 3031 3032 static struct clk_hw *gxl_hw_clks[] = { 3033 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 3034 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 3035 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 3036 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 3037 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 3038 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 3039 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 3040 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 3041 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 3042 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 3043 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 3044 [CLKID_CLK81] = &gxbb_clk81.hw, 3045 [CLKID_MPLL0] = &gxbb_mpll0.hw, 3046 [CLKID_MPLL1] = &gxbb_mpll1.hw, 3047 [CLKID_MPLL2] = &gxbb_mpll2.hw, 3048 [CLKID_DDR] = &gxbb_ddr.hw, 3049 [CLKID_DOS] = &gxbb_dos.hw, 3050 [CLKID_ISA] = &gxbb_isa.hw, 3051 [CLKID_PL301] = &gxbb_pl301.hw, 3052 [CLKID_PERIPHS] = &gxbb_periphs.hw, 3053 [CLKID_SPICC] = &gxbb_spicc.hw, 3054 [CLKID_I2C] = &gxbb_i2c.hw, 3055 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 3056 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 3057 [CLKID_RNG0] = &gxbb_rng0.hw, 3058 [CLKID_UART0] = &gxbb_uart0.hw, 3059 [CLKID_SDHC] = &gxbb_sdhc.hw, 3060 [CLKID_STREAM] = &gxbb_stream.hw, 3061 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 3062 [CLKID_SDIO] = &gxbb_sdio.hw, 3063 [CLKID_ABUF] = &gxbb_abuf.hw, 3064 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 3065 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 3066 [CLKID_SPI] = &gxbb_spi.hw, 3067 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 3068 [CLKID_ETH] = &gxbb_eth.hw, 3069 [CLKID_DEMUX] = &gxbb_demux.hw, 3070 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 3071 [CLKID_IEC958] = &gxbb_iec958.hw, 3072 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 3073 [CLKID_AMCLK] = &gxbb_amclk.hw, 3074 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 3075 [CLKID_MIXER] = &gxbb_mixer.hw, 3076 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 3077 [CLKID_ADC] = &gxbb_adc.hw, 3078 [CLKID_BLKMV] = &gxbb_blkmv.hw, 3079 [CLKID_AIU] = &gxbb_aiu.hw, 3080 [CLKID_UART1] = &gxbb_uart1.hw, 3081 [CLKID_G2D] = &gxbb_g2d.hw, 3082 [CLKID_USB0] = &gxbb_usb0.hw, 3083 [CLKID_USB1] = &gxbb_usb1.hw, 3084 [CLKID_RESET] = &gxbb_reset.hw, 3085 [CLKID_NAND] = &gxbb_nand.hw, 3086 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 3087 [CLKID_USB] = &gxbb_usb.hw, 3088 [CLKID_VDIN1] = &gxbb_vdin1.hw, 3089 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 3090 [CLKID_EFUSE] = &gxbb_efuse.hw, 3091 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 3092 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 3093 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 3094 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 3095 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 3096 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 3097 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 3098 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 3099 [CLKID_DVIN] = &gxbb_dvin.hw, 3100 [CLKID_UART2] = &gxbb_uart2.hw, 3101 [CLKID_SANA] = &gxbb_sana.hw, 3102 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 3103 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 3104 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 3105 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 3106 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 3107 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 3108 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 3109 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 3110 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 3111 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 3112 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 3113 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 3114 [CLKID_ENC480P] = &gxbb_enc480p.hw, 3115 [CLKID_RNG1] = &gxbb_rng1.hw, 3116 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 3117 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 3118 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 3119 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 3120 [CLKID_EDP] = &gxbb_edp.hw, 3121 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 3122 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 3123 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 3124 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 3125 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 3126 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 3127 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 3128 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 3129 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 3130 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 3131 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 3132 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 3133 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 3134 [CLKID_MALI_0] = &gxbb_mali_0.hw, 3135 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 3136 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 3137 [CLKID_MALI_1] = &gxbb_mali_1.hw, 3138 [CLKID_MALI] = &gxbb_mali.hw, 3139 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 3140 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 3141 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 3142 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 3143 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 3144 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 3145 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 3146 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 3147 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 3148 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 3149 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 3150 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 3151 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 3152 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 3153 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 3154 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 3155 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 3156 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 3157 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 3158 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 3159 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 3160 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 3161 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 3162 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 3163 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 3164 [CLKID_VPU] = &gxbb_vpu.hw, 3165 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 3166 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 3167 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 3168 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 3169 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 3170 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 3171 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 3172 [CLKID_VAPB] = &gxbb_vapb.hw, 3173 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw, 3174 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 3175 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 3176 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 3177 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 3178 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 3179 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 3180 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 3181 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3182 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3183 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3184 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3185 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3186 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3187 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 3188 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 3189 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 3190 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 3191 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 3192 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 3193 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 3194 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 3195 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 3196 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 3197 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3198 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3199 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3200 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3201 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3202 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3203 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3204 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3205 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3206 [CLKID_VCLK] = &gxbb_vclk.hw, 3207 [CLKID_VCLK2] = &gxbb_vclk2.hw, 3208 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3209 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3210 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3211 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3212 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3213 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3214 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3215 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3216 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3217 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3218 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3219 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3220 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3221 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3222 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3223 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3224 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3225 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3226 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3227 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3228 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3229 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3230 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3231 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3232 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3233 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3234 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3235 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3236 [CLKID_HDMI] = &gxbb_hdmi.hw, 3237 [CLKID_ACODEC] = &gxl_acodec.hw, 3238 }; 3239 3240 static const struct meson_eeclkc_data gxbb_clkc_data = { 3241 .hw_clks = { 3242 .hws = gxbb_hw_clks, 3243 .num = ARRAY_SIZE(gxbb_hw_clks), 3244 }, 3245 }; 3246 3247 static const struct meson_eeclkc_data gxl_clkc_data = { 3248 .hw_clks = { 3249 .hws = gxl_hw_clks, 3250 .num = ARRAY_SIZE(gxl_hw_clks), 3251 }, 3252 }; 3253 3254 static const struct of_device_id clkc_match_table[] = { 3255 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 3256 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 3257 {}, 3258 }; 3259 MODULE_DEVICE_TABLE(of, clkc_match_table); 3260 3261 static struct platform_driver gxbb_driver = { 3262 .probe = meson_eeclkc_probe, 3263 .driver = { 3264 .name = "gxbb-clkc", 3265 .of_match_table = clkc_match_table, 3266 }, 3267 }; 3268 module_platform_driver(gxbb_driver); 3269 3270 MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver"); 3271 MODULE_LICENSE("GPL"); 3272 MODULE_IMPORT_NS("CLK_MESON"); 3273