1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_HAL_RX_H
8 #define ATH12K_HAL_RX_H
9
10 struct hal_rx_wbm_rel_info {
11 u32 cookie;
12 enum hal_wbm_rel_src_module err_rel_src;
13 enum hal_reo_dest_ring_push_reason push_reason;
14 u32 err_code;
15 bool first_msdu;
16 bool last_msdu;
17 bool continuation;
18 void *rx_desc;
19 bool hw_cc_done;
20 };
21
22 #define HAL_INVALID_PEERID 0x3fff
23 #define VHT_SIG_SU_NSS_MASK 0x7
24
25 #define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \
26 le32_get_bits((__val), GENMASK(7, 0))
27
28 #define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \
29 le32_get_bits((__val), GENMASK(15, 8))
30
31 #define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \
32 le32_get_bits((__val), GENMASK(23, 16))
33
34 #define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \
35 le32_get_bits((__val), GENMASK(31, 24))
36
37 struct hal_rx_mon_status_tlv_hdr {
38 u32 hdr;
39 u8 value[];
40 };
41
42 enum hal_rx_su_mu_coding {
43 HAL_RX_SU_MU_CODING_BCC,
44 HAL_RX_SU_MU_CODING_LDPC,
45 HAL_RX_SU_MU_CODING_MAX,
46 };
47
48 enum hal_rx_gi {
49 HAL_RX_GI_0_8_US,
50 HAL_RX_GI_0_4_US,
51 HAL_RX_GI_1_6_US,
52 HAL_RX_GI_3_2_US,
53 HAL_RX_GI_MAX,
54 };
55
56 enum hal_rx_bw {
57 HAL_RX_BW_20MHZ,
58 HAL_RX_BW_40MHZ,
59 HAL_RX_BW_80MHZ,
60 HAL_RX_BW_160MHZ,
61 HAL_RX_BW_320MHZ,
62 HAL_RX_BW_MAX,
63 };
64
65 enum hal_rx_preamble {
66 HAL_RX_PREAMBLE_11A,
67 HAL_RX_PREAMBLE_11B,
68 HAL_RX_PREAMBLE_11N,
69 HAL_RX_PREAMBLE_11AC,
70 HAL_RX_PREAMBLE_11AX,
71 HAL_RX_PREAMBLE_11BA,
72 HAL_RX_PREAMBLE_11BE,
73 HAL_RX_PREAMBLE_MAX,
74 };
75
76 enum hal_rx_reception_type {
77 HAL_RX_RECEPTION_TYPE_SU,
78 HAL_RX_RECEPTION_TYPE_MU_MIMO,
79 HAL_RX_RECEPTION_TYPE_MU_OFDMA,
80 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
81 HAL_RX_RECEPTION_TYPE_MAX,
82 };
83
84 enum hal_rx_legacy_rate {
85 HAL_RX_LEGACY_RATE_1_MBPS,
86 HAL_RX_LEGACY_RATE_2_MBPS,
87 HAL_RX_LEGACY_RATE_5_5_MBPS,
88 HAL_RX_LEGACY_RATE_6_MBPS,
89 HAL_RX_LEGACY_RATE_9_MBPS,
90 HAL_RX_LEGACY_RATE_11_MBPS,
91 HAL_RX_LEGACY_RATE_12_MBPS,
92 HAL_RX_LEGACY_RATE_18_MBPS,
93 HAL_RX_LEGACY_RATE_24_MBPS,
94 HAL_RX_LEGACY_RATE_36_MBPS,
95 HAL_RX_LEGACY_RATE_48_MBPS,
96 HAL_RX_LEGACY_RATE_54_MBPS,
97 HAL_RX_LEGACY_RATE_INVALID,
98 };
99
100 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
101 #define HAL_TLV_STATUS_PPDU_DONE 1
102 #define HAL_TLV_STATUS_BUF_DONE 2
103 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3
104 #define HAL_RX_FCS_LEN 4
105
106 enum hal_rx_mon_status {
107 HAL_RX_MON_STATUS_PPDU_NOT_DONE,
108 HAL_RX_MON_STATUS_PPDU_DONE,
109 HAL_RX_MON_STATUS_BUF_DONE,
110 HAL_RX_MON_STATUS_BUF_ADDR,
111 HAL_RX_MON_STATUS_MPDU_START,
112 HAL_RX_MON_STATUS_MPDU_END,
113 HAL_RX_MON_STATUS_MSDU_END,
114 };
115
116 #define HAL_RX_MAX_MPDU 1024
117 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5)
118
119 struct hal_rx_user_status {
120 u32 mcs:4,
121 nss:3,
122 ofdma_info_valid:1,
123 ul_ofdma_ru_start_index:7,
124 ul_ofdma_ru_width:7,
125 ul_ofdma_ru_size:8;
126 u32 ul_ofdma_user_v0_word0;
127 u32 ul_ofdma_user_v0_word1;
128 u32 ast_index;
129 u32 tid;
130 u16 tcp_msdu_count;
131 u16 tcp_ack_msdu_count;
132 u16 udp_msdu_count;
133 u16 other_msdu_count;
134 u16 frame_control;
135 u8 frame_control_info_valid;
136 u8 data_sequence_control_info_valid;
137 u16 first_data_seq_ctrl;
138 u32 preamble_type;
139 u16 ht_flags;
140 u16 vht_flags;
141 u16 he_flags;
142 u8 rs_flags;
143 u8 ldpc;
144 u32 mpdu_cnt_fcs_ok;
145 u32 mpdu_cnt_fcs_err;
146 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
147 u32 mpdu_ok_byte_count;
148 u32 mpdu_err_byte_count;
149 bool ampdu_present;
150 u16 ampdu_id;
151 };
152
153 #define HAL_MAX_UL_MU_USERS 37
154
155 struct hal_rx_u_sig_info {
156 bool ul_dl;
157 u8 bw;
158 u8 ppdu_type_comp_mode;
159 u8 eht_sig_mcs;
160 u8 num_eht_sig_sym;
161 struct ieee80211_radiotap_eht_usig usig;
162 };
163
164 #define HAL_RX_MON_MAX_AGGR_SIZE 128
165
166 struct hal_rx_tlv_aggr_info {
167 bool in_progress;
168 u16 cur_len;
169 u16 tlv_tag;
170 u8 buf[HAL_RX_MON_MAX_AGGR_SIZE];
171 };
172
173 struct hal_rx_radiotap_eht {
174 __le32 known;
175 __le32 data[9];
176 };
177
178 #define EHT_MAX_USER_INFO 4
179
180 struct hal_rx_eht_info {
181 u8 num_user_info;
182 struct hal_rx_radiotap_eht eht;
183 u32 user_info[EHT_MAX_USER_INFO];
184 };
185
186 struct hal_rx_mon_ppdu_info {
187 u32 ppdu_id;
188 u32 last_ppdu_id;
189 u64 ppdu_ts;
190 u32 num_mpdu_fcs_ok;
191 u32 num_mpdu_fcs_err;
192 u32 preamble_type;
193 u32 mpdu_len;
194 u16 chan_num;
195 u16 freq;
196 u16 tcp_msdu_count;
197 u16 tcp_ack_msdu_count;
198 u16 udp_msdu_count;
199 u16 other_msdu_count;
200 u16 peer_id;
201 u8 rate;
202 u8 mcs;
203 u8 nss;
204 u8 bw;
205 u8 vht_flag_values1;
206 u8 vht_flag_values2;
207 u8 vht_flag_values3[4];
208 u8 vht_flag_values4;
209 u8 vht_flag_values5;
210 u16 vht_flag_values6;
211 u8 is_stbc;
212 u8 gi;
213 u8 sgi;
214 u8 ldpc;
215 u8 beamformed;
216 u8 rssi_comb;
217 u16 tid;
218 u8 fc_valid;
219 u16 ht_flags;
220 u16 vht_flags;
221 u16 he_flags;
222 u16 he_mu_flags;
223 u8 dcm;
224 u8 ru_alloc;
225 u8 reception_type;
226 u64 tsft;
227 u64 rx_duration;
228 u16 frame_control;
229 u32 ast_index;
230 u8 rs_fcs_err;
231 u8 rs_flags;
232 u8 cck_flag;
233 u8 ofdm_flag;
234 u8 ulofdma_flag;
235 u8 frame_control_info_valid;
236 u16 he_per_user_1;
237 u16 he_per_user_2;
238 u8 he_per_user_position;
239 u8 he_per_user_known;
240 u16 he_flags1;
241 u16 he_flags2;
242 u8 he_RU[4];
243 u16 he_data1;
244 u16 he_data2;
245 u16 he_data3;
246 u16 he_data4;
247 u16 he_data5;
248 u16 he_data6;
249 u32 ppdu_len;
250 u32 prev_ppdu_id;
251 u32 device_id;
252 u16 first_data_seq_ctrl;
253 u8 monitor_direct_used;
254 u8 data_sequence_control_info_valid;
255 u8 ltf_size;
256 u8 rxpcu_filter_pass;
257 s8 rssi_chain[8][8];
258 u32 num_users;
259 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
260 u8 addr1[ETH_ALEN];
261 u8 addr2[ETH_ALEN];
262 u8 addr3[ETH_ALEN];
263 u8 addr4[ETH_ALEN];
264 struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS];
265 u8 userid;
266 bool first_msdu_in_mpdu;
267 bool is_ampdu;
268 u8 medium_prot_type;
269 bool ppdu_continuation;
270 bool eht_usig;
271 struct hal_rx_u_sig_info u_sig_info;
272 bool is_eht;
273 struct hal_rx_eht_info eht_info;
274 struct hal_rx_tlv_aggr_info tlv_aggr;
275 };
276
277 #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
278 #define HAL_RX_PPDU_START_INFO1_CHAN_NUM GENMASK(15, 0)
279 #define HAL_RX_PPDU_START_INFO1_CHAN_FREQ GENMASK(31, 16)
280
281 struct hal_rx_ppdu_start {
282 __le32 info0;
283 __le32 info1;
284 __le32 ppdu_start_ts_31_0;
285 __le32 ppdu_start_ts_63_32;
286 __le32 rsvd[2];
287 } __packed;
288
289 #define HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID GENMASK(13, 0)
290 #define HAL_RX_PPDU_END_USER_STATS_INFO0_DEVICE_ID GENMASK(15, 14)
291 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(26, 16)
292
293 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(10, 0)
294 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(11)
295 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(12)
296 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(13)
297 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(24, 21)
298
299 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
300 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
301
302 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)
303
304 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)
305 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)
306
307 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)
308 #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)
309
310 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0)
311 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16)
312
313 #define HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT GENMASK(24, 0)
314 #define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT GENMASK(24, 0)
315
316 struct hal_rx_ppdu_end_user_stats {
317 __le32 rsvd0[2];
318 __le32 info0;
319 __le32 info1;
320 __le32 info2;
321 __le32 info3;
322 __le32 ht_ctrl;
323 __le32 rsvd1[2];
324 __le32 info4;
325 __le32 info5;
326 __le32 usr_resp_ref;
327 __le32 info6;
328 __le32 rsvd3[4];
329 __le32 info7;
330 __le32 rsvd4;
331 __le32 info8;
332 __le32 rsvd5[2];
333 __le32 usr_resp_ref_ext;
334 __le32 rsvd6;
335 } __packed;
336
337 struct hal_rx_ppdu_end_user_stats_ext {
338 __le32 info0;
339 __le32 info1;
340 __le32 info2;
341 __le32 info3;
342 __le32 info4;
343 __le32 info5;
344 __le32 info6;
345 __le32 rsvd;
346 } __packed;
347
348 #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
349 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
350
351 #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
352 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
353 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
354
355 struct hal_rx_ht_sig_info {
356 __le32 info0;
357 __le32 info1;
358 } __packed;
359
360 #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
361 #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
362
363 struct hal_rx_lsig_b_info {
364 __le32 info0;
365 } __packed;
366
367 #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
368 #define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)
369 #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)
370
371 struct hal_rx_lsig_a_info {
372 __le32 info0;
373 } __packed;
374
375 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)
376 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
377 #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)
378 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
379
380 #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)
381 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2)
382 #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)
383 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8)
384
385 struct hal_rx_vht_sig_a_info {
386 __le32 info0;
387 __le32 info1;
388 } __packed;
389
390 enum hal_rx_vht_sig_a_gi_setting {
391 HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
392 HAL_RX_VHT_SIG_A_SHORT_GI = 1,
393 HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
394 };
395
396 #define HE_GI_0_8 0
397 #define HE_GI_0_4 1
398 #define HE_GI_1_6 2
399 #define HE_GI_3_2 3
400
401 #define HE_LTF_1_X 0
402 #define HE_LTF_2_X 1
403 #define HE_LTF_4_X 2
404
405 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)
406 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7)
407 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)
408 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)
409 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)
410 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)
411 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)
412 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0)
413 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1)
414 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2)
415
416 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
417 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7)
418 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8)
419 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9)
420 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10)
421 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)
422 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13)
423 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15)
424
425 struct hal_rx_he_sig_a_su_info {
426 __le32 info0;
427 __le32 info1;
428 } __packed;
429
430 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG BIT(1)
431 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB GENMASK(3, 1)
432 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB BIT(4)
433 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5)
434 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE GENMASK(14, 11)
435 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW GENMASK(17, 15)
436 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)
437 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB BIT(22)
438 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE GENMASK(24, 23)
439 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25)
440
441 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0)
442 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8)
443 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA BIT(11)
444 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12)
445 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)
446 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15)
447
448 struct hal_rx_he_sig_a_mu_dl_info {
449 __le32 info0;
450 __le32 info1;
451 } __packed;
452
453 #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)
454
455 struct hal_rx_he_sig_b1_mu_info {
456 __le32 info0;
457 } __packed;
458
459 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)
460 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)
461 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20)
462 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)
463
464 struct hal_rx_he_sig_b2_mu_info {
465 __le32 info0;
466 } __packed;
467
468 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)
469 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)
470 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(14)
471 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)
472 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19)
473 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20)
474
475 struct hal_rx_he_sig_b2_ofdma_info {
476 __le32 info0;
477 } __packed;
478
479 enum hal_rx_ul_reception_type {
480 HAL_RECEPTION_TYPE_ULOFMDA,
481 HAL_RECEPTION_TYPE_ULMIMO,
482 HAL_RECEPTION_TYPE_OTHER,
483 HAL_RECEPTION_TYPE_FRAMELESS
484 };
485
486 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RECEPTION GENMASK(3, 0)
487 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW GENMASK(7, 5)
488 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8)
489
490 struct hal_rx_phyrx_rssi_legacy_info {
491 __le32 info0;
492 __le32 rsvd0[39];
493 __le32 info1;
494 __le32 rsvd1;
495 } __packed;
496
497 #define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16)
498 #define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(29, 16)
499 #define HAL_RX_MPDU_START_INFO1_DEVICE_ID GENMASK(31, 30)
500 #define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0)
501 struct hal_rx_mpdu_start {
502 __le32 rsvd0[9];
503 __le32 info0;
504 __le32 info1;
505 __le32 rsvd1[2];
506 __le32 info2;
507 __le32 rsvd2[16];
508 } __packed;
509
510 struct hal_rx_msdu_end {
511 __le32 info0;
512 __le32 rsvd0[9];
513 __le16 info00;
514 __le16 info01;
515 __le32 rsvd00[8];
516 __le32 info1;
517 __le32 rsvd1[10];
518 __le32 info2;
519 __le32 rsvd2;
520 } __packed;
521
522 #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
523 struct hal_rx_ppdu_end_duration {
524 __le32 rsvd0[9];
525 __le32 info0;
526 __le32 rsvd1[18];
527 } __packed;
528
529 struct hal_rx_rxpcu_classification_overview {
530 u32 rsvd0;
531 } __packed;
532
533 struct hal_rx_msdu_desc_info {
534 u32 msdu_flags;
535 u16 msdu_len; /* 14 bits for length */
536 };
537
538 #define HAL_RX_NUM_MSDU_DESC 6
539 struct hal_rx_msdu_list {
540 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
541 u64 paddr[HAL_RX_NUM_MSDU_DESC];
542 u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
543 u8 rbm[HAL_RX_NUM_MSDU_DESC];
544 };
545
546 #define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 GENMASK(31, 0)
547 #define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 GENMASK(15, 0)
548 #define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 GENMASK(31, 16)
549 #define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 GENMASK(31, 0)
550
551 struct hal_rx_frame_bitmap_ack {
552 __le32 reserved;
553 __le32 info0;
554 __le32 info1;
555 __le32 info2;
556 __le32 reserved1[10];
557 } __packed;
558
559 #define HAL_RX_RESP_REQ_INFO0_PPDU_ID GENMASK(15, 0)
560 #define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE BIT(16)
561 #define HAL_RX_RESP_REQ_INFO1_DURATION GENMASK(15, 0)
562 #define HAL_RX_RESP_REQ_INFO1_RATE_MCS GENMASK(24, 21)
563 #define HAL_RX_RESP_REQ_INFO1_SGI GENMASK(26, 25)
564 #define HAL_RX_RESP_REQ_INFO1_STBC BIT(27)
565 #define HAL_RX_RESP_REQ_INFO1_LDPC BIT(28)
566 #define HAL_RX_RESP_REQ_INFO1_IS_AMPDU BIT(29)
567 #define HAL_RX_RESP_REQ_INFO2_NUM_USER GENMASK(6, 0)
568 #define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 GENMASK(31, 0)
569 #define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 GENMASK(15, 0)
570 #define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 GENMASK(31, 16)
571 #define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 GENMASK(31, 0)
572
573 struct hal_rx_resp_req_info {
574 __le32 info0;
575 __le32 reserved[1];
576 __le32 info1;
577 __le32 info2;
578 __le32 reserved1[2];
579 __le32 info3;
580 __le32 info4;
581 __le32 info5;
582 __le32 reserved2[5];
583 } __packed;
584
585 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
586 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
587 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
588 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
589
590 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30)
591 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31)
592 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0)
593 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3)
594 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7)
595 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8)
596 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9)
597 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16)
598
599 /* HE Radiotap data1 Mask */
600 #define HE_SU_FORMAT_TYPE 0x0000
601 #define HE_EXT_SU_FORMAT_TYPE 0x0001
602 #define HE_MU_FORMAT_TYPE 0x0002
603 #define HE_TRIG_FORMAT_TYPE 0x0003
604 #define HE_BEAM_CHANGE_KNOWN 0x0008
605 #define HE_DL_UL_KNOWN 0x0010
606 #define HE_MCS_KNOWN 0x0020
607 #define HE_DCM_KNOWN 0x0040
608 #define HE_CODING_KNOWN 0x0080
609 #define HE_LDPC_EXTRA_SYMBOL_KNOWN 0x0100
610 #define HE_STBC_KNOWN 0x0200
611 #define HE_DATA_BW_RU_KNOWN 0x4000
612 #define HE_DOPPLER_KNOWN 0x8000
613 #define HE_BSS_COLOR_KNOWN 0x0004
614
615 /* HE Radiotap data2 Mask */
616 #define HE_GI_KNOWN 0x0002
617 #define HE_TXBF_KNOWN 0x0010
618 #define HE_PE_DISAMBIGUITY_KNOWN 0x0020
619 #define HE_TXOP_KNOWN 0x0040
620 #define HE_LTF_SYMBOLS_KNOWN 0x0004
621 #define HE_PRE_FEC_PADDING_KNOWN 0x0008
622 #define HE_MIDABLE_PERIODICITY_KNOWN 0x0080
623
624 /* HE radiotap data3 shift values */
625 #define HE_BEAM_CHANGE_SHIFT 6
626 #define HE_DL_UL_SHIFT 7
627 #define HE_TRANSMIT_MCS_SHIFT 8
628 #define HE_DCM_SHIFT 12
629 #define HE_CODING_SHIFT 13
630 #define HE_LDPC_EXTRA_SYMBOL_SHIFT 14
631 #define HE_STBC_SHIFT 15
632
633 /* HE radiotap data4 shift values */
634 #define HE_STA_ID_SHIFT 4
635
636 /* HE radiotap data5 */
637 #define HE_GI_SHIFT 4
638 #define HE_LTF_SIZE_SHIFT 6
639 #define HE_LTF_SYM_SHIFT 8
640 #define HE_TXBF_SHIFT 14
641 #define HE_PE_DISAMBIGUITY_SHIFT 15
642 #define HE_PRE_FEC_PAD_SHIFT 12
643
644 /* HE radiotap data6 */
645 #define HE_DOPPLER_SHIFT 4
646 #define HE_TXOP_SHIFT 8
647
648 /* HE radiotap HE-MU flags1 */
649 #define HE_SIG_B_MCS_KNOWN 0x0010
650 #define HE_SIG_B_DCM_KNOWN 0x0040
651 #define HE_SIG_B_SYM_NUM_KNOWN 0x8000
652 #define HE_RU_0_KNOWN 0x0100
653 #define HE_RU_1_KNOWN 0x0200
654 #define HE_RU_2_KNOWN 0x0400
655 #define HE_RU_3_KNOWN 0x0800
656 #define HE_DCM_FLAG_1_SHIFT 5
657 #define HE_SPATIAL_REUSE_MU_KNOWN 0x0100
658 #define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000
659
660 /* HE radiotap HE-MU flags2 */
661 #define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3
662 #define HE_BW_KNOWN 0x0004
663 #define HE_NUM_SIG_B_SYMBOLS_SHIFT 4
664 #define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100
665 #define HE_NUM_SIG_B_FLAG_2_SHIFT 9
666 #define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12
667 #define HE_LTF_KNOWN 0x8000
668
669 /* HE radiotap per_user_1 */
670 #define HE_STA_SPATIAL_SHIFT 11
671 #define HE_TXBF_SHIFT 14
672 #define HE_RESERVED_SET_TO_1_SHIFT 19
673 #define HE_STA_CODING_SHIFT 20
674
675 /* HE radiotap per_user_2 */
676 #define HE_STA_MCS_SHIFT 4
677 #define HE_STA_DCM_SHIFT 5
678
679 /* HE radiotap per user known */
680 #define HE_USER_FIELD_POSITION_KNOWN 0x01
681 #define HE_STA_ID_PER_USER_KNOWN 0x02
682 #define HE_STA_NSTS_KNOWN 0x04
683 #define HE_STA_TX_BF_KNOWN 0x08
684 #define HE_STA_SPATIAL_CONFIG_KNOWN 0x10
685 #define HE_STA_MCS_KNOWN 0x20
686 #define HE_STA_DCM_KNOWN 0x40
687 #define HE_STA_CODING_KNOWN 0x80
688
689 #define HAL_RX_MPDU_ERR_FCS BIT(0)
690 #define HAL_RX_MPDU_ERR_DECRYPT BIT(1)
691 #define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2)
692 #define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3)
693 #define HAL_RX_MPDU_ERR_OVERFLOW BIT(4)
694 #define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5)
695 #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6)
696 #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7)
697
698 #define HAL_RX_PHY_CMN_USER_INFO0_GI GENMASK(17, 16)
699
700 struct hal_phyrx_common_user_info {
701 __le32 rsvd[2];
702 __le32 info0;
703 __le32 rsvd1;
704 } __packed;
705
706 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE GENMASK(3, 0)
707 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_GI_LTF GENMASK(5, 4)
708 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM GENMASK(8, 6)
709 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS GENMASK(10, 7)
710 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_BEAMFORMED BIT(11)
711 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD GENMASK(13, 12)
712 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC GENMASK(17, 14)
713
714 struct hal_eht_sig_ndp_cmn_eb {
715 __le32 info0;
716 } __packed;
717
718 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE GENMASK(3, 0)
719 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_GI_LTF GENMASK(5, 4)
720 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM GENMASK(8, 6)
721 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_LDPC_EXTA_SYM BIT(9)
722 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10)
723 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISAMBIGUITY BIT(12)
724 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD GENMASK(16, 13)
725
726 struct hal_eht_sig_usig_overflow {
727 __le32 info0;
728 } __packed;
729
730 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0)
731 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS GENMASK(14, 11)
732 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_VALIDATE BIT(15)
733 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS GENMASK(19, 16)
734 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_BEAMFORMED BIT(20)
735 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CODING BIT(21)
736 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CRC GENMASK(25, 22)
737
738 struct hal_eht_sig_non_mu_mimo {
739 __le32 info0;
740 } __packed;
741
742 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0)
743 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS GENMASK(14, 11)
744 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CODING BIT(15)
745 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING GENMASK(22, 16)
746 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CRC GENMASK(26, 23)
747
748 struct hal_eht_sig_mu_mimo {
749 __le32 info0;
750 } __packed;
751
752 union hal_eht_sig_user_field {
753 struct hal_eht_sig_mu_mimo mu_mimo;
754 struct hal_eht_sig_non_mu_mimo n_mu_mimo;
755 };
756
757 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_SPATIAL_REUSE GENMASK(3, 0)
758 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_GI_LTF GENMASK(5, 4)
759 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_LTF_SYM GENMASK(8, 6)
760 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_LDPC_EXTA_SYM BIT(9)
761 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10)
762 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISAMBIGUITY BIT(12)
763 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISREGARD GENMASK(16, 13)
764 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS GENMASK(19, 17)
765
766 struct hal_eht_sig_non_ofdma_cmn_eb {
767 __le32 info0;
768 union hal_eht_sig_user_field user_field;
769 } __packed;
770
771 #define HAL_RX_EHT_SIG_OFDMA_EB1_SPATIAL_REUSE GENMASK_ULL(3, 0)
772 #define HAL_RX_EHT_SIG_OFDMA_EB1_GI_LTF GENMASK_ULL(5, 4)
773 #define HAL_RX_EHT_SIG_OFDMA_EB1_NUM_LFT_SYM GENMASK_ULL(8, 6)
774 #define HAL_RX_EHT_SIG_OFDMA_EB1_LDPC_EXTRA_SYM BIT(9)
775 #define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_FEC_PAD_FACTOR GENMASK_ULL(11, 10)
776 #define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_DISAMBIGUITY BIT(12)
777 #define HAL_RX_EHT_SIG_OFDMA_EB1_DISREGARD GENMASK_ULL(16, 13)
778 #define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1 GENMASK_ULL(25, 17)
779 #define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2 GENMASK_ULL(34, 26)
780 #define HAL_RX_EHT_SIG_OFDMA_EB1_CRC GENMASK_ULL(30, 27)
781
782 struct hal_eht_sig_ofdma_cmn_eb1 {
783 __le64 info0;
784 } __packed;
785
786 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1 GENMASK_ULL(8, 0)
787 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2 GENMASK_ULL(17, 9)
788 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3 GENMASK_ULL(26, 18)
789 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4 GENMASK_ULL(35, 27)
790 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5 GENMASK_ULL(44, 36)
791 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6 GENMASK_ULL(53, 45)
792 #define HAL_RX_EHT_SIG_OFDMA_EB2_MCS GNEMASK_ULL(57, 54)
793
794 struct hal_eht_sig_ofdma_cmn_eb2 {
795 __le64 info0;
796 } __packed;
797
798 struct hal_eht_sig_ofdma_cmn_eb {
799 struct hal_eht_sig_ofdma_cmn_eb1 eb1;
800 struct hal_eht_sig_ofdma_cmn_eb2 eb2;
801 union hal_eht_sig_user_field user_field;
802 } __packed;
803
804 enum hal_eht_bw {
805 HAL_EHT_BW_20,
806 HAL_EHT_BW_40,
807 HAL_EHT_BW_80,
808 HAL_EHT_BW_160,
809 HAL_EHT_BW_320_1,
810 HAL_EHT_BW_320_2,
811 };
812
813 #define HAL_RX_USIG_CMN_INFO0_PHY_VERSION GENMASK(2, 0)
814 #define HAL_RX_USIG_CMN_INFO0_BW GENMASK(5, 3)
815 #define HAL_RX_USIG_CMN_INFO0_UL_DL BIT(6)
816 #define HAL_RX_USIG_CMN_INFO0_BSS_COLOR GENMASK(12, 7)
817 #define HAL_RX_USIG_CMN_INFO0_TXOP GENMASK(19, 13)
818 #define HAL_RX_USIG_CMN_INFO0_DISREGARD GENMASK(25, 20)
819 #define HAL_RX_USIG_CMN_INFO0_VALIDATE BIT(26)
820
821 struct hal_mon_usig_cmn {
822 __le32 info0;
823 } __packed;
824
825 #define HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0)
826 #define HAL_RX_USIG_TB_INFO0_VALIDATE BIT(2)
827 #define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1 GENMASK(6, 3)
828 #define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2 GENMASK(10, 7)
829 #define HAL_RX_USIG_TB_INFO0_DISREGARD_1 GENMASK(15, 11)
830 #define HAL_RX_USIG_TB_INFO0_CRC GENMASK(19, 16)
831 #define HAL_RX_USIG_TB_INFO0_TAIL GENMASK(25, 20)
832 #define HAL_RX_USIG_TB_INFO0_RX_INTEG_CHECK_PASS BIT(31)
833
834 struct hal_mon_usig_tb {
835 __le32 info0;
836 } __packed;
837
838 #define HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0)
839 #define HAL_RX_USIG_MU_INFO0_VALIDATE_1 BIT(2)
840 #define HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO GENMASK(7, 3)
841 #define HAL_RX_USIG_MU_INFO0_VALIDATE_2 BIT(8)
842 #define HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS GENMASK(10, 9)
843 #define HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM GENMASK(15, 11)
844 #define HAL_RX_USIG_MU_INFO0_CRC GENMASK(20, 16)
845 #define HAL_RX_USIG_MU_INFO0_TAIL GENMASK(26, 21)
846 #define HAL_RX_USIG_MU_INFO0_RX_INTEG_CHECK_PASS BIT(31)
847
848 struct hal_mon_usig_mu {
849 __le32 info0;
850 } __packed;
851
852 union hal_mon_usig_non_cmn {
853 struct hal_mon_usig_tb tb;
854 struct hal_mon_usig_mu mu;
855 };
856
857 struct hal_mon_usig_hdr {
858 struct hal_mon_usig_cmn cmn;
859 union hal_mon_usig_non_cmn non_cmn;
860 } __packed;
861
862 #define HAL_RX_USR_INFO0_PHY_PPDU_ID GENMASK(15, 0)
863 #define HAL_RX_USR_INFO0_USR_RSSI GENMASK(23, 16)
864 #define HAL_RX_USR_INFO0_PKT_TYPE GENMASK(27, 24)
865 #define HAL_RX_USR_INFO0_STBC BIT(28)
866 #define HAL_RX_USR_INFO0_RECEPTION_TYPE GENMASK(31, 29)
867
868 #define HAL_RX_USR_INFO1_MCS GENMASK(3, 0)
869 #define HAL_RX_USR_INFO1_SGI GENMASK(5, 4)
870 #define HAL_RX_USR_INFO1_HE_RANGING_NDP BIT(6)
871 #define HAL_RX_USR_INFO1_MIMO_SS_BITMAP GENMASK(15, 8)
872 #define HAL_RX_USR_INFO1_RX_BW GENMASK(18, 16)
873 #define HAL_RX_USR_INFO1_DL_OFMDA_USR_IDX GENMASK(31, 24)
874
875 #define HAL_RX_USR_INFO2_DL_OFDMA_CONTENT_CHAN BIT(0)
876 #define HAL_RX_USR_INFO2_NSS GENMASK(10, 8)
877 #define HAL_RX_USR_INFO2_STREAM_OFFSET GENMASK(13, 11)
878 #define HAL_RX_USR_INFO2_STA_DCM BIT(14)
879 #define HAL_RX_USR_INFO2_LDPC BIT(15)
880 #define HAL_RX_USR_INFO2_RU_TYPE_80_0 GENMASK(19, 16)
881 #define HAL_RX_USR_INFO2_RU_TYPE_80_1 GENMASK(23, 20)
882 #define HAL_RX_USR_INFO2_RU_TYPE_80_2 GENMASK(27, 24)
883 #define HAL_RX_USR_INFO2_RU_TYPE_80_3 GENMASK(31, 28)
884
885 #define HAL_RX_USR_INFO3_RU_START_IDX_80_0 GENMASK(5, 0)
886 #define HAL_RX_USR_INFO3_RU_START_IDX_80_1 GENMASK(13, 8)
887 #define HAL_RX_USR_INFO3_RU_START_IDX_80_2 GENMASK(21, 16)
888 #define HAL_RX_USR_INFO3_RU_START_IDX_80_3 GENMASK(29, 24)
889
890 struct hal_receive_user_info {
891 __le32 info0;
892 __le32 info1;
893 __le32 info2;
894 __le32 info3;
895 __le32 user_fd_rssi_seg0;
896 __le32 user_fd_rssi_seg1;
897 __le32 user_fd_rssi_seg2;
898 __le32 user_fd_rssi_seg3;
899 } __packed;
900
901 enum hal_mon_reception_type {
902 HAL_RECEPTION_TYPE_SU,
903 HAL_RECEPTION_TYPE_DL_MU_MIMO,
904 HAL_RECEPTION_TYPE_DL_MU_OFMA,
905 HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
906 HAL_RECEPTION_TYPE_UL_MU_MIMO,
907 HAL_RECEPTION_TYPE_UL_MU_OFDMA,
908 HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
909 };
910
911 /* Different allowed RU in 11BE */
912 #define HAL_EHT_RU_26 0ULL
913 #define HAL_EHT_RU_52 1ULL
914 #define HAL_EHT_RU_78 2ULL
915 #define HAL_EHT_RU_106 3ULL
916 #define HAL_EHT_RU_132 4ULL
917 #define HAL_EHT_RU_242 5ULL
918 #define HAL_EHT_RU_484 6ULL
919 #define HAL_EHT_RU_726 7ULL
920 #define HAL_EHT_RU_996 8ULL
921 #define HAL_EHT_RU_996x2 9ULL
922 #define HAL_EHT_RU_996x3 10ULL
923 #define HAL_EHT_RU_996x4 11ULL
924 #define HAL_EHT_RU_NONE 15ULL
925 #define HAL_EHT_RU_INVALID 31ULL
926 /* MRUs spanning above 80Mhz
927 * HAL_EHT_RU_996_484 = HAL_EHT_RU_484 + HAL_EHT_RU_996 + 4 (reserved)
928 */
929 #define HAL_EHT_RU_996_484 18ULL
930 #define HAL_EHT_RU_996x2_484 28ULL
931 #define HAL_EHT_RU_996x3_484 40ULL
932 #define HAL_EHT_RU_996_484_242 23ULL
933
934 #define NUM_RU_BITS_PER80 16
935 #define NUM_RU_BITS_PER20 4
936
937 /* Different per_80Mhz band in 320Mhz bandwidth */
938 #define HAL_80_0 0
939 #define HAL_80_1 1
940 #define HAL_80_2 2
941 #define HAL_80_3 3
942
943 #define HAL_RU_80MHZ(num_band) ((num_band) * NUM_RU_BITS_PER80)
944 #define HAL_RU_20MHZ(idx_per_80) ((idx_per_80) * NUM_RU_BITS_PER20)
945
946 #define HAL_RU_SHIFT(num_band, idx_per_80) \
947 (HAL_RU_80MHZ(num_band) + HAL_RU_20MHZ(idx_per_80))
948
949 #define HAL_RU(ru, num_band, idx_per_80) \
950 ((u64)(ru) << HAL_RU_SHIFT(num_band, idx_per_80))
951
952 /* MRU-996+484 */
953 #define HAL_EHT_RU_996_484_0 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) | \
954 HAL_RU(HAL_EHT_RU_996, HAL_80_1, 0))
955 #define HAL_EHT_RU_996_484_1 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) | \
956 HAL_RU(HAL_EHT_RU_996, HAL_80_1, 0))
957 #define HAL_EHT_RU_996_484_2 (HAL_RU(HAL_EHT_RU_996, HAL_80_0, 0) | \
958 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1))
959 #define HAL_EHT_RU_996_484_3 (HAL_RU(HAL_EHT_RU_996, HAL_80_0, 0) | \
960 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0))
961 #define HAL_EHT_RU_996_484_4 (HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) | \
962 HAL_RU(HAL_EHT_RU_996, HAL_80_3, 0))
963 #define HAL_EHT_RU_996_484_5 (HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) | \
964 HAL_RU(HAL_EHT_RU_996, HAL_80_3, 0))
965 #define HAL_EHT_RU_996_484_6 (HAL_RU(HAL_EHT_RU_996, HAL_80_2, 0) | \
966 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
967 #define HAL_EHT_RU_996_484_7 (HAL_RU(HAL_EHT_RU_996, HAL_80_2, 0) | \
968 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
969
970 /* MRU-996x2+484 */
971 #define HAL_EHT_RU_996x2_484_0 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) | \
972 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
973 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
974 #define HAL_EHT_RU_996x2_484_1 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) | \
975 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
976 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
977 #define HAL_EHT_RU_996x2_484_2 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
978 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) | \
979 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
980 #define HAL_EHT_RU_996x2_484_3 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
981 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) | \
982 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
983 #define HAL_EHT_RU_996x2_484_4 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
984 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
985 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1))
986 #define HAL_EHT_RU_996x2_484_5 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
987 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
988 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0))
989 #define HAL_EHT_RU_996x2_484_6 (HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) | \
990 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
991 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
992 #define HAL_EHT_RU_996x2_484_7 (HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) | \
993 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
994 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
995 #define HAL_EHT_RU_996x2_484_8 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
996 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) | \
997 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
998 #define HAL_EHT_RU_996x2_484_9 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
999 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) | \
1000 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
1001 #define HAL_EHT_RU_996x2_484_10 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
1002 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
1003 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
1004 #define HAL_EHT_RU_996x2_484_11 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
1005 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
1006 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
1007
1008 /* MRU-996x3+484 */
1009 #define HAL_EHT_RU_996x3_484_0 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) | \
1010 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1011 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1012 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1013 #define HAL_EHT_RU_996x3_484_1 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) | \
1014 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1015 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1016 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1017 #define HAL_EHT_RU_996x3_484_2 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1018 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) | \
1019 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1020 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1021 #define HAL_EHT_RU_996x3_484_3 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1022 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) | \
1023 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1024 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1025 #define HAL_EHT_RU_996x3_484_4 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1026 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1027 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) | \
1028 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1029 #define HAL_EHT_RU_996x3_484_5 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1030 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1031 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) | \
1032 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1033 #define HAL_EHT_RU_996x3_484_6 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1034 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1035 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1036 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
1037 #define HAL_EHT_RU_996x3_484_7 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1038 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1039 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1040 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
1041
1042 #define HAL_RU_PER80(ru_per80, num_80mhz, ru_idx_per80mhz) \
1043 (HAL_RU(ru_per80, num_80mhz, ru_idx_per80mhz))
1044
1045 #define RU_INVALID 0
1046 #define RU_26 1
1047 #define RU_52 2
1048 #define RU_106 4
1049 #define RU_242 9
1050 #define RU_484 18
1051 #define RU_996 37
1052 #define RU_2X996 74
1053 #define RU_3X996 111
1054 #define RU_4X996 148
1055 #define RU_52_26 (RU_52 + RU_26)
1056 #define RU_106_26 (RU_106 + RU_26)
1057 #define RU_484_242 (RU_484 + RU_242)
1058 #define RU_996_484 (RU_996 + RU_484)
1059 #define RU_996_484_242 (RU_996 + RU_484_242)
1060 #define RU_2X996_484 (RU_2X996 + RU_484)
1061 #define RU_3X996_484 (RU_3X996 + RU_484)
1062
1063 enum ath12k_eht_ru_size {
1064 ATH12K_EHT_RU_26,
1065 ATH12K_EHT_RU_52,
1066 ATH12K_EHT_RU_106,
1067 ATH12K_EHT_RU_242,
1068 ATH12K_EHT_RU_484,
1069 ATH12K_EHT_RU_996,
1070 ATH12K_EHT_RU_996x2,
1071 ATH12K_EHT_RU_996x4,
1072 ATH12K_EHT_RU_52_26,
1073 ATH12K_EHT_RU_106_26,
1074 ATH12K_EHT_RU_484_242,
1075 ATH12K_EHT_RU_996_484,
1076 ATH12K_EHT_RU_996_484_242,
1077 ATH12K_EHT_RU_996x2_484,
1078 ATH12K_EHT_RU_996x3,
1079 ATH12K_EHT_RU_996x3_484,
1080
1081 /* Keep last */
1082 ATH12K_EHT_RU_INVALID,
1083 };
1084
1085 #define HAL_RX_RU_ALLOC_TYPE_MAX ATH12K_EHT_RU_INVALID
1086
1087 static inline
ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)1088 enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)
1089 {
1090 enum nl80211_he_ru_alloc ret;
1091
1092 switch (ru_tones) {
1093 case RU_52:
1094 ret = NL80211_RATE_INFO_HE_RU_ALLOC_52;
1095 break;
1096 case RU_106:
1097 ret = NL80211_RATE_INFO_HE_RU_ALLOC_106;
1098 break;
1099 case RU_242:
1100 ret = NL80211_RATE_INFO_HE_RU_ALLOC_242;
1101 break;
1102 case RU_484:
1103 ret = NL80211_RATE_INFO_HE_RU_ALLOC_484;
1104 break;
1105 case RU_996:
1106 ret = NL80211_RATE_INFO_HE_RU_ALLOC_996;
1107 break;
1108 case RU_2X996:
1109 ret = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
1110 break;
1111 case RU_26:
1112 fallthrough;
1113 default:
1114 ret = NL80211_RATE_INFO_HE_RU_ALLOC_26;
1115 break;
1116 }
1117 return ret;
1118 }
1119
1120 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab,
1121 struct hal_tlv_64_hdr *tlv,
1122 struct hal_reo_status *status);
1123 void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab,
1124 struct hal_tlv_64_hdr *tlv,
1125 struct hal_reo_status *status);
1126 void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab,
1127 struct hal_tlv_64_hdr *tlv,
1128 struct hal_reo_status *status);
1129 void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab,
1130 struct hal_tlv_64_hdr *tlv,
1131 struct hal_reo_status *status);
1132 void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab,
1133 struct hal_tlv_64_hdr *tlv,
1134 struct hal_reo_status *status);
1135 void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab,
1136 struct hal_tlv_64_hdr *tlv,
1137 struct hal_reo_status *status);
1138 void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab,
1139 struct hal_tlv_64_hdr *tlv,
1140 struct hal_reo_status *status);
1141 void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus,
1142 u32 *msdu_cookies,
1143 enum hal_rx_buf_return_buf_manager *rbm);
1144 void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab,
1145 struct hal_wbm_release_ring *desc,
1146 struct ath12k_buffer_addr *buf_addr_info,
1147 enum hal_wbm_rel_bm_act action);
1148 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo,
1149 dma_addr_t paddr, u32 cookie, u8 manager);
1150 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo,
1151 dma_addr_t *paddr,
1152 u32 *cookie, u8 *rbm);
1153 int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab,
1154 struct hal_reo_dest_ring *desc,
1155 dma_addr_t *paddr, u32 *desc_bank);
1156 int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc,
1157 struct hal_rx_wbm_rel_info *rel_info);
1158 void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab,
1159 struct ath12k_buffer_addr *buff_addr,
1160 dma_addr_t *paddr, u32 *cookie);
1161 void ath12k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, u32 *sw_cookie,
1162 struct ath12k_buffer_addr **pp_buf_addr,
1163 u8 *rbm, u32 *msdu_cnt);
1164 void ath12k_hal_rx_msdu_list_get(struct ath12k *ar,
1165 struct hal_rx_msdu_link *link_desc,
1166 struct hal_rx_msdu_list *msdu_list,
1167 u16 *num_msdus);
1168
1169 #endif
1170