1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU14_DRIVER_IF_V14_0_0_H 25 #define SMU14_DRIVER_IF_V14_0_0_H 26 27 typedef struct { 28 int32_t value; 29 uint32_t numFractionalBits; 30 } FloatInIntFormat_t; 31 32 typedef enum { 33 DSPCLK_DCFCLK = 0, 34 DSPCLK_DISPCLK, 35 DSPCLK_PIXCLK, 36 DSPCLK_PHYCLK, 37 DSPCLK_COUNT, 38 } DSPCLK_e; 39 40 typedef struct { 41 uint16_t Freq; // in MHz 42 uint16_t Vid; // min voltage in SVI3 VID 43 } DisplayClockTable_t; 44 45 typedef struct { 46 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) 47 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) 48 uint16_t MinMclk; 49 uint16_t MaxMclk; 50 51 uint8_t WmSetting; 52 uint8_t WmType; // Used for normal pstate change or memory retraining 53 uint8_t Padding[2]; 54 } WatermarkRowGeneric_t; 55 56 #define NUM_WM_RANGES 4 57 #define WM_PSTATE_CHG 0 58 #define WM_RETRAINING 1 59 60 typedef enum { 61 WM_SOCCLK = 0, 62 WM_DCFCLK, 63 WM_COUNT, 64 } WM_CLOCK_e; 65 66 typedef struct { 67 // Watermarks 68 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 69 70 uint32_t MmHubPadding[7]; // SMU internal use 71 } Watermarks_t; 72 73 typedef enum { 74 CUSTOM_DPM_SETTING_GFXCLK, 75 CUSTOM_DPM_SETTING_CCLK, 76 CUSTOM_DPM_SETTING_FCLK_CCX, 77 CUSTOM_DPM_SETTING_FCLK_GFX, 78 CUSTOM_DPM_SETTING_FCLK_STALLS, 79 CUSTOM_DPM_SETTING_LCLK, 80 CUSTOM_DPM_SETTING_COUNT, 81 } CUSTOM_DPM_SETTING_e; 82 83 typedef struct { 84 uint8_t ActiveHystLimit; 85 uint8_t IdleHystLimit; 86 uint8_t FPS; 87 uint8_t MinActiveFreqType; 88 FloatInIntFormat_t MinActiveFreq; 89 FloatInIntFormat_t PD_Data_limit; 90 FloatInIntFormat_t PD_Data_time_constant; 91 FloatInIntFormat_t PD_Data_error_coeff; 92 FloatInIntFormat_t PD_Data_error_rate_coeff; 93 } DpmActivityMonitorCoeffExt_t; 94 95 typedef struct { 96 DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; 97 } CustomDpmSettings_t; 98 99 #define NUM_DCFCLK_DPM_LEVELS 8 100 #define NUM_DISPCLK_DPM_LEVELS 8 101 #define NUM_DPPCLK_DPM_LEVELS 8 102 #define NUM_SOCCLK_DPM_LEVELS 8 103 #define NUM_VCN_DPM_LEVELS 8 104 #define NUM_SOC_VOLTAGE_LEVELS 8 105 #define NUM_VPE_DPM_LEVELS 8 106 #define NUM_FCLK_DPM_LEVELS 8 107 #define NUM_MEM_PSTATE_LEVELS 4 108 109 110 typedef struct { 111 uint32_t UClk; 112 uint32_t MemClk; 113 uint32_t Voltage; 114 uint8_t WckRatio; 115 uint8_t Spare[3]; 116 } MemPstateTable_t; 117 118 //Freq in MHz 119 //Voltage in milli volts with 2 fractional bits 120 typedef struct { 121 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; 122 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; 123 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; 124 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; 125 uint32_t VClocks[NUM_VCN_DPM_LEVELS]; 126 uint32_t DClocks[NUM_VCN_DPM_LEVELS]; 127 uint32_t VPEClocks[NUM_VPE_DPM_LEVELS]; 128 uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS]; 129 uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS]; 130 uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; 131 MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS]; 132 133 uint8_t NumDcfClkLevelsEnabled; 134 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk 135 uint8_t NumSocClkLevelsEnabled; 136 uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk 137 uint8_t VpeClkLevelsEnabled; 138 139 uint8_t NumMemPstatesEnabled; 140 uint8_t NumFclkLevelsEnabled; 141 uint8_t spare[2]; 142 143 uint32_t MinGfxClk; 144 uint32_t MaxGfxClk; 145 } DpmClocks_t; 146 147 typedef struct { 148 uint16_t CoreFrequency[16]; //Target core frequency [MHz] 149 uint16_t CorePower[16]; //CAC calculated core power [mW] 150 uint16_t CoreTemperature[16]; //TSEN measured core temperature [centi-C] 151 uint16_t GfxTemperature; //TSEN measured GFX temperature [centi-C] 152 uint16_t SocTemperature; //TSEN measured SOC temperature [centi-C] 153 uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [mW] 154 uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [mW] 155 uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz] 156 uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz] 157 uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C] 158 uint16_t GfxclkFrequency; //Time filtered target GFXCLK frequency [MHz] 159 uint16_t FclkFrequency; //Time filtered target FCLK frequency [MHz] 160 uint16_t GfxActivity; //Time filtered GFX busy % [0-100] 161 uint16_t SocclkFrequency; //Time filtered target SOCCLK frequency [MHz] 162 uint16_t VclkFrequency; //Time filtered target VCLK frequency [MHz] 163 uint16_t VcnActivity; //Time filtered VCN busy % [0-100] 164 uint16_t VpeclkFrequency; //Time filtered target VPECLK frequency [MHz] 165 uint16_t IpuclkFrequency; //Time filtered target IPUCLK frequency [MHz] 166 uint16_t IpuBusy[8]; //Time filtered IPU per-column busy % [0-100] 167 uint16_t DRAMReads; //Time filtered DRAM read bandwidth [MB/sec] 168 uint16_t DRAMWrites; //Time filtered DRAM write bandwidth [MB/sec] 169 uint16_t CoreC0Residency[16]; //Time filtered per-core C0 residency % [0-100] 170 uint16_t IpuPower; //Time filtered IPU power [mW] 171 uint32_t ApuPower; //Time filtered APU power [mW] 172 uint32_t GfxPower; //Time filtered GFX power [mW] 173 uint32_t dGpuPower; //Time filtered dGPU power [mW] 174 uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW] 175 uint32_t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW] 176 uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us] 177 uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles] 178 uint16_t MemclkFrequency; //Time filtered target MEMCLK frequency [MHz] 179 uint16_t MpipuclkFrequency; //Time filtered target MPIPUCLK frequency [MHz] 180 uint16_t IpuReads; //Time filtered IPU read bandwidth [MB/sec] 181 uint16_t IpuWrites; //Time filtered IPU write bandwidth [MB/sec] 182 uint32_t ThrottleResidency_PROCHOT; //Counter that is incremented on every metrics table update when PROCHOT was engaged [PM_TIMER cycles] 183 uint32_t ThrottleResidency_SPL; //Counter that is incremented on every metrics table update when SPL was engaged [PM_TIMER cycles] 184 uint32_t ThrottleResidency_FPPT; //Counter that is incremented on every metrics table update when fast PPT was engaged [PM_TIMER cycles] 185 uint32_t ThrottleResidency_SPPT; //Counter that is incremented on every metrics table update when slow PPT was engaged [PM_TIMER cycles] 186 uint32_t ThrottleResidency_THM_CORE; //Counter that is incremented on every metrics table update when CORE thermal throttling was engaged [PM_TIMER cycles] 187 uint32_t ThrottleResidency_THM_GFX; //Counter that is incremented on every metrics table update when GFX thermal throttling was engaged [PM_TIMER cycles] 188 uint32_t ThrottleResidency_THM_SOC; //Counter that is incremented on every metrics table update when SOC thermal throttling was engaged [PM_TIMER cycles] 189 uint16_t Psys; //Time filtered Psys power [mW] 190 uint16_t spare1; 191 uint32_t spare[6]; 192 } SmuMetrics_t; 193 194 //ISP tile definitions 195 typedef enum { 196 TILE_XTILE = 0, //ONO0 197 TILE_MTILE, //ONO1 198 TILE_PDP, //ONO2 199 TILE_CSTAT, //ONO2 200 TILE_LME, //ONO3 201 TILE_BYRP, //ONO4 202 TILE_GRBP, //ONO4 203 TILE_MCFP, //ONO4 204 TILE_YUVP, //ONO4 205 TILE_MCSC, //ONO4 206 TILE_GDC, //ONO5 207 TILE_MAX 208 } TILE_NUM_e; 209 210 // Tile Selection (Based on arguments) 211 #define ISP_TILE_SEL(tile) (1<<tile) 212 #define ISP_TILE_SEL_ALL 0x7FF 213 214 // Workload bits 215 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 216 #define WORKLOAD_PPLIB_VIDEO_BIT 2 217 #define WORKLOAD_PPLIB_VR_BIT 3 218 #define WORKLOAD_PPLIB_COMPUTE_BIT 4 219 #define WORKLOAD_PPLIB_CUSTOM_BIT 5 220 #define WORKLOAD_PPLIB_COUNT 6 221 222 #define TABLE_BIOS_IF 0 // Called by BIOS 223 #define TABLE_WATERMARKS 1 // Called by DAL through VBIOS 224 #define TABLE_CUSTOM_DPM 2 // Called by Driver 225 #define TABLE_BIOS_GPIO_CONFIG 3 // Called by BIOS 226 #define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS 227 #define TABLE_SPARE0 5 // Unused 228 #define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log 229 #define TABLE_SMU_METRICS 7 // Called by Driver and SMF/PMF 230 #define TABLE_COUNT 8 231 232 #endif 233