1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #ifndef _ABI_GUC_KLVS_ABI_H 7 #define _ABI_GUC_KLVS_ABI_H 8 9 #include <linux/types.h> 10 11 /** 12 * DOC: GuC KLV 13 * 14 * +---+-------+--------------------------------------------------------------+ 15 * | | Bits | Description | 16 * +===+=======+==============================================================+ 17 * | 0 | 31:16 | **KEY** - KLV key identifier | 18 * | | | - `GuC Self Config KLVs`_ | 19 * | | | - `GuC Opt In Feature KLVs`_ | 20 * | | | - `GuC VGT Policy KLVs`_ | 21 * | | | - `GuC VF Configuration KLVs`_ | 22 * | | | | 23 * | +-------+--------------------------------------------------------------+ 24 * | | 15:0 | **LEN** - length of VALUE (in 32bit dwords) | 25 * +---+-------+--------------------------------------------------------------+ 26 * | 1 | 31:0 | **VALUE** - actual value of the KLV (format depends on KEY) | 27 * +---+-------+ | 28 * |...| | | 29 * +---+-------+ | 30 * | n | 31:0 | | 31 * +---+-------+--------------------------------------------------------------+ 32 */ 33 34 #define GUC_KLV_LEN_MIN 1u 35 #define GUC_KLV_0_KEY (0xffffu << 16) 36 #define GUC_KLV_0_LEN (0xffffu << 0) 37 #define GUC_KLV_n_VALUE (0xffffffffu << 0) 38 39 /** 40 * DOC: GuC Global Config KLVs 41 * 42 * `GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_. 43 * 44 * _`GUC_KLV_GLOBAL_CFG_GMD_ID` : 0x3000 45 * Refers to 32 bit architecture version as reported by the HW IP. 46 * This key is supported on MTL+ platforms only. 47 * Requires GuC ABI 1.2+. 48 */ 49 50 #define GUC_KLV_GLOBAL_CFG_GMD_ID_KEY 0x3000u 51 #define GUC_KLV_GLOBAL_CFG_GMD_ID_LEN 1u 52 53 /** 54 * DOC: GuC Self Config KLVs 55 * 56 * `GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_. 57 * 58 * _`GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR` : 0x0900 59 * Refers to 64 bit Global Gfx address (in bytes) of memory based interrupts 60 * status vector for use by the GuC. 61 * 62 * _`GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR` : 0x0901 63 * Refers to 64 bit Global Gfx address (in bytes) of memory based interrupts 64 * source vector for use by the GuC. 65 * 66 * _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902 67 * Refers to 64 bit Global Gfx address of H2G `CT Buffer`_. 68 * Should be above WOPCM address but below APIC base address for native mode. 69 * 70 * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR : 0x0903 71 * Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. 72 * Should be above WOPCM address but below APIC base address for native mode. 73 * 74 * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE : 0x0904 75 * Refers to size of H2G `CT Buffer`_ in bytes. 76 * Should be a multiple of 4K. 77 * 78 * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR : 0x0905 79 * Refers to 64 bit Global Gfx address of G2H `CT Buffer`_. 80 * Should be above WOPCM address but below APIC base address for native mode. 81 * 82 * _GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR : 0x0906 83 * Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. 84 * Should be above WOPCM address but below APIC base address for native mode. 85 * 86 * _GUC_KLV_SELF_CFG_G2H_CTB_SIZE : 0x0907 87 * Refers to size of G2H `CT Buffer`_ in bytes. 88 * Should be a multiple of 4K. 89 */ 90 91 #define GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR_KEY 0x0900 92 #define GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR_LEN 2u 93 94 #define GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR_KEY 0x0901 95 #define GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR_LEN 2u 96 97 #define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_KEY 0x0902 98 #define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_LEN 2u 99 100 #define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_KEY 0x0903 101 #define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_LEN 2u 102 103 #define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_KEY 0x0904 104 #define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_LEN 1u 105 106 #define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_KEY 0x0905 107 #define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_LEN 2u 108 109 #define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_KEY 0x0906 110 #define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_LEN 2u 111 112 #define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY 0x0907 113 #define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN 1u 114 115 /* 116 * Per context scheduling policy update keys. 117 */ 118 enum { 119 GUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM = 0x2001, 120 GUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT = 0x2002, 121 GUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY = 0x2003, 122 GUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY = 0x2004, 123 GUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY = 0x2005, 124 125 GUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5, 126 }; 127 128 /** 129 * DOC: GuC Opt In Feature KLVs 130 * 131 * `GuC KLV`_ keys available for use with OPT_IN_FEATURE_KLV 132 * 133 * _`GUC_KLV_OPT_IN_FEATURE_EXT_CAT_ERR_TYPE` : 0x4001 134 * Adds an extra dword to the XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR G2H 135 * containing the type of the CAT error. On HW that does not support 136 * reporting the CAT error type, the extra dword is set to 0xdeadbeef. 137 * 138 * _`GUC_KLV_OPT_IN_FEATURE_DYNAMIC_INHIBIT_CONTEXT_SWITCH` : 0x4003 139 * This KLV enables the Dynamic Inhibit Context Switch optimization, which 140 * consists in the GuC setting the CTX_CTRL_INHIBIT_SYN_CTX_SWITCH bit to 141 * zero in the CTX_CONTEXT_CONTROL register of LRCs that are submitted 142 * to an oversubscribed engine. This will cause those contexts to be 143 * switched out immediately if they hit an unsatisfied semaphore wait 144 * (instead of waiting the full timeslice duration). The bit is instead set 145 * to one if a single context is queued on the engine, to avoid it being 146 * switched out if there isn't another context that can run in its place. 147 */ 148 149 #define GUC_KLV_OPT_IN_FEATURE_EXT_CAT_ERR_TYPE_KEY 0x4001 150 #define GUC_KLV_OPT_IN_FEATURE_EXT_CAT_ERR_TYPE_LEN 0u 151 152 #define GUC_KLV_OPT_IN_FEATURE_DYNAMIC_INHIBIT_CONTEXT_SWITCH_KEY 0x4003 153 #define GUC_KLV_OPT_IN_FEATURE_DYNAMIC_INHIBIT_CONTEXT_SWITCH_LEN 0u 154 155 /** 156 * DOC: GuC VGT Policy KLVs 157 * 158 * `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VGT_POLICY. 159 * 160 * _`GUC_KLV_VGT_POLICY_SCHED_IF_IDLE` : 0x8001 161 * This config sets whether strict scheduling is enabled whereby any VF 162 * that doesn’t have work to submit is still allocated a fixed execution 163 * time-slice to ensure active VFs execution is always consistent even 164 * during other VF reprovisiong / rebooting events. Changing this KLV 165 * impacts all VFs and takes effect on the next VF-Switch event. 166 * 167 * :0: don't schedule idle (default) 168 * :1: schedule if idle 169 * 170 * _`GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD` : 0x8002 171 * This config sets the sample period for tracking adverse event counters. 172 * A sample period is the period in millisecs during which events are counted. 173 * This is applicable for all the VFs. 174 * 175 * :0: adverse events are not counted (default) 176 * :n: sample period in milliseconds 177 * 178 * _`GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH` : 0x8D00 179 * This enum is to reset utilized HW engine after VF Switch (i.e to clean 180 * up Stale HW register left behind by previous VF) 181 * 182 * :0: don't reset (default) 183 * :1: reset 184 */ 185 186 #define GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_KEY 0x8001 187 #define GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_LEN 1u 188 189 #define GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD_KEY 0x8002 190 #define GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD_LEN 1u 191 192 #define GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH_KEY 0x8D00 193 #define GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH_LEN 1u 194 195 /** 196 * DOC: GuC VF Configuration KLVs 197 * 198 * `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VF_CFG. 199 * 200 * _`GUC_KLV_VF_CFG_GGTT_START` : 0x0001 201 * A 4K aligned start GTT address/offset assigned to VF. 202 * Value is 64 bits. 203 * 204 * _`GUC_KLV_VF_CFG_GGTT_SIZE` : 0x0002 205 * A 4K aligned size of GGTT assigned to VF. 206 * Value is 64 bits. 207 * 208 * _`GUC_KLV_VF_CFG_LMEM_SIZE` : 0x0003 209 * A 2M aligned size of local memory assigned to VF. 210 * Value is 64 bits. 211 * 212 * _`GUC_KLV_VF_CFG_NUM_CONTEXTS` : 0x0004 213 * Refers to the number of contexts allocated to this VF. 214 * 215 * :0: no contexts (default) 216 * :1-65535: number of contexts (Gen12) 217 * 218 * _`GUC_KLV_VF_CFG_TILE_MASK` : 0x0005 219 * For multi-tiled products, this field contains the bitwise-OR of tiles 220 * assigned to the VF. Bit-0-set means VF has access to Tile-0, 221 * Bit-31-set means VF has access to Tile-31, and etc. 222 * At least one tile will always be allocated. 223 * If all bits are zero, VF KMD should treat this as a fatal error. 224 * For, single-tile products this KLV config is ignored. 225 * 226 * _`GUC_KLV_VF_CFG_NUM_DOORBELLS` : 0x0006 227 * Refers to the number of doorbells allocated to this VF. 228 * 229 * :0: no doorbells (default) 230 * :1-255: number of doorbells (Gen12) 231 * 232 * _`GUC_KLV_VF_CFG_EXEC_QUANTUM` : 0x8A01 233 * This config sets the VFs-execution-quantum in milliseconds. 234 * GUC will attempt to obey the maximum values as much as HW is capable 235 * of and this will never be perfectly-exact (accumulated nano-second 236 * granularity) since the GPUs clock time runs off a different crystal 237 * from the CPUs clock. Changing this KLV on a VF that is currently 238 * running a context won't take effect until a new context is scheduled in. 239 * That said, when the PF is changing this value from 0x0 to 240 * a non-zero value, it might never take effect if the VF is running an 241 * infinitely long compute or shader kernel. In such a scenario, the 242 * PF would need to trigger a VM PAUSE and then change the KLV to force 243 * it to take effect. Such cases might typically happen on a 1PF+1VF 244 * Virtualization config enabled for heavier workloads like AI/ML. 245 * 246 * The max value for this KLV is 100 seconds, anything exceeding that 247 * will be clamped to the max. 248 * 249 * :0: infinite exec quantum (default) 250 * :100000: maximum exec quantum (100000ms == 100s) 251 * 252 * _`GUC_KLV_VF_CFG_PREEMPT_TIMEOUT` : 0x8A02 253 * This config sets the VF-preemption-timeout in microseconds. 254 * GUC will attempt to obey the minimum and maximum values as much as 255 * HW is capable and this will never be perfectly-exact (accumulated 256 * nano-second granularity) since the GPUs clock time runs off a 257 * different crystal from the CPUs clock. Changing this KLV on a VF 258 * that is currently running a context won't take effect until a new 259 * context is scheduled in. 260 * That said, when the PF is changing this value from 0x0 to 261 * a non-zero value, it might never take effect if the VF is running an 262 * infinitely long compute or shader kernel. 263 * In this case, the PF would need to trigger a VM PAUSE and then change 264 * the KLV to force it to take effect. Such cases might typically happen 265 * on a 1PF+1VF Virtualization config enabled for heavier workloads like 266 * AI/ML. 267 * 268 * The max value for this KLV is 100 seconds, anything exceeding that 269 * will be clamped to the max. 270 * 271 * :0: no preemption timeout (default) 272 * :100000000: maximum preemption timeout (100000000us == 100s) 273 * 274 * _`GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR` : 0x8A03 275 * This config sets threshold for CAT errors caused by the VF. 276 * 277 * :0: adverse events or error will not be reported (default) 278 * :n: event occurrence count per sampling interval 279 * 280 * _`GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET` : 0x8A04 281 * This config sets threshold for engine reset caused by the VF. 282 * 283 * :0: adverse events or error will not be reported (default) 284 * :n: event occurrence count per sampling interval 285 * 286 * _`GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT` : 0x8A05 287 * This config sets threshold for page fault errors caused by the VF. 288 * 289 * :0: adverse events or error will not be reported (default) 290 * :n: event occurrence count per sampling interval 291 * 292 * _`GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM` : 0x8A06 293 * This config sets threshold for H2G interrupts triggered by the VF. 294 * 295 * :0: adverse events or error will not be reported (default) 296 * :n: time (us) per sampling interval 297 * 298 * _`GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM` : 0x8A07 299 * This config sets threshold for GT interrupts triggered by the VF's 300 * workloads. 301 * 302 * :0: adverse events or error will not be reported (default) 303 * :n: time (us) per sampling interval 304 * 305 * _`GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM` : 0x8A08 306 * This config sets threshold for doorbell's ring triggered by the VF. 307 * 308 * :0: adverse events or error will not be reported (default) 309 * :n: time (us) per sampling interval 310 * 311 * _`GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID` : 0x8A0A 312 * Refers to the start index of doorbell assigned to this VF. 313 * 314 * :0: (default) 315 * :1-255: number of doorbells (Gen12) 316 * 317 * _`GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID` : 0x8A0B 318 * Refers to the start index in context array allocated to this VF’s use. 319 * 320 * :0: (default) 321 * :1-65535: number of contexts (Gen12) 322 * 323 * _`GUC_KLV_VF_CFG_SCHED_PRIORITY` : 0x8A0C 324 * This config controls VF’s scheduling priority. 325 * 326 * :0: LOW = schedule VF only if it has active work (default) 327 * :1: NORMAL = schedule VF always, irrespective of whether it has work or not 328 * :2: HIGH = schedule VF in the next time-slice after current active 329 * time-slice completes if it has active work 330 */ 331 332 #define GUC_KLV_VF_CFG_GGTT_START_KEY 0x0001 333 #define GUC_KLV_VF_CFG_GGTT_START_LEN 2u 334 335 #define GUC_KLV_VF_CFG_GGTT_SIZE_KEY 0x0002 336 #define GUC_KLV_VF_CFG_GGTT_SIZE_LEN 2u 337 338 #define GUC_KLV_VF_CFG_LMEM_SIZE_KEY 0x0003 339 #define GUC_KLV_VF_CFG_LMEM_SIZE_LEN 2u 340 341 #define GUC_KLV_VF_CFG_NUM_CONTEXTS_KEY 0x0004 342 #define GUC_KLV_VF_CFG_NUM_CONTEXTS_LEN 1u 343 344 #define GUC_KLV_VF_CFG_TILE_MASK_KEY 0x0005 345 #define GUC_KLV_VF_CFG_TILE_MASK_LEN 1u 346 347 #define GUC_KLV_VF_CFG_NUM_DOORBELLS_KEY 0x0006 348 #define GUC_KLV_VF_CFG_NUM_DOORBELLS_LEN 1u 349 350 #define GUC_KLV_VF_CFG_EXEC_QUANTUM_KEY 0x8a01 351 #define GUC_KLV_VF_CFG_EXEC_QUANTUM_LEN 1u 352 #define GUC_KLV_VF_CFG_EXEC_QUANTUM_MAX_VALUE 100000u 353 354 #define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_KEY 0x8a02 355 #define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_LEN 1u 356 #define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_MAX_VALUE 100000000u 357 358 #define GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR_KEY 0x8a03 359 #define GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR_LEN 1u 360 361 #define GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET_KEY 0x8a04 362 #define GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET_LEN 1u 363 364 #define GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT_KEY 0x8a05 365 #define GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT_LEN 1u 366 367 #define GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM_KEY 0x8a06 368 #define GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM_LEN 1u 369 370 #define GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM_KEY 0x8a07 371 #define GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM_LEN 1u 372 373 #define GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM_KEY 0x8a08 374 #define GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM_LEN 1u 375 376 #define GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID_KEY 0x8a0a 377 #define GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID_LEN 1u 378 379 #define GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID_KEY 0x8a0b 380 #define GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID_LEN 1u 381 382 #define GUC_KLV_VF_CFG_SCHED_PRIORITY_KEY 0x8a0c 383 #define GUC_KLV_VF_CFG_SCHED_PRIORITY_LEN 1u 384 #define GUC_SCHED_PRIORITY_LOW 0u 385 #define GUC_SCHED_PRIORITY_NORMAL 1u 386 #define GUC_SCHED_PRIORITY_HIGH 2u 387 388 /* 389 * Workaround keys: 390 */ 391 enum xe_guc_klv_ids { 392 GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED = 0x9002, 393 GUC_WORKAROUND_KLV_ID_GAM_PFQ_SHADOW_TAIL_POLLING = 0x9005, 394 GUC_WORKAROUND_KLV_ID_DISABLE_MTP_DURING_ASYNC_COMPUTE = 0x9007, 395 GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE = 0x9008, 396 GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET = 0x9009, 397 GUC_WA_KLV_WAKE_POWER_DOMAINS_FOR_OUTBOUND_MMIO = 0x900a, 398 GUC_WA_KLV_RESET_BB_STACK_PTR_ON_VF_SWITCH = 0x900b, 399 }; 400 401 #endif 402