1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2021, Google LLC.
4 */
5
6 #ifndef SELFTEST_KVM_APIC_H
7 #define SELFTEST_KVM_APIC_H
8
9 #include <stdint.h>
10
11 #include "processor.h"
12 #include "ucall_common.h"
13
14 #define APIC_DEFAULT_GPA 0xfee00000ULL
15
16 /* APIC base address MSR and fields */
17 #define MSR_IA32_APICBASE 0x0000001b
18 #define MSR_IA32_APICBASE_BSP (1<<8)
19 #define MSR_IA32_APICBASE_EXTD (1<<10)
20 #define MSR_IA32_APICBASE_ENABLE (1<<11)
21 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
22 #define GET_APIC_BASE(x) (((x) >> 12) << 12)
23
24 #define APIC_BASE_MSR 0x800
25 #define X2APIC_ENABLE (1UL << 10)
26 #define APIC_ID 0x20
27 #define APIC_LVR 0x30
28 #define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF)
29 #define APIC_TASKPRI 0x80
30 #define APIC_PROCPRI 0xA0
31 #define GET_APIC_PRI(x) (((x) & GENMASK(7, 4)) >> 4)
32 #define SET_APIC_PRI(x, y) (((x) & ~GENMASK(7, 4)) | (y << 4))
33 #define APIC_EOI 0xB0
34 #define APIC_SPIV 0xF0
35 #define APIC_SPIV_FOCUS_DISABLED (1 << 9)
36 #define APIC_SPIV_APIC_ENABLED (1 << 8)
37 #define APIC_ISR 0x100
38 #define APIC_IRR 0x200
39 #define APIC_ICR 0x300
40 #define APIC_LVTCMCI 0x2f0
41 #define APIC_DEST_SELF 0x40000
42 #define APIC_DEST_ALLINC 0x80000
43 #define APIC_DEST_ALLBUT 0xC0000
44 #define APIC_ICR_RR_MASK 0x30000
45 #define APIC_ICR_RR_INVALID 0x00000
46 #define APIC_ICR_RR_INPROG 0x10000
47 #define APIC_ICR_RR_VALID 0x20000
48 #define APIC_INT_LEVELTRIG 0x08000
49 #define APIC_INT_ASSERT 0x04000
50 #define APIC_ICR_BUSY 0x01000
51 #define APIC_DEST_LOGICAL 0x00800
52 #define APIC_DEST_PHYSICAL 0x00000
53 #define APIC_DM_FIXED 0x00000
54 #define APIC_DM_FIXED_MASK 0x00700
55 #define APIC_DM_LOWEST 0x00100
56 #define APIC_DM_SMI 0x00200
57 #define APIC_DM_REMRD 0x00300
58 #define APIC_DM_NMI 0x00400
59 #define APIC_DM_INIT 0x00500
60 #define APIC_DM_STARTUP 0x00600
61 #define APIC_DM_EXTINT 0x00700
62 #define APIC_VECTOR_MASK 0x000FF
63 #define APIC_ICR2 0x310
64 #define SET_APIC_DEST_FIELD(x) ((x) << 24)
65 #define APIC_LVTT 0x320
66 #define APIC_LVT_TIMER_ONESHOT (0 << 17)
67 #define APIC_LVT_TIMER_PERIODIC (1 << 17)
68 #define APIC_LVT_TIMER_TSCDEADLINE (2 << 17)
69 #define APIC_LVT_MASKED (1 << 16)
70 #define APIC_TMICT 0x380
71 #define APIC_TMCCT 0x390
72 #define APIC_TDCR 0x3E0
73 #define APIC_SELF_IPI 0x3F0
74
75 #define APIC_VECTOR_TO_BIT_NUMBER(v) ((unsigned int)(v) % 32)
76 #define APIC_VECTOR_TO_REG_OFFSET(v) ((unsigned int)(v) / 32 * 0x10)
77
78 void apic_disable(void);
79 void xapic_enable(void);
80 void x2apic_enable(void);
81
get_bsp_flag(void)82 static inline uint32_t get_bsp_flag(void)
83 {
84 return rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_BSP;
85 }
86
xapic_read_reg(unsigned int reg)87 static inline uint32_t xapic_read_reg(unsigned int reg)
88 {
89 return ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2];
90 }
91
xapic_write_reg(unsigned int reg,uint32_t val)92 static inline void xapic_write_reg(unsigned int reg, uint32_t val)
93 {
94 ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2] = val;
95 }
96
x2apic_read_reg(unsigned int reg)97 static inline uint64_t x2apic_read_reg(unsigned int reg)
98 {
99 return rdmsr(APIC_BASE_MSR + (reg >> 4));
100 }
101
x2apic_write_reg_safe(unsigned int reg,uint64_t value)102 static inline uint8_t x2apic_write_reg_safe(unsigned int reg, uint64_t value)
103 {
104 return wrmsr_safe(APIC_BASE_MSR + (reg >> 4), value);
105 }
106
x2apic_write_reg(unsigned int reg,uint64_t value)107 static inline void x2apic_write_reg(unsigned int reg, uint64_t value)
108 {
109 uint8_t fault = x2apic_write_reg_safe(reg, value);
110
111 __GUEST_ASSERT(!fault, "Unexpected fault 0x%x on WRMSR(%x) = %lx\n",
112 fault, APIC_BASE_MSR + (reg >> 4), value);
113 }
114
x2apic_write_reg_fault(unsigned int reg,uint64_t value)115 static inline void x2apic_write_reg_fault(unsigned int reg, uint64_t value)
116 {
117 uint8_t fault = x2apic_write_reg_safe(reg, value);
118
119 __GUEST_ASSERT(fault == GP_VECTOR,
120 "Wanted #GP on WRMSR(%x) = %lx, got 0x%x\n",
121 APIC_BASE_MSR + (reg >> 4), value, fault);
122 }
123
124
125 #endif /* SELFTEST_KVM_APIC_H */
126