1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 25 #define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 26 27 // *** IMPORTANT *** 28 // SMU TEAM: Always increment the interface version if 29 // any structure is changed in this file 30 #define SMU11_DRIVER_IF_VERSION 0x39 31 32 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 6 33 34 #define NUM_GFXCLK_DPM_LEVELS 16 35 #define NUM_SMNCLK_DPM_LEVELS 2 36 #define NUM_SOCCLK_DPM_LEVELS 8 37 #define NUM_MP0CLK_DPM_LEVELS 2 38 #define NUM_DCLK_DPM_LEVELS 8 39 #define NUM_VCLK_DPM_LEVELS 8 40 #define NUM_DCEFCLK_DPM_LEVELS 8 41 #define NUM_PHYCLK_DPM_LEVELS 8 42 #define NUM_DISPCLK_DPM_LEVELS 8 43 #define NUM_PIXCLK_DPM_LEVELS 8 44 #define NUM_DTBCLK_DPM_LEVELS 8 45 #define NUM_UCLK_DPM_LEVELS 4 46 #define NUM_MP1CLK_DPM_LEVELS 2 47 #define NUM_LINK_LEVELS 2 48 #define NUM_FCLK_DPM_LEVELS 8 49 #define NUM_XGMI_LEVELS 2 50 #define NUM_XGMI_PSTATE_LEVELS 4 51 #define NUM_OD_FAN_MAX_POINTS 6 52 53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1) 55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 63 #define MAX_DTBCLK_DPM_LEVEL (NUM_DTBCLK_DPM_LEVELS - 1) 64 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 65 #define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1) 66 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 67 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 68 69 //Gemini Modes 70 #define PPSMC_GeminiModeNone 0 //Single GPU board 71 #define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board 72 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board 73 74 // Feature Control Defines 75 // DPM 76 #define FEATURE_DPM_PREFETCHER_BIT 0 77 #define FEATURE_DPM_GFXCLK_BIT 1 78 #define FEATURE_DPM_GFX_GPO_BIT 2 79 #define FEATURE_DPM_UCLK_BIT 3 80 #define FEATURE_DPM_FCLK_BIT 4 81 #define FEATURE_DPM_SOCCLK_BIT 5 82 #define FEATURE_DPM_MP0CLK_BIT 6 83 #define FEATURE_DPM_LINK_BIT 7 84 #define FEATURE_DPM_DCEFCLK_BIT 8 85 #define FEATURE_DPM_XGMI_BIT 9 86 #define FEATURE_MEM_VDDCI_SCALING_BIT 10 87 #define FEATURE_MEM_MVDD_SCALING_BIT 11 88 89 //Idle 90 #define FEATURE_DS_GFXCLK_BIT 12 91 #define FEATURE_DS_SOCCLK_BIT 13 92 #define FEATURE_DS_FCLK_BIT 14 93 #define FEATURE_DS_LCLK_BIT 15 94 #define FEATURE_DS_DCEFCLK_BIT 16 95 #define FEATURE_DS_UCLK_BIT 17 96 #define FEATURE_GFX_ULV_BIT 18 97 #define FEATURE_FW_DSTATE_BIT 19 98 #define FEATURE_GFXOFF_BIT 20 99 #define FEATURE_BACO_BIT 21 100 #define FEATURE_MM_DPM_PG_BIT 22 101 #define FEATURE_SPARE_23_BIT 23 102 //Throttler/Response 103 #define FEATURE_PPT_BIT 24 104 #define FEATURE_TDC_BIT 25 105 #define FEATURE_APCC_PLUS_BIT 26 106 #define FEATURE_GTHR_BIT 27 107 #define FEATURE_ACDC_BIT 28 108 #define FEATURE_VR0HOT_BIT 29 109 #define FEATURE_VR1HOT_BIT 30 110 #define FEATURE_FW_CTF_BIT 31 111 #define FEATURE_FAN_CONTROL_BIT 32 112 #define FEATURE_THERMAL_BIT 33 113 #define FEATURE_GFX_DCS_BIT 34 114 //VF 115 #define FEATURE_RM_BIT 35 116 #define FEATURE_LED_DISPLAY_BIT 36 117 //Other 118 #define FEATURE_GFX_SS_BIT 37 119 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 120 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 121 122 #define FEATURE_MMHUB_PG_BIT 40 123 #define FEATURE_ATHUB_PG_BIT 41 124 #define FEATURE_APCC_DFLL_BIT 42 125 #define FEATURE_DF_SUPERV_BIT 43 126 #define FEATURE_RSMU_SMN_CG_BIT 44 127 #define FEATURE_DF_CSTATE_BIT 45 128 #define FEATURE_2_STEP_PSTATE_BIT 46 129 #define FEATURE_SMNCLK_DPM_BIT 47 130 #define FEATURE_PERLINK_GMIDOWN_BIT 48 131 #define FEATURE_GFX_EDC_BIT 49 132 #define FEATURE_SPARE_50_BIT 50 133 #define FEATURE_SPARE_51_BIT 51 134 #define FEATURE_SPARE_52_BIT 52 135 #define FEATURE_SPARE_53_BIT 53 136 #define FEATURE_SPARE_54_BIT 54 137 #define FEATURE_SPARE_55_BIT 55 138 #define FEATURE_SPARE_56_BIT 56 139 #define FEATURE_SPARE_57_BIT 57 140 #define FEATURE_SPARE_58_BIT 58 141 #define FEATURE_SPARE_59_BIT 59 142 #define FEATURE_SPARE_60_BIT 60 143 #define FEATURE_SPARE_61_BIT 61 144 #define FEATURE_SPARE_62_BIT 62 145 #define FEATURE_SPARE_63_BIT 63 146 #define NUM_FEATURES 64 147 148 //For use with feature control messages 149 typedef enum { 150 FEATURE_PWR_ALL, 151 FEATURE_PWR_S5, 152 FEATURE_PWR_BACO, 153 FEATURE_PWR_SOC, 154 FEATURE_PWR_GFX, 155 FEATURE_PWR_DOMAIN_COUNT, 156 } FEATURE_PWR_DOMAIN_e; 157 158 159 // Debug Overrides Bitmask 160 #define DPM_OVERRIDE_DISABLE_FCLK_PID 0x00000001 161 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 162 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000004 163 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_FCLK 0x00000008 164 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_FCLK 0x00000010 165 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020 166 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040 167 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_FCLK 0x00000080 168 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100 169 #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200 170 #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400 171 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK 0x00000800 172 #define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00001000 173 #define DPM_OVERRIDE_DISABLE_VCN_PG 0x00002000 174 #define DPM_OVERRIDE_DISABLE_FMAX_VMAX 0x00004000 175 176 // VR Mapping Bit Defines 177 #define VR_MAPPING_VR_SELECT_MASK 0x01 178 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 179 180 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 181 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 182 183 // PSI Bit Defines 184 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 185 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 186 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 187 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 188 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 189 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 190 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 191 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 192 193 // Throttler Control/Status Bits 194 #define THROTTLER_PADDING_BIT 0 195 #define THROTTLER_TEMP_EDGE_BIT 1 196 #define THROTTLER_TEMP_HOTSPOT_BIT 2 197 #define THROTTLER_TEMP_MEM_BIT 3 198 #define THROTTLER_TEMP_VR_GFX_BIT 4 199 #define THROTTLER_TEMP_VR_MEM0_BIT 5 200 #define THROTTLER_TEMP_VR_MEM1_BIT 6 201 #define THROTTLER_TEMP_VR_SOC_BIT 7 202 #define THROTTLER_TEMP_LIQUID0_BIT 8 203 #define THROTTLER_TEMP_LIQUID1_BIT 9 204 #define THROTTLER_TEMP_PLX_BIT 10 205 #define THROTTLER_TDC_GFX_BIT 11 206 #define THROTTLER_TDC_SOC_BIT 12 207 #define THROTTLER_PPT0_BIT 13 208 #define THROTTLER_PPT1_BIT 14 209 #define THROTTLER_PPT2_BIT 15 210 #define THROTTLER_PPT3_BIT 16 211 #define THROTTLER_FIT_BIT 17 212 #define THROTTLER_PPM_BIT 18 213 #define THROTTLER_APCC_BIT 19 214 215 // FW DState Features Control Bits 216 // FW DState Features Control Bits 217 #define FW_DSTATE_SOC_ULV_BIT 0 218 #define FW_DSTATE_G6_HSR_BIT 1 219 #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2 220 #define FW_DSTATE_MP0_DS_BIT 3 221 #define FW_DSTATE_SMN_DS_BIT 4 222 #define FW_DSTATE_MP1_DS_BIT 5 223 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 224 #define FW_DSTATE_SOC_LIV_MIN_BIT 7 225 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 226 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 9 227 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10 228 #define FW_DSTATE_MEM_PSI_BIT 11 229 230 #define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) 231 #define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) 232 #define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) 233 #define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) 234 #define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) 235 #define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) 236 #define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) 237 #define FW_DSTATE_SOC_LIV_MIN_MASK (1 << FW_DSTATE_SOC_LIV_MIN_BIT ) 238 #define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT ) 239 #define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 << FW_DSTATE_MEM_PLL_PWRDN_BIT ) 240 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 << FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT ) 241 #define FW_DSTATE_MEM_PSI_MASK (1 << FW_DSTATE_MEM_PSI_BIT ) 242 243 // GFX GPO Feature Contains PACE and DEM sub features 244 #define GFX_GPO_PACE_BIT 0 245 #define GFX_GPO_DEM_BIT 1 246 247 #define GFX_GPO_PACE_MASK (1 << GFX_GPO_PACE_BIT) 248 #define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT ) 249 250 #define GPO_UPDATE_REQ_UCLKDPM_MASK 0x1 251 #define GPO_UPDATE_REQ_FCLKDPM_MASK 0x2 252 #define GPO_UPDATE_REQ_MALLHIT_MASK 0x4 253 254 255 //LED Display Mask & Control Bits 256 #define LED_DISPLAY_GFX_DPM_BIT 0 257 #define LED_DISPLAY_PCIE_BIT 1 258 #define LED_DISPLAY_ERROR_BIT 2 259 260 //RLC Pace Table total number of levels 261 #define RLC_PACE_TABLE_NUM_LEVELS 16 262 263 typedef enum { 264 DRAM_BIT_WIDTH_DISABLED = 0, 265 DRAM_BIT_WIDTH_X_8, 266 DRAM_BIT_WIDTH_X_16, 267 DRAM_BIT_WIDTH_X_32, 268 DRAM_BIT_WIDTH_X_64, // NOT USED. 269 DRAM_BIT_WIDTH_X_128, 270 DRAM_BIT_WIDTH_COUNT, 271 } DRAM_BIT_WIDTH_TYPE_e; 272 273 //I2C Interface 274 #define NUM_I2C_CONTROLLERS 16 275 276 #define I2C_CONTROLLER_ENABLED 1 277 #define I2C_CONTROLLER_DISABLED 0 278 279 #define MAX_SW_I2C_COMMANDS 24 280 281 typedef enum { 282 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 283 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 284 I2C_CONTROLLER_PORT_COUNT, 285 } I2cControllerPort_e; 286 287 typedef enum { 288 I2C_CONTROLLER_NAME_VR_GFX = 0, 289 I2C_CONTROLLER_NAME_VR_SOC, 290 I2C_CONTROLLER_NAME_VR_VDDCI, 291 I2C_CONTROLLER_NAME_VR_MVDD, 292 I2C_CONTROLLER_NAME_LIQUID0, 293 I2C_CONTROLLER_NAME_LIQUID1, 294 I2C_CONTROLLER_NAME_PLX, 295 I2C_CONTROLLER_NAME_OTHER, 296 I2C_CONTROLLER_NAME_COUNT, 297 } I2cControllerName_e; 298 299 typedef enum { 300 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 301 I2C_CONTROLLER_THROTTLER_VR_GFX, 302 I2C_CONTROLLER_THROTTLER_VR_SOC, 303 I2C_CONTROLLER_THROTTLER_VR_VDDCI, 304 I2C_CONTROLLER_THROTTLER_VR_MVDD, 305 I2C_CONTROLLER_THROTTLER_LIQUID0, 306 I2C_CONTROLLER_THROTTLER_LIQUID1, 307 I2C_CONTROLLER_THROTTLER_PLX, 308 I2C_CONTROLLER_THROTTLER_INA3221, 309 I2C_CONTROLLER_THROTTLER_COUNT, 310 } I2cControllerThrottler_e; 311 312 typedef enum { 313 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 314 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 315 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 316 I2C_CONTROLLER_PROTOCOL_INA3221, 317 I2C_CONTROLLER_PROTOCOL_COUNT, 318 } I2cControllerProtocol_e; 319 320 typedef struct { 321 uint8_t Enabled; 322 uint8_t Speed; 323 uint8_t SlaveAddress; 324 uint8_t ControllerPort; 325 uint8_t ControllerName; 326 uint8_t ThermalThrotter; 327 uint8_t I2cProtocol; 328 uint8_t PaddingConfig; 329 } I2cControllerConfig_t; 330 331 typedef enum { 332 I2C_PORT_SVD_SCL = 0, 333 I2C_PORT_GPIO, 334 } I2cPort_e; 335 336 typedef enum { 337 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 338 I2C_SPEED_FAST_100K, //100 Kbits/s 339 I2C_SPEED_FAST_400K, //400 Kbits/s 340 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 341 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 342 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 343 I2C_SPEED_COUNT, 344 } I2cSpeed_e; 345 346 typedef enum { 347 I2C_CMD_READ = 0, 348 I2C_CMD_WRITE, 349 I2C_CMD_COUNT, 350 } I2cCmdType_e; 351 352 typedef enum { 353 FAN_MODE_AUTO = 0, 354 FAN_MODE_MANUAL_LINEAR, 355 } FanMode_e; 356 357 #define CMDCONFIG_STOP_BIT 0 358 #define CMDCONFIG_RESTART_BIT 1 359 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 360 361 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 362 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 363 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 364 365 typedef struct { 366 uint8_t ReadWriteData; //Return data for read. Data to send for write 367 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 368 } SwI2cCmd_t; //SW I2C Command Table 369 370 typedef struct { 371 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 372 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 373 uint8_t SlaveAddress; //Slave address of device 374 uint8_t NumCmds; //Number of commands 375 376 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 377 } SwI2cRequest_t; // SW I2C Request Table 378 379 typedef struct { 380 SwI2cRequest_t SwI2cRequest; 381 382 uint32_t Spare[8]; 383 uint32_t MmHubPadding[8]; // SMU internal use 384 } SwI2cRequestExternal_t; 385 386 //D3HOT sequences 387 typedef enum { 388 BACO_SEQUENCE, 389 MSR_SEQUENCE, 390 BAMACO_SEQUENCE, 391 ULPS_SEQUENCE, 392 D3HOT_SEQUENCE_COUNT, 393 } D3HOTSequence_e; 394 395 //THis is aligned with RSMU PGFSM Register Mapping 396 typedef enum { 397 PG_DYNAMIC_MODE = 0, 398 PG_STATIC_MODE, 399 } PowerGatingMode_e; 400 401 //This is aligned with RSMU PGFSM Register Mapping 402 typedef enum { 403 PG_POWER_DOWN = 0, 404 PG_POWER_UP, 405 } PowerGatingSettings_e; 406 407 typedef struct { 408 uint32_t a; // store in IEEE float format in this variable 409 uint32_t b; // store in IEEE float format in this variable 410 uint32_t c; // store in IEEE float format in this variable 411 } QuadraticInt_t; 412 413 typedef struct { 414 uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 415 uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 416 uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 417 } QuadraticFixedPoint_t; 418 419 typedef struct { 420 uint32_t m; // store in IEEE float format in this variable 421 uint32_t b; // store in IEEE float format in this variable 422 } LinearInt_t; 423 424 typedef struct { 425 uint32_t a; // store in IEEE float format in this variable 426 uint32_t b; // store in IEEE float format in this variable 427 uint32_t c; // store in IEEE float format in this variable 428 } DroopInt_t; 429 430 //Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL 431 #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5 432 typedef enum { 433 PIECEWISE_LINEAR_FUSED_MODEL = 0, 434 PIECEWISE_LINEAR_PP_MODEL, 435 QUADRATIC_PP_MODEL, 436 } DfllDroopModelSelect_e; 437 438 typedef struct { 439 uint32_t Fset[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in GHz, store in IEEE float format 440 uint32_t Vdroop[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in V , store in IEEE float format 441 }PiecewiseLinearDroopInt_t; 442 443 typedef enum { 444 GFXCLK_SOURCE_PLL = 0, 445 GFXCLK_SOURCE_DFLL, 446 GFXCLK_SOURCE_COUNT, 447 } GFXCLK_SOURCE_e; 448 449 //Only Clks that have DPM descriptors are listed here 450 typedef enum { 451 PPCLK_GFXCLK = 0, 452 PPCLK_SOCCLK, 453 PPCLK_UCLK, 454 PPCLK_FCLK, 455 PPCLK_DCLK_0, 456 PPCLK_VCLK_0, 457 PPCLK_DCLK_1, 458 PPCLK_VCLK_1, 459 PPCLK_DCEFCLK, 460 PPCLK_DISPCLK, 461 PPCLK_PIXCLK, 462 PPCLK_PHYCLK, 463 PPCLK_DTBCLK, 464 PPCLK_COUNT, 465 } PPCLK_e; 466 467 typedef enum { 468 VOLTAGE_MODE_AVFS = 0, 469 VOLTAGE_MODE_AVFS_SS, 470 VOLTAGE_MODE_SS, 471 VOLTAGE_MODE_COUNT, 472 } VOLTAGE_MODE_e; 473 474 475 typedef enum { 476 AVFS_VOLTAGE_GFX = 0, 477 AVFS_VOLTAGE_SOC, 478 AVFS_VOLTAGE_COUNT, 479 } AVFS_VOLTAGE_TYPE_e; 480 481 typedef enum { 482 UCLK_DIV_BY_1 = 0, 483 UCLK_DIV_BY_2, 484 UCLK_DIV_BY_4, 485 UCLK_DIV_BY_8, 486 } UCLK_DIV_e; 487 488 typedef enum { 489 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 490 GPIO_INT_POLARITY_ACTIVE_HIGH, 491 } GpioIntPolarity_e; 492 493 typedef enum { 494 PWR_CONFIG_TDP = 0, 495 PWR_CONFIG_TGP, 496 PWR_CONFIG_TCP_ESTIMATED, 497 PWR_CONFIG_TCP_MEASURED, 498 } PwrConfig_e; 499 500 typedef enum { 501 XGMI_LINK_RATE_2 = 2, // 2Gbps 502 XGMI_LINK_RATE_4 = 4, // 4Gbps 503 XGMI_LINK_RATE_8 = 8, // 8Gbps 504 XGMI_LINK_RATE_12 = 12, // 12Gbps 505 XGMI_LINK_RATE_16 = 16, // 16Gbps 506 XGMI_LINK_RATE_17 = 17, // 17Gbps 507 XGMI_LINK_RATE_18 = 18, // 18Gbps 508 XGMI_LINK_RATE_19 = 19, // 19Gbps 509 XGMI_LINK_RATE_20 = 20, // 20Gbps 510 XGMI_LINK_RATE_21 = 21, // 21Gbps 511 XGMI_LINK_RATE_22 = 22, // 22Gbps 512 XGMI_LINK_RATE_23 = 23, // 23Gbps 513 XGMI_LINK_RATE_24 = 24, // 24Gbps 514 XGMI_LINK_RATE_25 = 25, // 25Gbps 515 XGMI_LINK_RATE_COUNT 516 } XGMI_LINK_RATE_e; 517 518 typedef enum { 519 XGMI_LINK_WIDTH_1 = 0, // x1 520 XGMI_LINK_WIDTH_2, // x2 521 XGMI_LINK_WIDTH_4, // x4 522 XGMI_LINK_WIDTH_8, // x8 523 XGMI_LINK_WIDTH_9, // x9 524 XGMI_LINK_WIDTH_16, // x16 525 XGMI_LINK_WIDTH_COUNT 526 } XGMI_LINK_WIDTH_e; 527 528 typedef struct { 529 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 530 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 531 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 532 uint8_t Padding; 533 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 534 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 535 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 536 uint16_t Padding16; 537 } DpmDescriptor_t; 538 539 typedef enum { 540 PPT_THROTTLER_PPT0, 541 PPT_THROTTLER_PPT1, 542 PPT_THROTTLER_PPT2, 543 PPT_THROTTLER_PPT3, 544 PPT_THROTTLER_COUNT 545 } PPT_THROTTLER_e; 546 547 typedef enum { 548 TEMP_EDGE, 549 TEMP_HOTSPOT, 550 TEMP_MEM, 551 TEMP_VR_GFX, 552 TEMP_VR_MEM0, 553 TEMP_VR_MEM1, 554 TEMP_VR_SOC, 555 TEMP_LIQUID0, 556 TEMP_LIQUID1, 557 TEMP_PLX, 558 TEMP_COUNT, 559 } TEMP_e; 560 561 typedef enum { 562 TDC_THROTTLER_GFX, 563 TDC_THROTTLER_SOC, 564 TDC_THROTTLER_COUNT 565 } TDC_THROTTLER_e; 566 567 typedef enum { 568 CUSTOMER_VARIANT_ROW, 569 CUSTOMER_VARIANT_FALCON, 570 CUSTOMER_VARIANT_COUNT, 571 } CUSTOMER_VARIANT_e; 572 573 // Used for 2-step UCLK DPM change workaround 574 typedef struct { 575 uint16_t Fmin; 576 uint16_t Fmax; 577 } UclkDpmChangeRange_t; 578 579 typedef struct { 580 // MAJOR SECTION: SKU PARAMETERS 581 582 uint32_t Version; 583 584 // SECTION: Feature Enablement 585 uint32_t FeaturesToRun[NUM_FEATURES / 32]; 586 587 // SECTION: Infrastructure Limits 588 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts 589 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 590 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts 591 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 592 593 uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps 594 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms 595 596 uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius 597 598 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 599 600 // SECTION: Power Configuration 601 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e 602 uint8_t TotalPowerPadding[3]; 603 604 // SECTION: APCC Settings 605 uint32_t ApccPlusResidencyLimit; 606 607 //SECTION: SMNCLK DPM 608 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz 609 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) 610 611 uint32_t PaddingAPCC[4]; 612 613 // SECTION: Throttler settings 614 uint32_t ThrottlerControlMask; // See Throtter masks defines 615 616 // SECTION: FW DSTATE Settings 617 uint32_t FwDStateMask; // See FW DState masks defines 618 619 // SECTION: ULV Settings 620 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 621 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 622 623 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 624 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 625 626 uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC 627 uint16_t PaddingLIVmin; 628 629 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events 630 uint8_t paddingRlcUlvParams[3]; 631 632 // SECTION: Voltage Control Parameters 633 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 634 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 635 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 636 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 637 638 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 639 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 640 641 // SECTION: Temperature Dependent Vmin 642 uint16_t VDDGFX_TVmin; //Celcius 643 uint16_t VDDSOC_TVmin; //Celcius 644 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 645 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 646 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 647 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 648 649 uint16_t VDDGFX_TVminHystersis; // Celcius 650 uint16_t VDDSOC_TVminHystersis; // Celcius 651 652 //SECTION: DPM Config 1 653 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 654 655 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 656 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 657 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 658 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 659 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 660 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 661 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 662 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 663 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 664 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 665 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 666 uint32_t Paddingclks[16]; 667 668 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 669 670 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 671 672 // Used for MALL performance boost 673 uint16_t FclkBoostFreq; // In Mhz 674 uint16_t FclkParamPadding; 675 676 // SECTION: DPM Config 2 677 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 678 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 679 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 680 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 681 // GFXCLK DPM 682 uint16_t GfxclkFgfxoffEntry; // in Mhz 683 uint16_t GfxclkFinit; // in Mhz 684 uint16_t GfxclkFidle; // in MHz 685 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 686 uint8_t GfxclkPadding; 687 688 // GFX GPO 689 uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM 690 uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled 691 uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled 692 uint8_t GfxGpoPadding[1]; 693 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation 694 695 uint32_t GfxGpoPadding32[4]; 696 697 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz 698 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz 699 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz 700 701 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 702 703 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 704 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 705 706 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 707 708 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 709 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 710 711 uint32_t DcsParamPadding[5]; 712 713 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8 714 715 // UCLK section 716 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 717 uint8_t PaddingMem[3]; 718 719 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 720 721 // Used for 2-Step UCLK change workaround 722 UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz 723 UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz 724 uint16_t UclkDpmMidstepFreq; // In Mhz 725 uint16_t UclkMidstepPadding; 726 727 // Link DPM Settings 728 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 729 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 730 uint16_t LclkFreq[NUM_LINK_LEVELS]; 731 732 // SECTION: Fan Control 733 uint16_t FanStopTemp; //Celcius 734 uint16_t FanStartTemp; //Celcius 735 736 uint16_t FanGain[TEMP_COUNT]; 737 738 uint16_t FanPwmMin; 739 uint16_t FanAcousticLimitRpm; 740 uint16_t FanThrottlingRpm; 741 uint16_t FanMaximumRpm; 742 uint16_t MGpuFanBoostLimitRpm; 743 uint16_t FanTargetTemperature; 744 uint16_t FanTargetGfxclk; 745 uint16_t FanPadding16; 746 uint8_t FanTempInputSelect; 747 uint8_t FanPadding; 748 uint8_t FanZeroRpmEnable; 749 uint8_t FanTachEdgePerRev; 750 751 // The following are AFC override parameters. Leave at 0 to use FW defaults. 752 int16_t FuzzyFan_ErrorSetDelta; 753 int16_t FuzzyFan_ErrorRateSetDelta; 754 int16_t FuzzyFan_PwmSetDelta; 755 uint16_t FuzzyFan_Reserved; 756 757 // SECTION: AVFS 758 // Overrides 759 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 760 uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) 761 uint8_t Padding8_Avfs; 762 763 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 764 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 765 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 766 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 767 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 768 769 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format 770 771 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 772 773 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 774 775 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 776 uint8_t Padding8_GfxBtc[2]; 777 778 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 779 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 780 781 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 782 783 // SECTION: XGMI 784 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 785 uint8_t XgmiDpmSpare[2]; 786 787 // SECTION: Advanced Options 788 uint32_t DebugOverrides; 789 QuadraticInt_t ReservedEquation0; 790 QuadraticInt_t ReservedEquation1; 791 QuadraticInt_t ReservedEquation2; 792 QuadraticInt_t ReservedEquation3; 793 794 // SECTION: Sku Reserved 795 uint8_t CustomerVariant; 796 797 //VC BTC parameters are only applicable to VDD_GFX domain 798 uint8_t VcBtcEnabled; 799 uint16_t VcBtcVminT0; // T0_VMIN 800 uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET 801 uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB 802 uint32_t VcBtcPsmA; // A_PSM 803 uint32_t VcBtcPsmB; // B_PSM 804 uint32_t VcBtcVminA; // A_VMIN 805 uint32_t VcBtcVminB; // B_VMIN 806 807 uint32_t SkuReserved[9]; 808 809 810 // MAJOR SECTION: BOARD PARAMETERS 811 812 //SECTION: Gaming Clocks 813 uint32_t GamingClk[6]; 814 815 // SECTION: I2C Control 816 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 817 818 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 819 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 820 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 821 uint8_t I2cSpare[1]; 822 823 // SECTION: SVI2 Board Parameters 824 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 825 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 826 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 827 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 828 829 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 830 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 831 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 832 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 833 834 // SECTION: Telemetry Settings 835 uint16_t GfxMaxCurrent; // in Amps 836 int8_t GfxOffset; // in Amps 837 uint8_t Padding_TelemetryGfx; 838 839 uint16_t SocMaxCurrent; // in Amps 840 int8_t SocOffset; // in Amps 841 uint8_t Padding_TelemetrySoc; 842 843 uint16_t Mem0MaxCurrent; // in Amps 844 int8_t Mem0Offset; // in Amps 845 uint8_t Padding_TelemetryMem0; 846 847 uint16_t Mem1MaxCurrent; // in Amps 848 int8_t Mem1Offset; // in Amps 849 uint8_t Padding_TelemetryMem1; 850 851 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 852 853 // SECTION: GPIO Settings 854 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 855 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 856 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 857 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 858 859 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 860 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 861 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 862 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 863 864 // LED Display Settings 865 uint8_t LedPin0; // GPIO number for LedPin[0] 866 uint8_t LedPin1; // GPIO number for LedPin[1] 867 uint8_t LedPin2; // GPIO number for LedPin[2] 868 uint8_t LedEnableMask; 869 870 uint8_t LedPcie; // GPIO number for PCIE results 871 uint8_t LedError; // GPIO number for Error Cases 872 uint8_t LedSpare1[2]; 873 874 // SECTION: Clock Spread Spectrum 875 876 // GFXCLK PLL Spread Spectrum 877 uint8_t PllGfxclkSpreadEnabled; // on or off 878 uint8_t PllGfxclkSpreadPercent; // Q4.4 879 uint16_t PllGfxclkSpreadFreq; // kHz 880 881 // GFXCLK DFLL Spread Spectrum 882 uint8_t DfllGfxclkSpreadEnabled; // on or off 883 uint8_t DfllGfxclkSpreadPercent; // Q4.4 884 uint16_t DfllGfxclkSpreadFreq; // kHz 885 886 // UCLK Spread Spectrum 887 uint16_t UclkSpreadPadding; 888 uint16_t UclkSpreadFreq; // kHz 889 890 // FCLK Spread Spectrum 891 uint8_t FclkSpreadEnabled; // on or off 892 uint8_t FclkSpreadPercent; // Q4.4 893 uint16_t FclkSpreadFreq; // kHz 894 895 // Section: Memory Config 896 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 897 898 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 899 uint8_t PaddingMem1[3]; 900 901 // Section: Total Board Power 902 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 903 uint16_t BoardPowerPadding; 904 905 // SECTION: XGMI Training 906 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 907 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 908 909 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 910 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 911 912 // SECTION: UMC feature flags 913 uint8_t HsrEnabled; 914 uint8_t VddqOffEnabled; 915 uint8_t PaddingUmcFlags[2]; 916 917 // UCLK Spread Spectrum 918 uint8_t UclkSpreadPercent[16]; 919 920 // SECTION: Board Reserved 921 uint32_t BoardReserved[11]; 922 923 // SECTION: Structure Padding 924 925 // Padding for MMHUB - do not modify this 926 uint32_t MmHubPadding[8]; // SMU internal use 927 928 } PPTable_t; 929 930 typedef struct { 931 // Time constant parameters for clock averages in ms 932 uint16_t GfxclkAverageLpfTau; 933 uint16_t FclkAverageLpfTau; 934 uint16_t UclkAverageLpfTau; 935 uint16_t GfxActivityLpfTau; 936 uint16_t UclkActivityLpfTau; 937 uint16_t SocketPowerLpfTau; 938 uint16_t VcnClkAverageLpfTau; 939 uint16_t padding16; 940 } DriverSmuConfig_t; 941 942 typedef struct { 943 DriverSmuConfig_t DriverSmuConfig; 944 945 uint32_t Spare[7]; 946 // Padding - ignore 947 uint32_t MmHubPadding[8]; // SMU internal use 948 } DriverSmuConfigExternal_t; 949 950 typedef struct { 951 uint16_t GfxclkFmin; // MHz 952 uint16_t GfxclkFmax; // MHz 953 QuadraticInt_t CustomGfxVfCurve; // a: mV/MHz^2, b: mv/MHz, c: mV 954 uint16_t CustomCurveFmin; // MHz 955 uint16_t UclkFmin; // MHz 956 uint16_t UclkFmax; // MHz 957 int16_t OverDrivePct; // % 958 uint16_t FanMaximumRpm; 959 uint16_t FanMinimumPwm; 960 uint16_t FanAcousticLimitRpm; 961 uint16_t FanTargetTemperature; // Degree Celcius 962 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 963 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 964 uint16_t MaxOpTemp; // Degree Celcius 965 int16_t VddGfxOffset; // in mV 966 uint8_t FanZeroRpmEnable; 967 uint8_t FanZeroRpmStopTemp; 968 uint8_t FanMode; 969 uint8_t Padding[1]; 970 } OverDriveTable_t; 971 972 typedef struct { 973 OverDriveTable_t OverDriveTable; 974 uint32_t Spare[8]; 975 976 uint32_t MmHubPadding[8]; // SMU internal use 977 } OverDriveTableExternal_t; 978 979 typedef struct { 980 uint32_t CurrClock[PPCLK_COUNT]; 981 982 uint16_t AverageGfxclkFrequencyPreDs; 983 uint16_t AverageGfxclkFrequencyPostDs; 984 uint16_t AverageFclkFrequencyPreDs; 985 uint16_t AverageFclkFrequencyPostDs; 986 uint16_t AverageUclkFrequencyPreDs ; 987 uint16_t AverageUclkFrequencyPostDs ; 988 989 990 uint16_t AverageGfxActivity ; 991 uint16_t AverageUclkActivity ; 992 uint8_t CurrSocVoltageOffset ; 993 uint8_t CurrGfxVoltageOffset ; 994 uint8_t CurrMemVidOffset ; 995 uint8_t Padding8 ; 996 uint16_t AverageSocketPower ; 997 uint16_t TemperatureEdge ; 998 uint16_t TemperatureHotspot ; 999 uint16_t TemperatureMem ; 1000 uint16_t TemperatureVrGfx ; 1001 uint16_t TemperatureVrMem0 ; 1002 uint16_t TemperatureVrMem1 ; 1003 uint16_t TemperatureVrSoc ; 1004 uint16_t TemperatureLiquid0 ; 1005 uint16_t TemperatureLiquid1 ; 1006 uint16_t TemperaturePlx ; 1007 uint16_t Padding16 ; 1008 uint32_t ThrottlerStatus ; 1009 1010 uint8_t LinkDpmLevel; 1011 uint8_t CurrFanPwm; 1012 uint16_t CurrFanSpeed; 1013 1014 //BACO metrics, PMFW-1721 1015 //metrics for D3hot entry/exit and driver ARM msgs 1016 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1017 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1018 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1019 1020 //PMFW-4362 1021 uint32_t EnergyAccumulator; 1022 uint16_t AverageVclk0Frequency ; 1023 uint16_t AverageDclk0Frequency ; 1024 uint16_t AverageVclk1Frequency ; 1025 uint16_t AverageDclk1Frequency ; 1026 uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1027 uint8_t PcieRate ; 1028 uint8_t PcieWidth ; 1029 1030 } SmuMetrics_t; 1031 1032 typedef struct { 1033 SmuMetrics_t SmuMetrics; 1034 uint32_t Spare[1]; 1035 1036 // Padding - ignore 1037 uint32_t MmHubPadding[8]; // SMU internal use 1038 } SmuMetricsExternal_t; 1039 1040 typedef struct { 1041 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 1042 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 1043 uint16_t MinUclk; 1044 uint16_t MaxUclk; 1045 1046 uint8_t WmSetting; 1047 uint8_t Flags; 1048 uint8_t Padding[2]; 1049 1050 } WatermarkRowGeneric_t; 1051 1052 #define NUM_WM_RANGES 4 1053 1054 typedef enum { 1055 WM_SOCCLK = 0, 1056 WM_DCEFCLK, 1057 WM_COUNT, 1058 } WM_CLOCK_e; 1059 1060 typedef enum { 1061 WATERMARKS_CLOCK_RANGE = 0, 1062 WATERMARKS_DUMMY_PSTATE, 1063 WATERMARKS_MALL, 1064 WATERMARKS_COUNT, 1065 } WATERMARKS_FLAGS_e; 1066 1067 typedef struct { 1068 // Watermarks 1069 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 1070 } Watermarks_t; 1071 1072 typedef struct { 1073 Watermarks_t Watermarks; 1074 1075 uint32_t MmHubPadding[8]; // SMU internal use 1076 } WatermarksExternal_t; 1077 1078 typedef struct { 1079 uint16_t avgPsmCount[67]; 1080 uint16_t minPsmCount[67]; 1081 float avgPsmVoltage[67]; 1082 float minPsmVoltage[67]; 1083 } AvfsDebugTable_t; 1084 1085 typedef struct { 1086 AvfsDebugTable_t AvfsDebugTable; 1087 1088 uint32_t MmHubPadding[8]; // SMU internal use 1089 } AvfsDebugTableExternal_t; 1090 1091 typedef struct { 1092 uint8_t AvfsVersion; 1093 uint8_t Padding; 1094 1095 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 1096 1097 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 1098 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1099 1100 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 1101 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 1102 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 1103 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 1104 1105 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1106 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1107 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 1108 1109 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1110 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1111 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 1112 1113 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1114 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1115 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 1116 1117 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1118 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1119 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 1120 1121 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1122 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1123 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 1124 1125 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 1126 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 1127 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 1128 1129 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 1130 1131 1132 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1133 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1134 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 1135 1136 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 1137 1138 uint32_t EnabledAvfsModules[3]; //Sienna_Cichlid - 67 AVFS modules 1139 } AvfsFuseOverride_t; 1140 1141 typedef struct { 1142 AvfsFuseOverride_t AvfsFuseOverride; 1143 1144 uint32_t MmHubPadding[8]; // SMU internal use 1145 } AvfsFuseOverrideExternal_t; 1146 1147 typedef struct { 1148 uint8_t Gfx_ActiveHystLimit; 1149 uint8_t Gfx_IdleHystLimit; 1150 uint8_t Gfx_FPS; 1151 uint8_t Gfx_MinActiveFreqType; 1152 uint8_t Gfx_BoosterFreqType; 1153 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1154 uint16_t Gfx_MinActiveFreq; // MHz 1155 uint16_t Gfx_BoosterFreq; // MHz 1156 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1157 uint32_t Gfx_PD_Data_limit_a; // Q16 1158 uint32_t Gfx_PD_Data_limit_b; // Q16 1159 uint32_t Gfx_PD_Data_limit_c; // Q16 1160 uint32_t Gfx_PD_Data_error_coeff; // Q16 1161 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1162 1163 uint8_t Fclk_ActiveHystLimit; 1164 uint8_t Fclk_IdleHystLimit; 1165 uint8_t Fclk_FPS; 1166 uint8_t Fclk_MinActiveFreqType; 1167 uint8_t Fclk_BoosterFreqType; 1168 uint8_t Fclk_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1169 uint16_t Fclk_MinActiveFreq; // MHz 1170 uint16_t Fclk_BoosterFreq; // MHz 1171 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1172 uint32_t Fclk_PD_Data_limit_a; // Q16 1173 uint32_t Fclk_PD_Data_limit_b; // Q16 1174 uint32_t Fclk_PD_Data_limit_c; // Q16 1175 uint32_t Fclk_PD_Data_error_coeff; // Q16 1176 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1177 1178 uint8_t Mem_ActiveHystLimit; 1179 uint8_t Mem_IdleHystLimit; 1180 uint8_t Mem_FPS; 1181 uint8_t Mem_MinActiveFreqType; 1182 uint8_t Mem_BoosterFreqType; 1183 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1184 uint16_t Mem_MinActiveFreq; // MHz 1185 uint16_t Mem_BoosterFreq; // MHz 1186 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 1187 uint32_t Mem_PD_Data_limit_a; // Q16 1188 uint32_t Mem_PD_Data_limit_b; // Q16 1189 uint32_t Mem_PD_Data_limit_c; // Q16 1190 uint32_t Mem_PD_Data_error_coeff; // Q16 1191 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 1192 1193 uint32_t Mem_UpThreshold_Limit; // Q16 1194 uint8_t Mem_UpHystLimit; 1195 uint8_t Mem_DownHystLimit; 1196 uint16_t Mem_Fps; 1197 1198 } DpmActivityMonitorCoeffInt_t; 1199 1200 1201 typedef struct { 1202 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1203 uint32_t MmHubPadding[8]; // SMU internal use 1204 } DpmActivityMonitorCoeffIntExternal_t; 1205 1206 // Workload bits 1207 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1208 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1209 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1210 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1211 #define WORKLOAD_PPLIB_VR_BIT 4 1212 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1213 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1214 #define WORKLOAD_PPLIB_COUNT 7 1215 1216 1217 // These defines are used with the following messages: 1218 // SMC_MSG_TransferTableDram2Smu 1219 // SMC_MSG_TransferTableSmu2Dram 1220 1221 // Table transfer status 1222 #define TABLE_TRANSFER_OK 0x0 1223 #define TABLE_TRANSFER_FAILED 0xFF 1224 1225 // Table types 1226 #define TABLE_PPTABLE 0 1227 #define TABLE_WATERMARKS 1 1228 #define TABLE_AVFS_PSM_DEBUG 2 1229 #define TABLE_AVFS_FUSE_OVERRIDE 3 1230 #define TABLE_PMSTATUSLOG 4 1231 #define TABLE_SMU_METRICS 5 1232 #define TABLE_DRIVER_SMU_CONFIG 6 1233 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1234 #define TABLE_OVERDRIVE 8 1235 #define TABLE_I2C_COMMANDS 9 1236 #define TABLE_PACE 10 1237 #define TABLE_COUNT 11 1238 1239 typedef struct { 1240 float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; 1241 } RlcPaceFlopsPerByteOverride_t; 1242 1243 typedef struct { 1244 RlcPaceFlopsPerByteOverride_t RlcPaceFlopsPerByteOverride; 1245 1246 uint32_t MmHubPadding[8]; // SMU internal use 1247 } RlcPaceFlopsPerByteOverrideExternal_t; 1248 1249 // These defines are used with the SMC_MSG_SetUclkFastSwitch message. 1250 #define UCLK_SWITCH_SLOW 0 1251 #define UCLK_SWITCH_FAST 1 1252 #endif 1253