1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifndef _FENV_H_
30 #define _FENV_H_
31
32 #include <sys/_types.h>
33 #include <machine/endian.h>
34
35 #ifndef __fenv_static
36 #define __fenv_static static
37 #endif
38
39 typedef __uint32_t fenv_t;
40 typedef __uint32_t fexcept_t;
41
42 /* Exception flags */
43 #define FE_INEXACT 0x02000000
44 #define FE_DIVBYZERO 0x04000000
45 #define FE_UNDERFLOW 0x08000000
46 #define FE_OVERFLOW 0x10000000
47 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */
48
49 /*
50 * The PowerPC architecture has extra invalid flags that indicate the
51 * specific type of invalid operation occurred. These flags may be
52 * tested, set, and cleared---but not masked---separately. All of
53 * these bits are cleared when FE_INVALID is cleared, but only
54 * FE_VXSOFT is set when FE_INVALID is explicitly set in software.
55 */
56 #define FE_VXCVI 0x00000100 /* invalid integer convert */
57 #define FE_VXSQRT 0x00000200 /* square root of a negative */
58 #define FE_VXSOFT 0x00000400 /* software-requested exception */
59 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */
60 #define FE_VXIMZ 0x00100000 /* inf * 0 */
61 #define FE_VXZDZ 0x00200000 /* 0 / 0 */
62 #define FE_VXIDI 0x00400000 /* inf / inf */
63 #define FE_VXISI 0x00800000 /* inf - inf */
64 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */
65 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \
66 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \
67 FE_VXSNAN | FE_INVALID)
68
69 #define _FPUSW_SHIFT 22
70 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
71 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
72
73 /* Rounding modes */
74 #define FE_TONEAREST 0x0000
75 #define FE_TOWARDZERO 0x0001
76 #define FE_UPWARD 0x0002
77 #define FE_DOWNWARD 0x0003
78 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
79 FE_UPWARD | FE_TOWARDZERO)
80
81 __BEGIN_DECLS
82
83 /* Default floating-point environment */
84 extern const fenv_t __fe_dfl_env;
85 #define FE_DFL_ENV (&__fe_dfl_env)
86
87 /* We need to be able to map status flag positions to mask flag positions */
88 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
89 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
90
91 #ifndef _SOFT_FLOAT
92 #define __mffs(__env) \
93 __asm __volatile("mffs %0" : "=f" ((__env)->__d))
94 #define __mtfsf(__env) \
95 __asm __volatile("mtfsf 255,%0" :: "f" ((__env).__d))
96 #else
97 #define __mffs(__env)
98 #define __mtfsf(__env)
99 #endif
100
101 union __fpscr {
102 double __d;
103 struct {
104 #if _BYTE_ORDER == _LITTLE_ENDIAN
105 fenv_t __reg;
106 __uint32_t __junk;
107 #else
108 __uint32_t __junk;
109 fenv_t __reg;
110 #endif
111 } __bits;
112 };
113
114 int feclearexcept(int);
115 #define feclearexcept(a) __feclearexcept_int(a)
116
117 __fenv_static inline int
__feclearexcept_int(int __excepts)118 __feclearexcept_int(int __excepts)
119 {
120 union __fpscr __r;
121
122 if (__excepts & FE_INVALID)
123 __excepts |= FE_ALL_INVALID;
124 __mffs(&__r);
125 __r.__bits.__reg &= ~__excepts;
126 __mtfsf(__r);
127 return (0);
128 }
129
130 __fenv_static inline int
fegetexceptflag(fexcept_t * __flagp,int __excepts)131 fegetexceptflag(fexcept_t *__flagp, int __excepts)
132 {
133 union __fpscr __r;
134
135 __mffs(&__r);
136 *__flagp = __r.__bits.__reg & __excepts;
137 return (0);
138 }
139
140 __fenv_static inline int
fesetexceptflag(const fexcept_t * __flagp,int __excepts)141 fesetexceptflag(const fexcept_t *__flagp, int __excepts)
142 {
143 union __fpscr __r;
144
145 if (__excepts & FE_INVALID)
146 __excepts |= FE_ALL_INVALID;
147 __mffs(&__r);
148 __r.__bits.__reg &= ~__excepts;
149 __r.__bits.__reg |= *__flagp & __excepts;
150 __mtfsf(__r);
151 return (0);
152 }
153
154 __fenv_static inline int
feraiseexcept(int __excepts)155 feraiseexcept(int __excepts)
156 {
157 union __fpscr __r;
158
159 if (__excepts & FE_INVALID)
160 __excepts |= FE_VXSOFT;
161 __mffs(&__r);
162 __r.__bits.__reg |= __excepts;
163 __mtfsf(__r);
164 return (0);
165 }
166
167 __fenv_static inline int
fetestexcept(int __excepts)168 fetestexcept(int __excepts)
169 {
170 union __fpscr __r;
171
172 __mffs(&__r);
173 return (__r.__bits.__reg & __excepts);
174 }
175
176 __fenv_static inline int
fegetround(void)177 fegetround(void)
178 {
179 union __fpscr __r;
180
181 __mffs(&__r);
182 return (__r.__bits.__reg & _ROUND_MASK);
183 }
184
185 __fenv_static inline int
fesetround(int __round)186 fesetround(int __round)
187 {
188 union __fpscr __r;
189
190 if (__round & ~_ROUND_MASK)
191 return (-1);
192 __mffs(&__r);
193 __r.__bits.__reg &= ~_ROUND_MASK;
194 __r.__bits.__reg |= __round;
195 __mtfsf(__r);
196 return (0);
197 }
198
199 __fenv_static inline int
fegetenv(fenv_t * __envp)200 fegetenv(fenv_t *__envp)
201 {
202 union __fpscr __r;
203
204 __mffs(&__r);
205 *__envp = __r.__bits.__reg;
206 return (0);
207 }
208
209 __fenv_static inline int
feholdexcept(fenv_t * __envp)210 feholdexcept(fenv_t *__envp)
211 {
212 union __fpscr __r;
213
214 __mffs(&__r);
215 *__envp = __r.__bits.__reg;
216 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
217 __mtfsf(__r);
218 return (0);
219 }
220
221 __fenv_static inline int
fesetenv(const fenv_t * __envp)222 fesetenv(const fenv_t *__envp)
223 {
224 union __fpscr __r;
225
226 __r.__bits.__reg = *__envp;
227 __mtfsf(__r);
228 return (0);
229 }
230
231 __fenv_static inline int
feupdateenv(const fenv_t * __envp)232 feupdateenv(const fenv_t *__envp)
233 {
234 union __fpscr __r;
235
236 __mffs(&__r);
237 __r.__bits.__reg &= FE_ALL_EXCEPT;
238 __r.__bits.__reg |= *__envp;
239 __mtfsf(__r);
240 return (0);
241 }
242
243 #if __BSD_VISIBLE
244
245 __fenv_static inline int
feenableexcept(int __mask)246 feenableexcept(int __mask)
247 {
248 union __fpscr __r;
249 fenv_t __oldmask;
250
251 __mffs(&__r);
252 __oldmask = __r.__bits.__reg;
253 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
254 __mtfsf(__r);
255 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
256 }
257
258 __fenv_static inline int
fedisableexcept(int __mask)259 fedisableexcept(int __mask)
260 {
261 union __fpscr __r;
262 fenv_t __oldmask;
263
264 __mffs(&__r);
265 __oldmask = __r.__bits.__reg;
266 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
267 __mtfsf(__r);
268 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
269 }
270
271 /* We currently provide no external definition of fegetexcept(). */
272 static inline int
fegetexcept(void)273 fegetexcept(void)
274 {
275 union __fpscr __r;
276
277 __mffs(&__r);
278 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
279 }
280
281 #endif /* __BSD_VISIBLE */
282
283 __END_DECLS
284
285 #endif /* !_FENV_H_ */
286