1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Exynos specific definitions for Samsung pinctrl and gpiolib driver.
4  *
5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6  *		http://www.samsung.com
7  * Copyright (c) 2012 Linaro Ltd
8  *		http://www.linaro.org
9  *
10  * This file contains the Exynos specific definitions for the Samsung
11  * pinctrl/gpiolib interface drivers.
12  *
13  * Author: Thomas Abraham <thomas.ab@samsung.com>
14  */
15 
16 #ifndef __PINCTRL_SAMSUNG_EXYNOS_H
17 #define __PINCTRL_SAMSUNG_EXYNOS_H
18 
19 /* Values for the pin CON register */
20 #define EXYNOS_PIN_CON_FUNC_EINT	0xf
21 
22 /* External GPIO and wakeup interrupt related definitions */
23 #define EXYNOS_GPIO_ECON_OFFSET		0x700
24 #define EXYNOS_GPIO_EFLTCON_OFFSET	0x800
25 #define EXYNOS_GPIO_EMASK_OFFSET	0x900
26 #define EXYNOS_GPIO_EPEND_OFFSET	0xA00
27 #define EXYNOS_WKUP_ECON_OFFSET		0xE00
28 #define EXYNOS_WKUP_EMASK_OFFSET	0xF00
29 #define EXYNOS_WKUP_EPEND_OFFSET	0xF40
30 #define EXYNOS7_WKUP_ECON_OFFSET	0x700
31 #define EXYNOS7_WKUP_EMASK_OFFSET	0x900
32 #define EXYNOS7_WKUP_EPEND_OFFSET	0xA00
33 #define EXYNOS_SVC_OFFSET		0xB08
34 #define EXYNOSAUTO_SVC_OFFSET		0xF008
35 
36 /* helpers to access interrupt service register */
37 #define EXYNOS_SVC_GROUP_SHIFT		3
38 #define EXYNOS_SVC_GROUP_MASK		0x1f
39 #define EXYNOS_SVC_NUM_MASK		7
40 #define EXYNOS_SVC_GROUP(x)		((x >> EXYNOS_SVC_GROUP_SHIFT) & \
41 						EXYNOS_SVC_GROUP_MASK)
42 
43 /* Exynos specific external interrupt trigger types */
44 #define EXYNOS_EINT_LEVEL_LOW		0
45 #define EXYNOS_EINT_LEVEL_HIGH		1
46 #define EXYNOS_EINT_EDGE_FALLING	2
47 #define EXYNOS_EINT_EDGE_RISING		3
48 #define EXYNOS_EINT_EDGE_BOTH		4
49 #define EXYNOS_EINT_CON_MASK		0xF
50 #define EXYNOS_EINT_CON_LEN		4
51 
52 #define EXYNOS_EINT_MAX_PER_BANK	8
53 #define EXYNOS_EINT_NR_WKUP_EINT
54 
55 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id)		\
56 	{						\
57 		.type		= &bank_type_off,	\
58 		.pctl_offset	= reg,			\
59 		.nr_pins	= pins,			\
60 		.eint_type	= EINT_TYPE_NONE,	\
61 		.name		= id			\
62 	}
63 
64 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs)	\
65 	{						\
66 		.type		= &bank_type_off,	\
67 		.pctl_offset	= reg,			\
68 		.nr_pins	= pins,			\
69 		.eint_type	= EINT_TYPE_GPIO,	\
70 		.eint_offset	= offs,			\
71 		.name		= id			\
72 	}
73 
74 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs)	\
75 	{						\
76 		.type		= &bank_type_alive,	\
77 		.pctl_offset	= reg,			\
78 		.nr_pins	= pins,			\
79 		.eint_type	= EINT_TYPE_WKUP,	\
80 		.eint_offset	= offs,			\
81 		.name		= id			\
82 	}
83 
84 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs)		\
85 	{							\
86 		.type		= &exynos5433_bank_type_off,	\
87 		.pctl_offset	= reg,				\
88 		.nr_pins	= pins,				\
89 		.eint_type	= EINT_TYPE_GPIO,		\
90 		.eint_offset	= offs,				\
91 		.name		= id				\
92 	}
93 
94 #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs)		\
95 	{							\
96 		.type		= &exynos5433_bank_type_alive,	\
97 		.pctl_offset	= reg,				\
98 		.nr_pins	= pins,				\
99 		.eint_type	= EINT_TYPE_WKUP,		\
100 		.eint_offset	= offs,				\
101 		.name		= id				\
102 	}
103 
104 #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
105 	{							\
106 		.type           = &exynos5433_bank_type_off,	\
107 		.pctl_offset    = reg,				\
108 		.nr_pins        = pins,				\
109 		.eint_type      = EINT_TYPE_WKUP,		\
110 		.eint_offset    = offs,				\
111 		.name           = id,				\
112 		.pctl_res_idx   = pctl_idx,			\
113 	}							\
114 
115 #define EXYNOS7870_PIN_BANK_EINTN(pins, reg, id)		\
116 	{							\
117 		.type		= &exynos7870_bank_type_alive,	\
118 		.pctl_offset	= reg,				\
119 		.nr_pins	= pins,				\
120 		.eint_type	= EINT_TYPE_NONE,		\
121 		.name		= id				\
122 	}
123 
124 #define EXYNOS7870_PIN_BANK_EINTW(pins, reg, id, offs)		\
125 	{							\
126 		.type		= &exynos7870_bank_type_alive,	\
127 		.pctl_offset	= reg,				\
128 		.nr_pins	= pins,				\
129 		.eint_type	= EINT_TYPE_WKUP,		\
130 		.eint_offset	= offs,				\
131 		.name		= id				\
132 	}
133 
134 #define EXYNOS850_PIN_BANK_EINTN(pins, reg, id)			\
135 	{							\
136 		.type		= &exynos850_bank_type_alive,	\
137 		.pctl_offset	= reg,				\
138 		.nr_pins	= pins,				\
139 		.eint_type	= EINT_TYPE_NONE,		\
140 		.name		= id				\
141 	}
142 
143 #define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs)		\
144 	{							\
145 		.type		= &exynos850_bank_type_off,	\
146 		.pctl_offset	= reg,				\
147 		.nr_pins	= pins,				\
148 		.eint_type	= EINT_TYPE_GPIO,		\
149 		.eint_offset	= offs,				\
150 		.name		= id				\
151 	}
152 
153 #define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs)		\
154 	{							\
155 		.type		= &exynos850_bank_type_alive,	\
156 		.pctl_offset	= reg,				\
157 		.nr_pins	= pins,				\
158 		.eint_type	= EINT_TYPE_WKUP,		\
159 		.eint_offset	= offs,				\
160 		.name		= id				\
161 	}
162 
163 #define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs)		\
164 	{							\
165 		.type		= &exynos8895_bank_type_off,	\
166 		.pctl_offset	= reg,				\
167 		.nr_pins	= pins,				\
168 		.eint_type	= EINT_TYPE_GPIO,		\
169 		.eint_offset	= offs,				\
170 		.name		= id				\
171 	}
172 
173 #define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs)	\
174 	{							\
175 		.type			= &exynos850_bank_type_off,	\
176 		.pctl_offset		= reg,				\
177 		.nr_pins		= pins,				\
178 		.eint_type		= EINT_TYPE_GPIO,		\
179 		.eint_con_offset	= con_offs,			\
180 		.eint_mask_offset	= mask_offs,			\
181 		.eint_pend_offset	= pend_offs,			\
182 		.name			= id				\
183 	}
184 
185 #define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs)	\
186 	{							\
187 		.type			= &exynos850_bank_type_alive,	\
188 		.pctl_offset		= reg,				\
189 		.nr_pins		= pins,				\
190 		.eint_type		= EINT_TYPE_WKUP,		\
191 		.eint_con_offset	= con_offs,			\
192 		.eint_mask_offset	= mask_offs,			\
193 		.eint_pend_offset	= pend_offs,			\
194 		.name			= id				\
195 	}
196 
197 #define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \
198 	{							\
199 		.type			= &exynos850_bank_type_off,	\
200 		.pctl_offset		= reg,			\
201 		.nr_pins		= pins,			\
202 		.eint_type		= EINT_TYPE_GPIO,	\
203 		.eint_offset		= offs,			\
204 		.eint_fltcon_offset	= fltcon_offs,		\
205 		.name			= id			\
206 	}
207 
208 #define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \
209 	{								\
210 		.type			= &exynos850_bank_type_alive,	\
211 		.pctl_offset		= reg,				\
212 		.nr_pins		= pins,				\
213 		.eint_type		= EINT_TYPE_WKUP,		\
214 		.eint_offset		= offs,				\
215 		.eint_fltcon_offset	= fltcon_offs,			\
216 		.name			= id				\
217 	}
218 
219 /**
220  * struct exynos_weint_data: irq specific data for all the wakeup interrupts
221  * generated by the external wakeup interrupt controller.
222  * @irq: interrupt number within the domain.
223  * @bank: bank responsible for this interrupt
224  */
225 struct exynos_weint_data {
226 	unsigned int irq;
227 	struct samsung_pin_bank *bank;
228 };
229 
230 /**
231  * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
232  * generated by the external wakeup interrupt controller.
233  * @nr_banks: count of banks being part of the mux
234  * @banks: array of banks being part of the mux
235  */
236 struct exynos_muxed_weint_data {
237 	unsigned int nr_banks;
238 	struct samsung_pin_bank *banks[] __counted_by(nr_banks);
239 };
240 
241 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
242 int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
243 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata);
244 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata);
245 struct samsung_retention_ctrl *
246 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
247 		      const struct samsung_retention_data *data);
248 
249 #endif /* __PINCTRL_SAMSUNG_EXYNOS_H */
250