1 /*
2 * CPU interfaces that are target independent.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * SPDX-License-Identifier: LGPL-2.1+
7 */
8 #ifndef CPU_COMMON_H
9 #define CPU_COMMON_H
10
11 #include "exec/vaddr.h"
12 #include "exec/hwaddr.h"
13 #include "hw/core/cpu.h"
14 #include "tcg/debug-assert.h"
15 #include "exec/page-protection.h"
16
17 #define EXCP_INTERRUPT 0x10000 /* async interruption */
18 #define EXCP_HLT 0x10001 /* hlt instruction reached */
19 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
20 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
21 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
22 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
23
24 void cpu_exec_init_all(void);
25 void cpu_exec_step_atomic(CPUState *cpu);
26
27 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size())
28
29 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
30 extern QemuMutex qemu_cpu_list_lock;
31 void qemu_init_cpu_list(void);
32 void cpu_list_lock(void);
33 void cpu_list_unlock(void);
34 unsigned int cpu_list_generation_id_get(void);
35
36 int cpu_get_free_index(void);
37
38 void tcg_iommu_init_notifier_list(CPUState *cpu);
39 void tcg_iommu_free_notifier_list(CPUState *cpu);
40
41 enum device_endian {
42 DEVICE_NATIVE_ENDIAN,
43 DEVICE_BIG_ENDIAN,
44 DEVICE_LITTLE_ENDIAN,
45 };
46
47 /* address in the RAM (different from a physical address) */
48 #if defined(CONFIG_XEN_BACKEND)
49 typedef uint64_t ram_addr_t;
50 # define RAM_ADDR_MAX UINT64_MAX
51 # define RAM_ADDR_FMT "%" PRIx64
52 #else
53 typedef uintptr_t ram_addr_t;
54 # define RAM_ADDR_MAX UINTPTR_MAX
55 # define RAM_ADDR_FMT "%" PRIxPTR
56 #endif
57
58 /* memory API */
59
60 void qemu_ram_remap(ram_addr_t addr);
61 /* This should not be used by devices. */
62 ram_addr_t qemu_ram_addr_from_host(void *ptr);
63 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
64 RAMBlock *qemu_ram_block_by_name(const char *name);
65
66 /*
67 * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock.
68 *
69 * @ptr: The host pointer to translate.
70 * @round_offset: Whether to round the result offset down to a target page
71 * @offset: Will be set to the offset within the returned RAMBlock.
72 *
73 * Returns: RAMBlock (or NULL if not found)
74 *
75 * By the time this function returns, the returned pointer is not protected
76 * by RCU anymore. If the caller is not within an RCU critical section and
77 * does not hold the BQL, it must have other means of protecting the
78 * pointer, such as a reference to the memory region that owns the RAMBlock.
79 */
80 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
81 ram_addr_t *offset);
82 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
83 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
84 void qemu_ram_unset_idstr(RAMBlock *block);
85 const char *qemu_ram_get_idstr(RAMBlock *rb);
86 void *qemu_ram_get_host_addr(RAMBlock *rb);
87 ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
88 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
89 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb);
90 bool qemu_ram_is_shared(RAMBlock *rb);
91 bool qemu_ram_is_noreserve(RAMBlock *rb);
92 bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
93 void qemu_ram_set_uf_zeroable(RAMBlock *rb);
94 bool qemu_ram_is_migratable(RAMBlock *rb);
95 void qemu_ram_set_migratable(RAMBlock *rb);
96 void qemu_ram_unset_migratable(RAMBlock *rb);
97 bool qemu_ram_is_named_file(RAMBlock *rb);
98 int qemu_ram_get_fd(RAMBlock *rb);
99
100 size_t qemu_ram_pagesize(RAMBlock *block);
101 size_t qemu_ram_pagesize_largest(void);
102
103 /**
104 * cpu_address_space_init:
105 * @cpu: CPU to add this address space to
106 * @asidx: integer index of this address space
107 * @prefix: prefix to be used as name of address space
108 * @mr: the root memory region of address space
109 *
110 * Add the specified address space to the CPU's cpu_ases list.
111 * The address space added with @asidx 0 is the one used for the
112 * convenience pointer cpu->as.
113 * The target-specific code which registers ASes is responsible
114 * for defining what semantics address space 0, 1, 2, etc have.
115 *
116 * Before the first call to this function, the caller must set
117 * cpu->num_ases to the total number of address spaces it needs
118 * to support.
119 *
120 * Note that with KVM only one address space is supported.
121 */
122 void cpu_address_space_init(CPUState *cpu, int asidx,
123 const char *prefix, MemoryRegion *mr);
124 /**
125 * cpu_address_space_destroy:
126 * @cpu: CPU for which address space needs to be destroyed
127 * @asidx: integer index of this address space
128 *
129 * Note that with KVM only one address space is supported.
130 */
131 void cpu_address_space_destroy(CPUState *cpu, int asidx);
132
133 void cpu_physical_memory_rw(hwaddr addr, void *buf,
134 hwaddr len, bool is_write);
cpu_physical_memory_read(hwaddr addr,void * buf,hwaddr len)135 static inline void cpu_physical_memory_read(hwaddr addr,
136 void *buf, hwaddr len)
137 {
138 cpu_physical_memory_rw(addr, buf, len, false);
139 }
cpu_physical_memory_write(hwaddr addr,const void * buf,hwaddr len)140 static inline void cpu_physical_memory_write(hwaddr addr,
141 const void *buf, hwaddr len)
142 {
143 cpu_physical_memory_rw(addr, (void *)buf, len, true);
144 }
145 void *cpu_physical_memory_map(hwaddr addr,
146 hwaddr *plen,
147 bool is_write);
148 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
149 bool is_write, hwaddr access_len);
150
151 bool cpu_physical_memory_is_io(hwaddr phys_addr);
152
153 /* Coalesced MMIO regions are areas where write operations can be reordered.
154 * This usually implies that write operations are side-effect free. This allows
155 * batching which can make a major impact on performance when using
156 * virtualization.
157 */
158 void qemu_flush_coalesced_mmio_buffer(void);
159
160 void cpu_flush_icache_range(hwaddr start, hwaddr len);
161
162 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
163
164 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
165 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
166 int ram_block_discard_guest_memfd_range(RAMBlock *rb, uint64_t start,
167 size_t length);
168
169 /* Returns: 0 on success, -1 on error */
170 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
171 void *ptr, size_t len, bool is_write);
172
173 /* vl.c */
174 void list_cpus(void);
175
176 #ifdef CONFIG_TCG
177 #include "qemu/atomic.h"
178
179 /**
180 * cpu_unwind_state_data:
181 * @cpu: the cpu context
182 * @host_pc: the host pc within the translation
183 * @data: output data
184 *
185 * Attempt to load the unwind state for a host pc occurring in
186 * translated code. If @host_pc is not in translated code, the
187 * function returns false; otherwise @data is loaded.
188 * This is the same unwind info as given to restore_state_to_opc.
189 */
190 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
191
192 /**
193 * cpu_restore_state:
194 * @cpu: the cpu context
195 * @host_pc: the host pc within the translation
196 * @return: true if state was restored, false otherwise
197 *
198 * Attempt to restore the state for a fault occurring in translated
199 * code. If @host_pc is not in translated code no state is
200 * restored and the function returns false.
201 */
202 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc);
203
204 /**
205 * cpu_loop_exit_requested:
206 * @cpu: The CPU state to be tested
207 *
208 * Indicate if somebody asked for a return of the CPU to the main loop
209 * (e.g., via cpu_exit() or cpu_interrupt()).
210 *
211 * This is helpful for architectures that support interruptible
212 * instructions. After writing back all state to registers/memory, this
213 * call can be used to check if it makes sense to return to the main loop
214 * or to continue executing the interruptible instruction.
215 */
cpu_loop_exit_requested(CPUState * cpu)216 static inline bool cpu_loop_exit_requested(CPUState *cpu)
217 {
218 return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0;
219 }
220
221 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
222 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
223 #endif /* CONFIG_TCG */
224 G_NORETURN void cpu_loop_exit(CPUState *cpu);
225 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
226
227 /* accel/tcg/cpu-exec.c */
228 int cpu_exec(CPUState *cpu);
229
230 /**
231 * env_archcpu(env)
232 * @env: The architecture environment
233 *
234 * Return the ArchCPU associated with the environment.
235 */
env_archcpu(CPUArchState * env)236 static inline ArchCPU *env_archcpu(CPUArchState *env)
237 {
238 return (void *)env - sizeof(CPUState);
239 }
240
241 /**
242 * env_cpu_const(env)
243 * @env: The architecture environment
244 *
245 * Return the CPUState associated with the environment.
246 */
env_cpu_const(const CPUArchState * env)247 static inline const CPUState *env_cpu_const(const CPUArchState *env)
248 {
249 return (void *)env - sizeof(CPUState);
250 }
251
252 /**
253 * env_cpu(env)
254 * @env: The architecture environment
255 *
256 * Return the CPUState associated with the environment.
257 */
env_cpu(CPUArchState * env)258 static inline CPUState *env_cpu(CPUArchState *env)
259 {
260 return (CPUState *)env_cpu_const(env);
261 }
262
263 #endif /* CPU_COMMON_H */
264