1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
9 #define _ASM_X86_AMD_IOMMU_TYPES_H
10
11 #include <linux/bitfield.h>
12 #include <linux/iommu.h>
13 #include <linux/types.h>
14 #include <linux/mmu_notifier.h>
15 #include <linux/mutex.h>
16 #include <linux/msi.h>
17 #include <linux/list.h>
18 #include <linux/spinlock.h>
19 #include <linux/pci.h>
20 #include <linux/iommufd.h>
21 #include <linux/irqreturn.h>
22 #include <linux/generic_pt/iommu.h>
23
24 #include <uapi/linux/iommufd.h>
25
26 /*
27 * Maximum number of IOMMUs supported
28 */
29 #define MAX_IOMMUS 32
30
31 /*
32 * some size calculation constants
33 */
34 #define DEV_TABLE_ENTRY_SIZE 32
35
36 /* Capability offsets used by the driver */
37 #define MMIO_CAP_HDR_OFFSET 0x00
38 #define MMIO_RANGE_OFFSET 0x0c
39 #define MMIO_MISC_OFFSET 0x10
40
41 /* Masks, shifts and macros to parse the device range capability */
42 #define MMIO_RANGE_LD_MASK 0xff000000
43 #define MMIO_RANGE_FD_MASK 0x00ff0000
44 #define MMIO_RANGE_BUS_MASK 0x0000ff00
45 #define MMIO_RANGE_LD_SHIFT 24
46 #define MMIO_RANGE_FD_SHIFT 16
47 #define MMIO_RANGE_BUS_SHIFT 8
48 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
49 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
50 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
51 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
52
53 /* Flag masks for the AMD IOMMU exclusion range */
54 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
55 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
56
57 /* Used offsets into the MMIO space */
58 #define MMIO_DEV_TABLE_OFFSET 0x0000
59 #define MMIO_CMD_BUF_OFFSET 0x0008
60 #define MMIO_EVT_BUF_OFFSET 0x0010
61 #define MMIO_CONTROL_OFFSET 0x0018
62 #define MMIO_EXCL_BASE_OFFSET 0x0020
63 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
64 #define MMIO_EXT_FEATURES 0x0030
65 #define MMIO_PPR_LOG_OFFSET 0x0038
66 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0
67 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
68 #define MMIO_MSI_ADDR_LO_OFFSET 0x015C
69 #define MMIO_MSI_ADDR_HI_OFFSET 0x0160
70 #define MMIO_MSI_DATA_OFFSET 0x0164
71 #define MMIO_INTCAPXT_EVT_OFFSET 0x0170
72 #define MMIO_INTCAPXT_PPR_OFFSET 0x0178
73 #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180
74 #define MMIO_EXT_FEATURES2 0x01A0
75 #define MMIO_CMD_HEAD_OFFSET 0x2000
76 #define MMIO_CMD_TAIL_OFFSET 0x2008
77 #define MMIO_EVT_HEAD_OFFSET 0x2010
78 #define MMIO_EVT_TAIL_OFFSET 0x2018
79 #define MMIO_STATUS_OFFSET 0x2020
80 #define MMIO_PPR_HEAD_OFFSET 0x2030
81 #define MMIO_PPR_TAIL_OFFSET 0x2038
82 #define MMIO_GA_HEAD_OFFSET 0x2040
83 #define MMIO_GA_TAIL_OFFSET 0x2048
84 #define MMIO_CNTR_CONF_OFFSET 0x4000
85 #define MMIO_CNTR_REG_OFFSET 0x40000
86 #define MMIO_REG_END_OFFSET 0x80000
87
88
89
90 /* Extended Feature Bits */
91 #define FEATURE_PREFETCH BIT_ULL(0)
92 #define FEATURE_PPR BIT_ULL(1)
93 #define FEATURE_X2APIC BIT_ULL(2)
94 #define FEATURE_NX BIT_ULL(3)
95 #define FEATURE_GT BIT_ULL(4)
96 #define FEATURE_IA BIT_ULL(6)
97 #define FEATURE_GA BIT_ULL(7)
98 #define FEATURE_HE BIT_ULL(8)
99 #define FEATURE_PC BIT_ULL(9)
100 #define FEATURE_HATS GENMASK_ULL(11, 10)
101 #define FEATURE_GATS GENMASK_ULL(13, 12)
102 #define FEATURE_GLX GENMASK_ULL(15, 14)
103 #define FEATURE_GAM_VAPIC BIT_ULL(21)
104 #define FEATURE_PASMAX GENMASK_ULL(36, 32)
105 #define FEATURE_GIOSUP BIT_ULL(48)
106 #define FEATURE_HASUP BIT_ULL(49)
107 #define FEATURE_EPHSUP BIT_ULL(50)
108 #define FEATURE_HDSUP BIT_ULL(52)
109 #define FEATURE_SNP BIT_ULL(63)
110
111
112 /* Extended Feature 2 Bits */
113 #define FEATURE_SEVSNPIO_SUP BIT_ULL(1)
114 #define FEATURE_GCR3TRPMODE BIT_ULL(3)
115 #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5)
116 #define FEATURE_SNPAVICSUP_GAM(x) \
117 (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
118 #define FEATURE_HT_RANGE_IGNORE BIT_ULL(11)
119
120 #define FEATURE_NUM_INT_REMAP_SUP GENMASK_ULL(9, 8)
121 #define FEATURE_NUM_INT_REMAP_SUP_2K(x) \
122 (FIELD_GET(FEATURE_NUM_INT_REMAP_SUP, x) == 0x1)
123
124 /* Note:
125 * The current driver only support 16-bit PASID.
126 * Currently, hardware only implement upto 16-bit PASID
127 * even though the spec says it could have upto 20 bits.
128 */
129 #define PASID_MASK 0x0000ffff
130
131 /* MMIO status bits */
132 #define MMIO_STATUS_EVT_OVERFLOW_MASK BIT(0)
133 #define MMIO_STATUS_EVT_INT_MASK BIT(1)
134 #define MMIO_STATUS_COM_WAIT_INT_MASK BIT(2)
135 #define MMIO_STATUS_EVT_RUN_MASK BIT(3)
136 #define MMIO_STATUS_PPR_OVERFLOW_MASK BIT(5)
137 #define MMIO_STATUS_PPR_INT_MASK BIT(6)
138 #define MMIO_STATUS_PPR_RUN_MASK BIT(7)
139 #define MMIO_STATUS_GALOG_RUN_MASK BIT(8)
140 #define MMIO_STATUS_GALOG_OVERFLOW_MASK BIT(9)
141 #define MMIO_STATUS_GALOG_INT_MASK BIT(10)
142
143 /* event logging constants */
144 #define EVENT_ENTRY_SIZE 0x10
145 #define EVENT_TYPE_SHIFT 28
146 #define EVENT_TYPE_MASK 0xf
147 #define EVENT_TYPE_ILL_DEV 0x1
148 #define EVENT_TYPE_IO_FAULT 0x2
149 #define EVENT_TYPE_DEV_TAB_ERR 0x3
150 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
151 #define EVENT_TYPE_ILL_CMD 0x5
152 #define EVENT_TYPE_CMD_HARD_ERR 0x6
153 #define EVENT_TYPE_IOTLB_INV_TO 0x7
154 #define EVENT_TYPE_INV_DEV_REQ 0x8
155 #define EVENT_TYPE_INV_PPR_REQ 0x9
156 #define EVENT_TYPE_RMP_FAULT 0xd
157 #define EVENT_TYPE_RMP_HW_ERR 0xe
158 #define EVENT_DEVID_MASK 0xffff
159 #define EVENT_DEVID_SHIFT 0
160 #define EVENT_DOMID_MASK_LO 0xffff
161 #define EVENT_DOMID_MASK_HI 0xf0000
162 #define EVENT_FLAGS_MASK 0xfff
163 #define EVENT_FLAGS_SHIFT 0x10
164 #define EVENT_FLAG_RW 0x020
165 #define EVENT_FLAG_I 0x008
166
167 /* feature control bits */
168 #define CONTROL_IOMMU_EN 0
169 #define CONTROL_HT_TUN_EN 1
170 #define CONTROL_EVT_LOG_EN 2
171 #define CONTROL_EVT_INT_EN 3
172 #define CONTROL_COMWAIT_EN 4
173 #define CONTROL_INV_TIMEOUT 5
174 #define CONTROL_PASSPW_EN 8
175 #define CONTROL_RESPASSPW_EN 9
176 #define CONTROL_COHERENT_EN 10
177 #define CONTROL_ISOC_EN 11
178 #define CONTROL_CMDBUF_EN 12
179 #define CONTROL_PPRLOG_EN 13
180 #define CONTROL_PPRINT_EN 14
181 #define CONTROL_PPR_EN 15
182 #define CONTROL_GT_EN 16
183 #define CONTROL_GA_EN 17
184 #define CONTROL_GAM_EN 25
185 #define CONTROL_GALOG_EN 28
186 #define CONTROL_GAINT_EN 29
187 #define CONTROL_NUM_INT_REMAP_MODE 43
188 #define CONTROL_NUM_INT_REMAP_MODE_MASK 0x03
189 #define CONTROL_NUM_INT_REMAP_MODE_2K 0x01
190 #define CONTROL_EPH_EN 45
191 #define CONTROL_XT_EN 50
192 #define CONTROL_INTCAPXT_EN 51
193 #define CONTROL_GCR3TRPMODE 58
194 #define CONTROL_IRTCACHEDIS 59
195 #define CONTROL_SNPAVIC_EN 61
196
197 #define CTRL_INV_TO_MASK 7
198 #define CTRL_INV_TO_NONE 0
199 #define CTRL_INV_TO_1MS 1
200 #define CTRL_INV_TO_10MS 2
201 #define CTRL_INV_TO_100MS 3
202 #define CTRL_INV_TO_1S 4
203 #define CTRL_INV_TO_10S 5
204 #define CTRL_INV_TO_100S 6
205
206 /* command specific defines */
207 #define CMD_COMPL_WAIT 0x01
208 #define CMD_INV_DEV_ENTRY 0x02
209 #define CMD_INV_IOMMU_PAGES 0x03
210 #define CMD_INV_IOTLB_PAGES 0x04
211 #define CMD_INV_IRT 0x05
212 #define CMD_COMPLETE_PPR 0x07
213 #define CMD_INV_ALL 0x08
214
215 #define CMD_COMPL_WAIT_STORE_MASK 0x01
216 #define CMD_COMPL_WAIT_INT_MASK 0x02
217 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
218 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
219 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
220
221 #define PPR_STATUS_MASK 0xf
222 #define PPR_STATUS_SHIFT 12
223
224 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
225
226 /* macros and definitions for device table entries */
227 #define DEV_ENTRY_VALID 0x00
228 #define DEV_ENTRY_TRANSLATION 0x01
229 #define DEV_ENTRY_HAD 0x07
230 #define DEV_ENTRY_PPR 0x34
231 #define DEV_ENTRY_IR 0x3d
232 #define DEV_ENTRY_IW 0x3e
233 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
234 #define DEV_ENTRY_EX 0x67
235 #define DEV_ENTRY_SYSMGT1 0x68
236 #define DEV_ENTRY_SYSMGT2 0x69
237 #define DTE_DATA1_SYSMGT_MASK GENMASK_ULL(41, 40)
238
239 #define DEV_ENTRY_IRQ_TBL_EN 0x80
240 #define DEV_ENTRY_INIT_PASS 0xb8
241 #define DEV_ENTRY_EINT_PASS 0xb9
242 #define DEV_ENTRY_NMI_PASS 0xba
243 #define DEV_ENTRY_LINT0_PASS 0xbe
244 #define DEV_ENTRY_LINT1_PASS 0xbf
245 #define DEV_ENTRY_MODE_MASK 0x07
246 #define DEV_ENTRY_MODE_SHIFT 0x09
247
248 #define MAX_DEV_TABLE_ENTRIES 0xffff
249
250 /* constants to configure the command buffer */
251 #define CMD_BUFFER_SIZE 8192
252 #define CMD_BUFFER_UNINITIALIZED 1
253 #define CMD_BUFFER_ENTRIES 512
254 #define MMIO_CMD_SIZE_SHIFT 56
255 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
256 #define MMIO_CMD_HEAD_MASK GENMASK_ULL(18, 4) /* Command buffer head ptr field [18:4] */
257 #define MMIO_CMD_BUFFER_HEAD(x) FIELD_GET(MMIO_CMD_HEAD_MASK, (x))
258 #define MMIO_CMD_TAIL_MASK GENMASK_ULL(18, 4) /* Command buffer tail ptr field [18:4] */
259 #define MMIO_CMD_BUFFER_TAIL(x) FIELD_GET(MMIO_CMD_TAIL_MASK, (x))
260
261 /* constants for event buffer handling */
262 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
263 #define EVT_LEN_MASK (0x9ULL << 56)
264
265 /* Constants for PPR Log handling */
266 #define PPR_LOG_ENTRIES 512
267 #define PPR_LOG_SIZE_SHIFT 56
268 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
269 #define PPR_ENTRY_SIZE 16
270 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
271
272 /* PAGE_SERVICE_REQUEST PPR Log Buffer Entry flags */
273 #define PPR_FLAG_EXEC 0x002 /* Execute permission requested */
274 #define PPR_FLAG_READ 0x004 /* Read permission requested */
275 #define PPR_FLAG_WRITE 0x020 /* Write permission requested */
276 #define PPR_FLAG_US 0x040 /* 1: User, 0: Supervisor */
277 #define PPR_FLAG_RVSD 0x080 /* Reserved bit not zero */
278 #define PPR_FLAG_GN 0x100 /* GVA and PASID is valid */
279
280 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
281 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
282 #define PPR_DEVID(x) ((x) & 0xffffULL)
283 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
284 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
285 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
286 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
287
288 #define PPR_REQ_FAULT 0x01
289
290 /* Constants for GA Log handling */
291 #define GA_LOG_ENTRIES 512
292 #define GA_LOG_SIZE_SHIFT 56
293 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT)
294 #define GA_ENTRY_SIZE 8
295 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
296
297 #define GA_TAG(x) (u32)(x & 0xffffffffULL)
298 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL)
299 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
300
301 #define GA_GUEST_NR 0x1
302
303 #define IOMMU_IN_ADDR_BIT_SIZE 52
304 #define IOMMU_OUT_ADDR_BIT_SIZE 52
305
306 /*
307 * This bitmap is used to advertise the page sizes our hardware support
308 * to the IOMMU core, which will then use this information to split
309 * physically contiguous memory regions it is mapping into page sizes
310 * that we support.
311 *
312 * 512GB Pages are not supported due to a hardware bug
313 * Page sizes >= the 52 bit max physical address of the CPU are not supported.
314 */
315 #define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G)
316
317 /* Special mode where page-sizes are limited to 4 KiB */
318 #define AMD_IOMMU_PGSIZES_4K (PAGE_SIZE)
319
320 /* 4K, 2MB, 1G page sizes are supported */
321 #define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30))
322
323 /* Bit value definition for dte irq remapping fields*/
324 #define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6)
325 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
326 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
327 #define DTE_IRQ_REMAP_ENABLE 1ULL
328
329 #define DTE_INTTAB_ALIGNMENT 128
330 #define DTE_INTTABLEN_MASK (0xfULL << 1)
331 #define DTE_INTTABLEN_VALUE_512 9ULL
332 #define DTE_INTTABLEN_512 (DTE_INTTABLEN_VALUE_512 << 1)
333 #define MAX_IRQS_PER_TABLE_512 BIT(DTE_INTTABLEN_VALUE_512)
334 #define DTE_INTTABLEN_VALUE_2K 11ULL
335 #define DTE_INTTABLEN_2K (DTE_INTTABLEN_VALUE_2K << 1)
336 #define MAX_IRQS_PER_TABLE_2K BIT(DTE_INTTABLEN_VALUE_2K)
337
338 #define PAGE_MODE_NONE 0x00
339 #define PAGE_MODE_1_LEVEL 0x01
340 #define PAGE_MODE_2_LEVEL 0x02
341 #define PAGE_MODE_3_LEVEL 0x03
342 #define PAGE_MODE_4_LEVEL 0x04
343 #define PAGE_MODE_5_LEVEL 0x05
344 #define PAGE_MODE_6_LEVEL 0x06
345 #define PAGE_MODE_7_LEVEL 0x07
346
347 #define GUEST_PGTABLE_4_LEVEL 0x00
348 #define GUEST_PGTABLE_5_LEVEL 0x01
349
350 #define PM_ADDR_MASK 0x000ffffffffff000ULL
351
352 /*
353 * Bit value definition for DTE fields
354 */
355 #define DTE_FLAG_V BIT_ULL(0)
356 #define DTE_FLAG_TV BIT_ULL(1)
357 #define DTE_FLAG_HAD (3ULL << 7)
358 #define DTE_MODE_MASK GENMASK_ULL(11, 9)
359 #define DTE_HOST_TRP GENMASK_ULL(51, 12)
360 #define DTE_FLAG_PPR BIT_ULL(52)
361 #define DTE_FLAG_GIOV BIT_ULL(54)
362 #define DTE_FLAG_GV BIT_ULL(55)
363 #define DTE_GLX GENMASK_ULL(57, 56)
364 #define DTE_FLAG_IR BIT_ULL(61)
365 #define DTE_FLAG_IW BIT_ULL(62)
366
367 #define DTE_FLAG_IOTLB BIT_ULL(32)
368 #define DTE_FLAG_MASK (0x3ffULL << 32)
369 #define DTE_DOMID_MASK GENMASK_ULL(15, 0)
370
371 #define DTE_GCR3_14_12 GENMASK_ULL(60, 58)
372 #define DTE_GCR3_30_15 GENMASK_ULL(31, 16)
373 #define DTE_GCR3_51_31 GENMASK_ULL(63, 43)
374
375 #define DTE_GPT_LEVEL_SHIFT 54
376 #define DTE_GPT_LEVEL_MASK GENMASK_ULL(55, 54)
377
378 #define GCR3_VALID 0x01ULL
379
380 /* DTE[128:179] | DTE[184:191] */
381 #define DTE_DATA2_INTR_MASK ~GENMASK_ULL(55, 52)
382
383 #define IOMMU_PROT_MASK 0x03
384 #define IOMMU_PROT_IR 0x01
385 #define IOMMU_PROT_IW 0x02
386
387 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2)
388
389 /* IOMMU capabilities */
390 #define IOMMU_CAP_IOTLB 24
391 #define IOMMU_CAP_NPCACHE 26
392 #define IOMMU_CAP_EFR 27
393
394 /* IOMMU IVINFO */
395 #define IOMMU_IVINFO_OFFSET 36
396 #define IOMMU_IVINFO_EFRSUP BIT(0)
397 #define IOMMU_IVINFO_DMA_REMAP BIT(1)
398
399 /* IOMMU Feature Reporting Field (for IVHD type 10h */
400 #define IOMMU_FEAT_GASUP_SHIFT 6
401
402 /* IOMMU HATDIS for IVHD type 11h and 40h */
403 #define IOMMU_IVHD_ATTR_HATDIS_SHIFT 0
404
405 /* IOMMU Extended Feature Register (EFR) */
406 #define IOMMU_EFR_XTSUP_SHIFT 2
407 #define IOMMU_EFR_GASUP_SHIFT 7
408 #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46
409
410 #define MAX_DOMAIN_ID 65536
411
412 /* Timeout stuff */
413 #define LOOP_TIMEOUT 100000
414 #define MMIO_STATUS_TIMEOUT 2000000
415
416 extern bool amd_iommu_dump;
417 #define DUMP_printk(format, arg...) \
418 do { \
419 if (amd_iommu_dump) \
420 pr_info(format, ## arg); \
421 } while(0);
422
423 /* global flag if IOMMUs cache non-present entries */
424 extern bool amd_iommu_np_cache;
425 /* Only true if all IOMMUs support device IOTLBs */
426 extern bool amd_iommu_iotlb_sup;
427
428 struct irq_remap_table {
429 raw_spinlock_t lock;
430 unsigned min_index;
431 u32 *table;
432 };
433
434 /* Interrupt remapping feature used? */
435 extern bool amd_iommu_irq_remap;
436
437 extern const struct iommu_ops amd_iommu_ops;
438
439 /* IVRS indicates that pre-boot remapping was enabled */
440 extern bool amdr_ivrs_remap_support;
441
442 #define PCI_SBDF_TO_SEGID(sbdf) (((sbdf) >> 16) & 0xffff)
443 #define PCI_SBDF_TO_DEVID(sbdf) ((sbdf) & 0xffff)
444 #define PCI_SEG_DEVID_TO_SBDF(seg, devid) ((((u32)(seg) & 0xffff) << 16) | \
445 ((devid) & 0xffff))
446
447 /* Make iterating over all pci segment easier */
448 #define for_each_pci_segment(pci_seg) \
449 list_for_each_entry((pci_seg), &amd_iommu_pci_seg_list, list)
450 #define for_each_pci_segment_safe(pci_seg, next) \
451 list_for_each_entry_safe((pci_seg), (next), &amd_iommu_pci_seg_list, list)
452 /*
453 * Make iterating over all IOMMUs easier
454 */
455 #define for_each_iommu(iommu) \
456 list_for_each_entry((iommu), &amd_iommu_list, list)
457 #define for_each_iommu_safe(iommu, next) \
458 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
459 /* Making iterating over protection_domain->dev_data_list easier */
460 #define for_each_pdom_dev_data(pdom_dev_data, pdom) \
461 list_for_each_entry(pdom_dev_data, &pdom->dev_data_list, list)
462 #define for_each_pdom_dev_data_safe(pdom_dev_data, next, pdom) \
463 list_for_each_entry_safe((pdom_dev_data), (next), &pdom->dev_data_list, list)
464
465 #define for_each_ivhd_dte_flags(entry) \
466 list_for_each_entry((entry), &amd_ivhd_dev_flags_list, list)
467
468 struct amd_iommu;
469 struct iommu_domain;
470 struct irq_domain;
471 struct amd_irte_ops;
472
473 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0)
474
475 struct gcr3_tbl_info {
476 u64 *gcr3_tbl; /* Guest CR3 table */
477 int glx; /* Number of levels for GCR3 table */
478 u32 pasid_cnt; /* Track attached PASIDs */
479 u16 domid; /* Per device domain ID */
480 };
481
482 enum protection_domain_mode {
483 PD_MODE_NONE,
484 PD_MODE_V1,
485 PD_MODE_V2,
486 };
487
488 /* Track dev_data/PASID list for the protection domain */
489 struct pdom_dev_data {
490 /* Points to attached device data */
491 struct iommu_dev_data *dev_data;
492 /* PASID attached to the protection domain */
493 ioasid_t pasid;
494 /* For protection_domain->dev_data_list */
495 struct list_head list;
496 };
497
498 /* Keeps track of the IOMMUs attached to protection domain */
499 struct pdom_iommu_info {
500 struct amd_iommu *iommu; /* IOMMUs attach to protection domain */
501 u32 refcnt; /* Count of attached dev/pasid per domain/IOMMU */
502 };
503
504 struct amd_iommu_viommu {
505 struct iommufd_viommu core;
506 struct protection_domain *parent; /* nest parent domain for this viommu */
507 struct list_head pdom_list; /* For protection_domain->viommu_list */
508
509 /*
510 * Per-vIOMMU guest domain ID to host domain ID mapping.
511 * Indexed by guest domain ID.
512 */
513 struct xarray gdomid_array;
514 };
515
516 /*
517 * Contains guest domain ID mapping info,
518 * which is stored in the struct xarray gdomid_array.
519 */
520 struct guest_domain_mapping_info {
521 refcount_t users;
522 u32 hdom_id; /* Host domain ID */
523 };
524
525 /*
526 * Nested domain is specifically used for nested translation
527 */
528 struct nested_domain {
529 struct iommu_domain domain; /* generic domain handle used by iommu core code */
530 u16 gdom_id; /* domain ID from gDTE */
531 struct guest_domain_mapping_info *gdom_info;
532 struct iommu_hwpt_amd_guest gdte; /* Guest vIOMMU DTE */
533 struct amd_iommu_viommu *viommu; /* AMD hw-viommu this nested domain belong to */
534 };
535
536 /*
537 * This structure contains generic data for IOMMU protection domains
538 * independent of their use.
539 */
540 struct protection_domain {
541 union {
542 struct iommu_domain domain;
543 struct pt_iommu iommu;
544 struct pt_iommu_amdv1 amdv1;
545 struct pt_iommu_x86_64 amdv2;
546 };
547 struct list_head dev_list; /* List of all devices in this domain */
548 spinlock_t lock; /* mostly used to lock the page table*/
549 u16 id; /* the domain id written to the device table */
550 enum protection_domain_mode pd_mode; /* Track page table type */
551 bool dirty_tracking; /* dirty tracking is enabled in the domain */
552 struct xarray iommu_array; /* per-IOMMU reference count */
553
554 struct mmu_notifier mn; /* mmu notifier for the SVA domain */
555 struct list_head dev_data_list; /* List of pdom_dev_data */
556
557 /*
558 * Store reference to list of vIOMMUs, which use this protection domain.
559 * This will be used to look up host domain ID when flushing this domain.
560 */
561 struct list_head viommu_list;
562 };
563 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, iommu, domain);
564 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv1.iommu, domain);
565 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv2.iommu, domain);
566
567 /*
568 * This structure contains information about one PCI segment in the system.
569 */
570 struct amd_iommu_pci_seg {
571 /* List with all PCI segments in the system */
572 struct list_head list;
573
574 /* List of all available dev_data structures */
575 struct llist_head dev_data_list;
576
577 /* PCI segment number */
578 u16 id;
579
580 /* Largest PCI device id we expect translation requests for */
581 u16 last_bdf;
582
583 /* Size of the device table */
584 u32 dev_table_size;
585
586 /*
587 * device table virtual address
588 *
589 * Pointer to the per PCI segment device table.
590 * It is indexed by the PCI device id or the HT unit id and contains
591 * information about the domain the device belongs to as well as the
592 * page table root pointer.
593 */
594 struct dev_table_entry *dev_table;
595
596 /*
597 * The rlookup iommu table is used to find the IOMMU which is
598 * responsible for a specific device. It is indexed by the PCI
599 * device id.
600 */
601 struct amd_iommu **rlookup_table;
602
603 /*
604 * This table is used to find the irq remapping table for a given
605 * device id quickly.
606 */
607 struct irq_remap_table **irq_lookup_table;
608
609 /*
610 * Pointer to a device table which the content of old device table
611 * will be copied to. It's only be used in kdump kernel.
612 */
613 struct dev_table_entry *old_dev_tbl_cpy;
614
615 /*
616 * The alias table is a driver specific data structure which contains the
617 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
618 * More than one device can share the same requestor id.
619 */
620 u16 *alias_table;
621
622 /*
623 * A list of required unity mappings we find in ACPI. It is not locked
624 * because as runtime it is only read. It is created at ACPI table
625 * parsing time.
626 */
627 struct list_head unity_map;
628 };
629
630 /*
631 * Structure where we save information about one hardware AMD IOMMU in the
632 * system.
633 */
634 struct amd_iommu {
635 struct list_head list;
636
637 /* Index within the IOMMU array */
638 int index;
639
640 /* locks the accesses to the hardware */
641 raw_spinlock_t lock;
642
643 /* Pointer to PCI device of this IOMMU */
644 struct pci_dev *dev;
645
646 /* Cache pdev to root device for resume quirks */
647 struct pci_dev *root_pdev;
648
649 /* physical address of MMIO space */
650 u64 mmio_phys;
651
652 /* physical end address of MMIO space */
653 u64 mmio_phys_end;
654
655 /* virtual address of MMIO space */
656 u8 __iomem *mmio_base;
657
658 /* capabilities of that IOMMU read from ACPI */
659 u32 cap;
660
661 /* flags read from acpi table */
662 u8 acpi_flags;
663
664 /* Extended features */
665 u64 features;
666
667 /* Extended features 2 */
668 u64 features2;
669
670 /* PCI device id of the IOMMU device */
671 u16 devid;
672
673 /*
674 * Capability pointer. There could be more than one IOMMU per PCI
675 * device function if there are more than one AMD IOMMU capability
676 * pointers.
677 */
678 u16 cap_ptr;
679
680 /* pci domain of this IOMMU */
681 struct amd_iommu_pci_seg *pci_seg;
682
683 /* start of exclusion range of that IOMMU */
684 u64 exclusion_start;
685 /* length of exclusion range of that IOMMU */
686 u64 exclusion_length;
687
688 /* command buffer virtual address */
689 u8 *cmd_buf;
690 u32 cmd_buf_head;
691 u32 cmd_buf_tail;
692
693 /* event buffer virtual address */
694 u8 *evt_buf;
695
696 /* Name for event log interrupt */
697 unsigned char evt_irq_name[16];
698
699 /* Base of the PPR log, if present */
700 u8 *ppr_log;
701
702 /* Name for PPR log interrupt */
703 unsigned char ppr_irq_name[16];
704
705 /* Base of the GA log, if present */
706 u8 *ga_log;
707
708 /* Name for GA log interrupt */
709 unsigned char ga_irq_name[16];
710
711 /* Tail of the GA log, if present */
712 u8 *ga_log_tail;
713
714 /* true if interrupts for this IOMMU are already enabled */
715 bool int_enabled;
716
717 /* if one, we need to send a completion wait command */
718 bool need_sync;
719
720 /* true if disable irte caching */
721 bool irtcachedis_enabled;
722
723 /* Handle for IOMMU core code */
724 struct iommu_device iommu;
725
726 /*
727 * We can't rely on the BIOS to restore all values on reinit, so we
728 * need to stash them
729 */
730
731 /* The iommu BAR */
732 u32 stored_addr_lo;
733 u32 stored_addr_hi;
734
735 /*
736 * Each iommu has 6 l1s, each of which is documented as having 0x12
737 * registers
738 */
739 u32 stored_l1[6][0x12];
740
741 /* The l2 indirect registers */
742 u32 stored_l2[0x83];
743
744 /* The maximum PC banks and counters/bank (PCSup=1) */
745 u8 max_banks;
746 u8 max_counters;
747 #ifdef CONFIG_IRQ_REMAP
748 struct irq_domain *ir_domain;
749
750 struct amd_irte_ops *irte_ops;
751 #endif
752
753 u32 flags;
754 volatile u64 *cmd_sem;
755 u64 cmd_sem_val;
756 /*
757 * Track physical address to directly use it in build_completion_wait()
758 * and avoid adding any special checks and handling for kdump.
759 */
760 u64 cmd_sem_paddr;
761
762 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
763 /* DebugFS Info */
764 struct dentry *debugfs;
765 int dbg_mmio_offset;
766 int dbg_cap_offset;
767 #endif
768
769 /* IOPF support */
770 struct iopf_queue *iopf_queue;
771 unsigned char iopfq_name[32];
772 };
773
dev_to_amd_iommu(struct device * dev)774 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
775 {
776 struct iommu_device *iommu = dev_to_iommu_device(dev);
777
778 return container_of(iommu, struct amd_iommu, iommu);
779 }
780
781 #define ACPIHID_UID_LEN 256
782 #define ACPIHID_HID_LEN 9
783
784 struct acpihid_map_entry {
785 struct list_head list;
786 u8 uid[ACPIHID_UID_LEN];
787 u8 hid[ACPIHID_HID_LEN];
788 u32 devid;
789 u32 root_devid;
790 bool cmd_line;
791 struct iommu_group *group;
792 };
793
794 struct devid_map {
795 struct list_head list;
796 u8 id;
797 u32 devid;
798 bool cmd_line;
799 };
800
801 #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
802 #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
803 #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
804 /* Device may request execution on memory pages */
805 #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8
806 /* Device may request super-user privileges */
807 #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10
808
809 /*
810 * This struct contains device specific data for the IOMMU
811 */
812 struct iommu_dev_data {
813 /*Protect against attach/detach races */
814 struct mutex mutex;
815 spinlock_t dte_lock; /* DTE lock for 256-bit access */
816
817 struct list_head list; /* For domain->dev_list */
818 struct llist_node dev_data_list; /* For global dev_data_list */
819 struct protection_domain *domain; /* Domain the device is bound to */
820 struct gcr3_tbl_info gcr3_info; /* Per-device GCR3 table */
821 struct device *dev;
822 u16 devid; /* PCI Device ID */
823
824 unsigned int max_irqs; /* Maximum IRQs supported by device */
825 u32 max_pasids; /* Max supported PASIDs */
826 u32 flags; /* Holds AMD_IOMMU_DEVICE_FLAG_<*> */
827 int ats_qdep;
828 u8 ats_enabled :1; /* ATS state */
829 u8 pri_enabled :1; /* PRI state */
830 u8 pasid_enabled:1; /* PASID state */
831 u8 pri_tlp :1; /* PASID TLB required for
832 PPR completions */
833 u8 ppr :1; /* Enable device PPR support */
834 bool use_vapic; /* Enable device to use vapic mode */
835 bool defer_attach;
836
837 struct ratelimit_state rs; /* Ratelimit IOPF messages */
838 };
839
840 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
841 extern struct list_head ioapic_map;
842 extern struct list_head hpet_map;
843 extern struct list_head acpihid_map;
844
845 /*
846 * List with all PCI segments in the system. This list is not locked because
847 * it is only written at driver initialization time
848 */
849 extern struct list_head amd_iommu_pci_seg_list;
850
851 /*
852 * List with all IOMMUs in the system. This list is not locked because it is
853 * only written and read at driver initialization or suspend time
854 */
855 extern struct list_head amd_iommu_list;
856
857 /*
858 * Structure defining one entry in the device table
859 */
860 struct dev_table_entry {
861 union {
862 u64 data[4];
863 u128 data128[2];
864 };
865 };
866
867 /*
868 * Structure defining one entry in the command buffer
869 */
870 struct iommu_cmd {
871 u32 data[4];
872 };
873
874 /*
875 * Structure to sture persistent DTE flags from IVHD
876 */
877 struct ivhd_dte_flags {
878 struct list_head list;
879 u16 segid;
880 u16 devid_first;
881 u16 devid_last;
882 struct dev_table_entry dte;
883 };
884
885 /*
886 * One entry for unity mappings parsed out of the ACPI table.
887 */
888 struct unity_map_entry {
889 struct list_head list;
890
891 /* starting device id this entry is used for (including) */
892 u16 devid_start;
893 /* end device id this entry is used for (including) */
894 u16 devid_end;
895
896 /* start address to unity map (including) */
897 u64 address_start;
898 /* end address to unity map (including) */
899 u64 address_end;
900
901 /* required protection */
902 int prot;
903 };
904
905 /*
906 * Data structures for device handling
907 */
908
909 extern bool amd_iommu_force_isolation;
910
911 /* Max levels of glxval supported */
912 extern int amd_iommu_max_glx_val;
913
914 /* IDA to track protection domain IDs */
915 extern struct ida pdom_ids;
916
917 /* Global EFR and EFR2 registers */
918 extern u64 amd_iommu_efr;
919 extern u64 amd_iommu_efr2;
920
get_ioapic_devid(int id)921 static inline int get_ioapic_devid(int id)
922 {
923 struct devid_map *entry;
924
925 list_for_each_entry(entry, &ioapic_map, list) {
926 if (entry->id == id)
927 return entry->devid;
928 }
929
930 return -EINVAL;
931 }
932
get_hpet_devid(int id)933 static inline int get_hpet_devid(int id)
934 {
935 struct devid_map *entry;
936
937 list_for_each_entry(entry, &hpet_map, list) {
938 if (entry->id == id)
939 return entry->devid;
940 }
941
942 return -EINVAL;
943 }
944
945 enum amd_iommu_intr_mode_type {
946 AMD_IOMMU_GUEST_IR_LEGACY,
947
948 /* This mode is not visible to users. It is used when
949 * we cannot fully enable vAPIC and fallback to only support
950 * legacy interrupt remapping via 128-bit IRTE.
951 */
952 AMD_IOMMU_GUEST_IR_LEGACY_GA,
953 AMD_IOMMU_GUEST_IR_VAPIC,
954 };
955
956 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
957 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
958
959 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
960
961 union irte {
962 u32 val;
963 struct {
964 u32 valid : 1,
965 no_fault : 1,
966 int_type : 3,
967 rq_eoi : 1,
968 dm : 1,
969 rsvd_1 : 1,
970 destination : 8,
971 vector : 8,
972 rsvd_2 : 8;
973 } fields;
974 };
975
976 #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff)
977 #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff)
978
979 union irte_ga_lo {
980 u64 val;
981
982 /* For int remapping */
983 struct {
984 u64 valid : 1,
985 no_fault : 1,
986 /* ------ */
987 int_type : 3,
988 rq_eoi : 1,
989 dm : 1,
990 /* ------ */
991 guest_mode : 1,
992 destination : 24,
993 ga_tag : 32;
994 } fields_remap;
995
996 /* For guest vAPIC */
997 struct {
998 u64 valid : 1,
999 no_fault : 1,
1000 /* ------ */
1001 ga_log_intr : 1,
1002 rsvd1 : 3,
1003 is_run : 1,
1004 /* ------ */
1005 guest_mode : 1,
1006 destination : 24,
1007 ga_tag : 32;
1008 } fields_vapic;
1009 };
1010
1011 union irte_ga_hi {
1012 u64 val;
1013 struct {
1014 u64 vector : 8,
1015 rsvd_1 : 4,
1016 ga_root_ptr : 40,
1017 rsvd_2 : 4,
1018 destination : 8;
1019 } fields;
1020 };
1021
1022 struct irte_ga {
1023 union {
1024 struct {
1025 union irte_ga_lo lo;
1026 union irte_ga_hi hi;
1027 };
1028 u128 irte;
1029 };
1030 };
1031
1032 struct irq_2_irte {
1033 u16 devid; /* Device ID for IRTE table */
1034 u16 index; /* Index into IRTE table*/
1035 };
1036
1037 struct amd_ir_data {
1038 struct amd_iommu *iommu;
1039 struct irq_2_irte irq_2_irte;
1040 struct msi_msg msi_entry;
1041 void *entry; /* Pointer to union irte or struct irte_ga */
1042
1043 /**
1044 * Store information for activate/de-activate
1045 * Guest virtual APIC mode during runtime.
1046 */
1047 struct irq_cfg *cfg;
1048 int ga_vector;
1049 u64 ga_root_ptr;
1050 u32 ga_tag;
1051 };
1052
1053 struct amd_irte_ops {
1054 void (*prepare)(void *, u32, bool, u8, u32, int);
1055 void (*activate)(struct amd_iommu *iommu, void *, u16, u16);
1056 void (*deactivate)(struct amd_iommu *iommu, void *, u16, u16);
1057 void (*set_affinity)(struct amd_iommu *iommu, void *, u16, u16, u8, u32);
1058 void *(*get)(struct irq_remap_table *, int);
1059 void (*set_allocated)(struct irq_remap_table *, int);
1060 bool (*is_allocated)(struct irq_remap_table *, int);
1061 void (*clear_allocated)(struct irq_remap_table *, int);
1062 };
1063
1064 #ifdef CONFIG_IRQ_REMAP
1065 extern struct amd_irte_ops irte_32_ops;
1066 extern struct amd_irte_ops irte_128_ops;
1067 #endif
1068
1069 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
1070