1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * Copyright (c) 2012 Linaro Ltd 8 * http://www.linaro.org 9 * 10 * Author: Thomas Abraham <thomas.ab@samsung.com> 11 */ 12 13 #ifndef __PINCTRL_SAMSUNG_H 14 #define __PINCTRL_SAMSUNG_H 15 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/machine.h> 21 22 #include <linux/gpio/driver.h> 23 24 /** 25 * enum pincfg_type - possible pin configuration types supported. 26 * @PINCFG_TYPE_FUNC: Function configuration. 27 * @PINCFG_TYPE_DAT: Pin value configuration. 28 * @PINCFG_TYPE_PUD: Pull up/down configuration. 29 * @PINCFG_TYPE_DRV: Drive strength configuration. 30 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode. 31 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode. 32 */ 33 enum pincfg_type { 34 PINCFG_TYPE_FUNC, 35 PINCFG_TYPE_DAT, 36 PINCFG_TYPE_PUD, 37 PINCFG_TYPE_DRV, 38 PINCFG_TYPE_CON_PDN, 39 PINCFG_TYPE_PUD_PDN, 40 41 PINCFG_TYPE_NUM 42 }; 43 44 /* 45 * pin configuration (pull up/down and drive strength) type and its value are 46 * packed together into a 16-bits. The upper 8-bits represent the configuration 47 * type and the lower 8-bits hold the value of the configuration type. 48 */ 49 #define PINCFG_TYPE_MASK 0xFF 50 #define PINCFG_VALUE_SHIFT 8 51 #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) 52 #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) 53 #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) 54 #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ 55 PINCFG_VALUE_SHIFT) 56 /* 57 * Values for the pin CON register, choosing pin function. 58 * The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210, 59 * Exynos ARMv7, Exynos ARMv8, Tesla FSD. 60 */ 61 #define PIN_CON_FUNC_INPUT 0x0 62 #define PIN_CON_FUNC_OUTPUT 0x1 63 64 /* Values for the pin PUD register */ 65 #define EXYNOS_PIN_PUD_PULL_DISABLE 0x0 66 #define EXYNOS_PIN_PID_PULL_DOWN 0x1 67 #define EXYNOS_PIN_PID_PULL_UP 0x3 68 69 /* 70 * enum pud_index - Possible index values to access the pud_val array. 71 * @PUD_PULL_DISABLE: Index for the value of pud disable 72 * @PUD_PULL_DOWN: Index for the value of pull down enable 73 * @PUD_PULL_UP: Index for the value of pull up enable 74 * @PUD_MAX: Maximum value of the index 75 */ 76 enum pud_index { 77 PUD_PULL_DISABLE, 78 PUD_PULL_DOWN, 79 PUD_PULL_UP, 80 PUD_MAX, 81 }; 82 83 /** 84 * enum eint_type - possible external interrupt types. 85 * @EINT_TYPE_NONE: bank does not support external interrupts 86 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts 87 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts 88 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts 89 * 90 * Samsung GPIO controller groups all the available pins into banks. The pins 91 * in a pin bank can support external gpio interrupts or external wakeup 92 * interrupts or no interrupts at all. From a software perspective, the only 93 * difference between external gpio and external wakeup interrupts is that 94 * the wakeup interrupts can additionally wakeup the system if it is in 95 * suspended state. 96 */ 97 enum eint_type { 98 EINT_TYPE_NONE, 99 EINT_TYPE_GPIO, 100 EINT_TYPE_WKUP, 101 EINT_TYPE_WKUP_MUX, 102 }; 103 104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */ 105 #define PIN_NAME_LENGTH 10 106 107 #define PIN_GROUP(n, p, f) \ 108 { \ 109 .name = n, \ 110 .pins = p, \ 111 .num_pins = ARRAY_SIZE(p), \ 112 .func = f \ 113 } 114 115 #define PMX_FUNC(n, g) \ 116 { \ 117 .name = n, \ 118 .groups = g, \ 119 .num_groups = ARRAY_SIZE(g), \ 120 } 121 122 struct samsung_pinctrl_drv_data; 123 124 /** 125 * struct samsung_pin_bank_type: pin bank type description 126 * @fld_width: widths of configuration bitfields (0 if unavailable) 127 * @reg_offset: offsets of configuration registers (don't care of width is 0) 128 */ 129 struct samsung_pin_bank_type { 130 u8 fld_width[PINCFG_TYPE_NUM]; 131 u8 reg_offset[PINCFG_TYPE_NUM]; 132 }; 133 134 /** 135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data). 136 * @type: type of the bank (register offsets and bitfield widths) 137 * @pctl_offset: starting offset of the pin-bank registers. 138 * @pctl_res_idx: index of base address for pin-bank registers. 139 * @nr_pins: number of pins included in this bank. 140 * @eint_func: function to set in CON register to configure pin as EINT. 141 * @eint_type: type of the external interrupt supported by the bank. 142 * @eint_mask: bit mask of pins which support EINT function. 143 * @eint_offset: SoC-specific EINT register or interrupt offset of bank. 144 * @eint_num: total number of eint pins. 145 * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank. 146 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. 147 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. 148 * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset. 149 * @name: name to be prefixed for each pin in this pin bank. 150 */ 151 struct samsung_pin_bank_data { 152 const struct samsung_pin_bank_type *type; 153 u32 pctl_offset; 154 u8 pctl_res_idx; 155 u8 nr_pins; 156 u8 eint_func; 157 enum eint_type eint_type; 158 u32 eint_mask; 159 u32 eint_offset; 160 u32 eint_num; 161 u32 eint_con_offset; 162 u32 eint_mask_offset; 163 u32 eint_pend_offset; 164 u32 eint_fltcon_offset; 165 const char *name; 166 }; 167 168 /** 169 * struct samsung_pin_bank: represent a controller pin-bank. 170 * @type: type of the bank (register offsets and bitfield widths) 171 * @pctl_base: base address of the pin-bank registers 172 * @pctl_offset: starting offset of the pin-bank registers. 173 * @nr_pins: number of pins included in this bank. 174 * @eint_base: base address of the pin-bank EINT registers. 175 * @eint_func: function to set in CON register to configure pin as EINT. 176 * @eint_type: type of the external interrupt supported by the bank. 177 * @eint_mask: bit mask of pins which support EINT function. 178 * @eint_offset: SoC-specific EINT register or interrupt offset of bank. 179 * @eint_num: total number of eint pins. 180 * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank. 181 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. 182 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. 183 * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset. 184 * @name: name to be prefixed for each pin in this pin bank. 185 * @id: id of the bank, propagated to the pin range. 186 * @pin_base: starting pin number of the bank. 187 * @soc_priv: per-bank private data for SoC-specific code. 188 * @of_node: OF node of the bank. 189 * @drvdata: link to controller driver data 190 * @irq_domain: IRQ domain of the bank. 191 * @gpio_chip: GPIO chip of the bank. 192 * @grange: linux gpio pin range supported by this bank. 193 * @irq_chip: link to irq chip for external gpio and wakeup interrupts. 194 * @slock: spinlock protecting bank registers 195 * @pm_save: saved register values during suspend 196 */ 197 struct samsung_pin_bank { 198 const struct samsung_pin_bank_type *type; 199 void __iomem *pctl_base; 200 u32 pctl_offset; 201 u8 nr_pins; 202 void __iomem *eint_base; 203 u8 eint_func; 204 enum eint_type eint_type; 205 u32 eint_mask; 206 u32 eint_offset; 207 u32 eint_num; 208 u32 eint_con_offset; 209 u32 eint_mask_offset; 210 u32 eint_pend_offset; 211 u32 eint_fltcon_offset; 212 const char *name; 213 u32 id; 214 215 u32 pin_base; 216 void *soc_priv; 217 struct fwnode_handle *fwnode; 218 struct samsung_pinctrl_drv_data *drvdata; 219 struct irq_domain *irq_domain; 220 struct gpio_chip gpio_chip; 221 struct pinctrl_gpio_range grange; 222 struct exynos_irq_chip *irq_chip; 223 raw_spinlock_t slock; 224 225 u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ 226 }; 227 228 /** 229 * struct samsung_retention_data: runtime pin-bank retention control data. 230 * @regs: array of PMU registers to control pad retention. 231 * @nr_regs: number of registers in @regs array. 232 * @value: value to store to registers to turn off retention. 233 * @refcnt: atomic counter if retention control affects more than one bank. 234 * @priv: retention control code private data 235 * @enable: platform specific callback to enter retention mode. 236 * @disable: platform specific callback to exit retention mode. 237 **/ 238 struct samsung_retention_ctrl { 239 const u32 *regs; 240 int nr_regs; 241 u32 value; 242 atomic_t *refcnt; 243 void *priv; 244 void (*enable)(struct samsung_pinctrl_drv_data *); 245 void (*disable)(struct samsung_pinctrl_drv_data *); 246 }; 247 248 /** 249 * struct samsung_retention_data: represent a pin-bank retention control data. 250 * @regs: array of PMU registers to control pad retention. 251 * @nr_regs: number of registers in @regs array. 252 * @value: value to store to registers to turn off retention. 253 * @refcnt: atomic counter if retention control affects more than one bank. 254 * @init: platform specific callback to initialize retention control. 255 **/ 256 struct samsung_retention_data { 257 const u32 *regs; 258 int nr_regs; 259 u32 value; 260 atomic_t *refcnt; 261 struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *, 262 const struct samsung_retention_data *); 263 }; 264 265 /** 266 * struct samsung_pin_ctrl: represent a pin controller. 267 * @pin_banks: list of pin banks included in this controller. 268 * @nr_banks: number of pin banks. 269 * @nr_ext_resources: number of the extra base address for pin banks. 270 * @retention_data: configuration data for retention control. 271 * @eint_gpio_init: platform specific callback to setup the external gpio 272 * interrupts for the controller. 273 * @eint_wkup_init: platform specific callback to setup the external wakeup 274 * interrupts for the controller. 275 * @suspend: platform specific suspend callback, executed during pin controller 276 * device suspend, see samsung_pinctrl_suspend() 277 * @resume: platform specific resume callback, executed during pin controller 278 * device suspend, see samsung_pinctrl_resume() 279 * 280 * External wakeup interrupts must define at least eint_wkup_init, 281 * retention_data and suspend in order for proper suspend/resume to work. 282 */ 283 struct samsung_pin_ctrl { 284 const struct samsung_pin_bank_data *pin_banks; 285 unsigned int nr_banks; 286 unsigned int nr_ext_resources; 287 const struct samsung_retention_data *retention_data; 288 289 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); 290 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); 291 void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata); 292 void (*suspend)(struct samsung_pin_bank *bank); 293 void (*resume)(struct samsung_pin_bank *bank); 294 }; 295 296 /** 297 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. 298 * @node: global list node 299 * @virt_base: register base address of the controller; this will be equal 300 * to each bank samsung_pin_bank->pctl_base and used on legacy 301 * platforms (like S3C24XX or S3C64XX) which has to access the base 302 * through samsung_pinctrl_drv_data, not samsung_pin_bank). 303 * @dev: device instance representing the controller. 304 * @irq: interrpt number used by the controller to notify gpio interrupts. 305 * @pclk: optional bus clock if required for accessing registers 306 * @ctrl: pin controller instance managed by the driver. 307 * @pctl: pin controller descriptor registered with the pinctrl subsystem. 308 * @pctl_dev: cookie representing pinctrl device instance. 309 * @pin_groups: list of pin groups available to the driver. 310 * @nr_groups: number of such pin groups. 311 * @pmx_functions: list of pin functions available to the driver. 312 * @nr_function: number of such pin functions. 313 * @nr_pins: number of pins supported by the controller. 314 * @retention_ctrl: retention control runtime data. 315 * @suspend: platform specific suspend callback, executed during pin controller 316 * device suspend, see samsung_pinctrl_suspend() 317 * @resume: platform specific resume callback, executed during pin controller 318 * device suspend, see samsung_pinctrl_resume() 319 */ 320 struct samsung_pinctrl_drv_data { 321 struct list_head node; 322 void __iomem *virt_base; 323 struct device *dev; 324 int irq; 325 struct clk *pclk; 326 327 struct pinctrl_desc pctl; 328 struct pinctrl_dev *pctl_dev; 329 330 const struct samsung_pin_group *pin_groups; 331 unsigned int nr_groups; 332 const struct samsung_pmx_func *pmx_functions; 333 unsigned int nr_functions; 334 335 struct samsung_pin_bank *pin_banks; 336 unsigned int nr_banks; 337 unsigned int nr_pins; 338 unsigned int pud_val[PUD_MAX]; 339 340 struct samsung_retention_ctrl *retention_ctrl; 341 342 void (*suspend)(struct samsung_pin_bank *bank); 343 void (*resume)(struct samsung_pin_bank *bank); 344 }; 345 346 /** 347 * struct samsung_pinctrl_of_match_data: OF match device specific configuration data. 348 * @ctrl: array of pin controller data. 349 * @num_ctrl: size of array @ctrl. 350 */ 351 struct samsung_pinctrl_of_match_data { 352 const struct samsung_pin_ctrl *ctrl; 353 unsigned int num_ctrl; 354 }; 355 356 /** 357 * struct samsung_pin_group: represent group of pins of a pinmux function. 358 * @name: name of the pin group, used to lookup the group. 359 * @pins: the pins included in this group. 360 * @num_pins: number of pins included in this group. 361 * @func: the function number to be programmed when selected. 362 */ 363 struct samsung_pin_group { 364 const char *name; 365 const unsigned int *pins; 366 u8 num_pins; 367 u8 func; 368 }; 369 370 /** 371 * struct samsung_pmx_func: represent a pin function. 372 * @name: name of the pin function, used to lookup the function. 373 * @groups: one or more names of pin groups that provide this function. 374 * @num_groups: number of groups included in @groups. 375 */ 376 struct samsung_pmx_func { 377 const char *name; 378 const char **groups; 379 u8 num_groups; 380 u32 val; 381 }; 382 383 /* list of all exported SoC specific data */ 384 extern const struct samsung_pinctrl_of_match_data exynos2200_of_data; 385 extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; 386 extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; 387 extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data; 388 extern const struct samsung_pinctrl_of_match_data exynos5250_of_data; 389 extern const struct samsung_pinctrl_of_match_data exynos5260_of_data; 390 extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; 391 extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; 392 extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; 393 extern const struct samsung_pinctrl_of_match_data exynos7_of_data; 394 extern const struct samsung_pinctrl_of_match_data exynos7870_of_data; 395 extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; 396 extern const struct samsung_pinctrl_of_match_data exynos850_of_data; 397 extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; 398 extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; 399 extern const struct samsung_pinctrl_of_match_data exynos990_of_data; 400 extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; 401 extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data; 402 extern const struct samsung_pinctrl_of_match_data fsd_of_data; 403 extern const struct samsung_pinctrl_of_match_data gs101_of_data; 404 extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; 405 extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; 406 extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; 407 extern const struct samsung_pinctrl_of_match_data s3c2440_of_data; 408 extern const struct samsung_pinctrl_of_match_data s3c2450_of_data; 409 extern const struct samsung_pinctrl_of_match_data s5pv210_of_data; 410 411 #endif /* __PINCTRL_SAMSUNG_H */ 412