1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2023-2025 Intel Corporation
4 */
5
6 #ifndef __fw_regulatory_h__
7 #define __fw_regulatory_h__
8
9 #include "fw/img.h"
10 #include "fw/api/commands.h"
11 #include "fw/api/power.h"
12 #include "fw/api/phy.h"
13 #include "fw/api/config.h"
14 #include "fw/api/nvm-reg.h"
15 #include "iwl-trans.h"
16
17 #define BIOS_SAR_MAX_PROFILE_NUM 4
18 /*
19 * Each SAR profile has (up to, depends on the table revision) 4 chains:
20 * chain A, chain B, chain A when in CDB, chain B when in CDB
21 */
22 #define BIOS_SAR_MAX_CHAINS_PER_PROFILE 4
23 #define BIOS_SAR_NUM_CHAINS 2
24 #define BIOS_SAR_MAX_SUB_BANDS_NUM 11
25
26 #define BIOS_GEO_NUM_CHAINS 2
27 #define BIOS_GEO_MAX_NUM_BANDS 3
28 #define BIOS_GEO_MAX_PROFILE_NUM 8
29 #define BIOS_GEO_MIN_PROFILE_NUM 3
30
31 #define IWL_SAR_ENABLE_MSK BIT(0)
32
33 /* PPAG gain value bounds in 1/8 dBm */
34 #define IWL_PPAG_MIN_LB -16
35 #define IWL_PPAG_MAX_LB 24
36 #define IWL_PPAG_MIN_HB -16
37 #define IWL_PPAG_MAX_HB 40
38
39 #define IWL_PPAG_ETSI_CHINA_MASK 3
40 #define IWL_PPAG_REV3_MASK 0x7FF
41
42 #define IWL_WTAS_ENABLED_MSK BIT(0)
43 #define IWL_WTAS_OVERRIDE_IEC_MSK BIT(1)
44 #define IWL_WTAS_ENABLE_IEC_MSK BIT(2)
45 #define IWL_WTAS_CANADA_UHB_MSK BIT(15)
46 #define IWL_WTAS_USA_UHB_MSK BIT(16)
47
48 struct iwl_tas_selection_data {
49 u8 override_tas_iec:1,
50 enable_tas_iec:1,
51 usa_tas_uhb_allowed:1,
52 canada_tas_uhb_allowed:1;
53 };
54
55 #define BIOS_MCC_CHINA 0x434e
56
57 /*
58 * The profile for revision 2 is a superset of revision 1, which is in
59 * turn a superset of revision 0. So we can store all revisions
60 * inside revision 2, which is what we represent here.
61 */
62
63 /*
64 * struct iwl_sar_profile_chain - per-chain values of a SAR profile
65 * @subbands: the SAR value for each subband
66 */
67 struct iwl_sar_profile_chain {
68 u8 subbands[BIOS_SAR_MAX_SUB_BANDS_NUM];
69 };
70
71 /*
72 * struct iwl_sar_profile - SAR profile from SAR tables
73 * @enabled: whether the profile is enabled or not
74 * @chains: per-chain SAR values
75 */
76 struct iwl_sar_profile {
77 bool enabled;
78 struct iwl_sar_profile_chain chains[BIOS_SAR_MAX_CHAINS_PER_PROFILE];
79 };
80
81 /* Same thing as with SAR, all revisions fit in revision 2 */
82
83 /*
84 * struct iwl_geo_profile_band - per-band geo SAR offsets
85 * @max: the max tx power allowed for the band
86 * @chains: SAR offsets values for each chain
87 */
88 struct iwl_geo_profile_band {
89 u8 max;
90 u8 chains[BIOS_GEO_NUM_CHAINS];
91 };
92
93 /*
94 * struct iwl_geo_profile - geo profile
95 * @bands: per-band table of the SAR offsets
96 */
97 struct iwl_geo_profile {
98 struct iwl_geo_profile_band bands[BIOS_GEO_MAX_NUM_BANDS];
99 };
100
101 /* Same thing as with SAR, all revisions fit in revision 2 */
102 struct iwl_ppag_chain {
103 s8 subbands[BIOS_SAR_MAX_SUB_BANDS_NUM];
104 };
105
106 struct iwl_tas_data {
107 u8 block_list_size;
108 u16 block_list_array[IWL_WTAS_BLACK_LIST_MAX];
109 u8 table_source;
110 u8 table_revision;
111 u32 tas_selection;
112 };
113
114 /* For DSM revision 0 and 4 */
115 enum iwl_dsm_funcs {
116 DSM_FUNC_QUERY = 0,
117 DSM_FUNC_DISABLE_SRD = 1,
118 DSM_FUNC_ENABLE_INDONESIA_5G2 = 2,
119 DSM_FUNC_ENABLE_6E = 3,
120 DSM_FUNC_REGULATORY_CONFIG = 4,
121 DSM_FUNC_11AX_ENABLEMENT = 6,
122 DSM_FUNC_ENABLE_UNII4_CHAN = 7,
123 DSM_FUNC_ACTIVATE_CHANNEL = 8,
124 DSM_FUNC_FORCE_DISABLE_CHANNELS = 9,
125 DSM_FUNC_ENERGY_DETECTION_THRESHOLD = 10,
126 DSM_FUNC_RFI_CONFIG = 11,
127 DSM_FUNC_ENABLE_11BE = 12,
128 DSM_FUNC_ENABLE_11BN = 13,
129 DSM_FUNC_ENABLE_UNII_9 = 14,
130 DSM_FUNC_NUM_FUNCS,
131 };
132
133 enum iwl_dsm_values_srd {
134 DSM_VALUE_SRD_ACTIVE,
135 DSM_VALUE_SRD_PASSIVE,
136 DSM_VALUE_SRD_DISABLE,
137 DSM_VALUE_SRD_MAX
138 };
139
140 enum iwl_dsm_values_indonesia {
141 DSM_VALUE_INDONESIA_DISABLE,
142 DSM_VALUE_INDONESIA_ENABLE,
143 DSM_VALUE_INDONESIA_RESERVED,
144 DSM_VALUE_INDONESIA_MAX
145 };
146
147 enum iwl_dsm_unii4_bitmap {
148 DSM_VALUE_UNII4_US_OVERRIDE_MSK = BIT(0),
149 DSM_VALUE_UNII4_US_EN_MSK = BIT(1),
150 DSM_VALUE_UNII4_ETSI_OVERRIDE_MSK = BIT(2),
151 DSM_VALUE_UNII4_ETSI_EN_MSK = BIT(3),
152 DSM_VALUE_UNII4_CANADA_OVERRIDE_MSK = BIT(4),
153 DSM_VALUE_UNII4_CANADA_EN_MSK = BIT(5),
154 };
155
156 #define DSM_UNII4_ALLOW_BITMAP (DSM_VALUE_UNII4_US_OVERRIDE_MSK |\
157 DSM_VALUE_UNII4_US_EN_MSK |\
158 DSM_VALUE_UNII4_ETSI_OVERRIDE_MSK |\
159 DSM_VALUE_UNII4_ETSI_EN_MSK |\
160 DSM_VALUE_UNII4_CANADA_OVERRIDE_MSK |\
161 DSM_VALUE_UNII4_CANADA_EN_MSK)
162
163 #define DSM_11AX_ALLOW_BITMAP 0xF
164 #define DSM_EDT_ALLOWED_BITMAP 0x7ffff0
165 #define DSM_FORCE_DISABLE_CHANNELS_ALLOWED_BITMAP 0x7FF
166
167 enum iwl_dsm_values_rfi {
168 DSM_VALUE_RFI_DLVR_DISABLE = BIT(0),
169 DSM_VALUE_RFI_DDR_DISABLE = BIT(1),
170 };
171
172 #define DSM_VALUE_RFI_DISABLE (DSM_VALUE_RFI_DLVR_DISABLE |\
173 DSM_VALUE_RFI_DDR_DISABLE)
174
175 bool iwl_rfi_is_enabled_in_bios(struct iwl_fw_runtime *fwrt);
176
177 enum iwl_dsm_masks_reg {
178 DSM_MASK_CHINA_22_REG = BIT(2)
179 };
180
181 struct iwl_fw_runtime;
182
183 bool iwl_sar_geo_support(struct iwl_fw_runtime *fwrt);
184
185 int iwl_sar_geo_fill_table(struct iwl_fw_runtime *fwrt,
186 struct iwl_per_chain_offset *table,
187 u32 n_bands, u32 n_profiles);
188
189 int iwl_sar_fill_profile(struct iwl_fw_runtime *fwrt,
190 __le16 *per_chain, u32 n_tables, u32 n_subbands,
191 int prof_a, int prof_b);
192
193 int iwl_fill_ppag_table(struct iwl_fw_runtime *fwrt,
194 union iwl_ppag_table_cmd *cmd,
195 int *cmd_size);
196
197 bool iwl_is_ppag_approved(struct iwl_fw_runtime *fwrt);
198
199 bool iwl_is_tas_approved(void);
200 bool iwl_add_mcc_to_tas_block_list(u16 *list, u8 *size, u16 mcc);
201
202 struct iwl_tas_selection_data
203 iwl_parse_tas_selection(const u32 tas_selection, const u8 tbl_rev);
204
205 int iwl_bios_get_wrds_table(struct iwl_fw_runtime *fwrt);
206
207 int iwl_bios_get_ewrd_table(struct iwl_fw_runtime *fwrt);
208
209 int iwl_bios_get_wgds_table(struct iwl_fw_runtime *fwrt);
210
211 int iwl_bios_get_ppag_table(struct iwl_fw_runtime *fwrt);
212
213 int iwl_bios_get_tas_table(struct iwl_fw_runtime *fwrt,
214 struct iwl_tas_data *data);
215
216 int iwl_bios_get_pwr_limit(struct iwl_fw_runtime *fwrt,
217 u64 *dflt_pwr_limit);
218
219 int iwl_bios_get_mcc(struct iwl_fw_runtime *fwrt, char *mcc);
220 int iwl_bios_get_eckv(struct iwl_fw_runtime *fwrt, u32 *ext_clk);
221 int iwl_bios_get_wbem(struct iwl_fw_runtime *fwrt, u32 *value);
222
223 int iwl_bios_get_dsm(struct iwl_fw_runtime *fwrt, enum iwl_dsm_funcs func,
224 u32 *value);
225
iwl_bios_get_ppag_flags(const u32 ppag_modes,const u8 ppag_bios_rev)226 static inline u32 iwl_bios_get_ppag_flags(const u32 ppag_modes,
227 const u8 ppag_bios_rev)
228 {
229 /* For revision 4 and above driver is pipe */
230 if (ppag_bios_rev >= 4)
231 return ppag_modes;
232
233 return ppag_modes & (ppag_bios_rev < 3 ? IWL_PPAG_ETSI_CHINA_MASK :
234 IWL_PPAG_REV3_MASK);
235 }
236
237 bool iwl_puncturing_is_allowed_in_bios(u32 puncturing, u16 mcc);
238
239 #define IWL_DSBR_FW_MODIFIED_URM_MASK BIT(8)
240 #define IWL_DSBR_PERMANENT_URM_MASK BIT(9)
241
242 int iwl_bios_get_dsbr(struct iwl_fw_runtime *fwrt, u32 *value);
243 int iwl_bios_get_phy_filters(struct iwl_fw_runtime *fwrt);
244
iwl_bios_setup_step(struct iwl_trans * trans,struct iwl_fw_runtime * fwrt)245 static inline void iwl_bios_setup_step(struct iwl_trans *trans,
246 struct iwl_fw_runtime *fwrt)
247 {
248 u32 dsbr;
249
250 if (!trans->mac_cfg->integrated)
251 return;
252
253 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ)
254 return;
255
256 if (iwl_bios_get_dsbr(fwrt, &dsbr))
257 dsbr = 0;
258
259 trans->conf.dsbr_urm_fw_dependent =
260 !!(dsbr & IWL_DSBR_FW_MODIFIED_URM_MASK);
261 trans->conf.dsbr_urm_permanent =
262 !!(dsbr & IWL_DSBR_PERMANENT_URM_MASK);
263 }
264 #endif /* __fw_regulatory_h__ */
265