1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 #ifndef _XE_REGS_H_
6 #define _XE_REGS_H_
7 
8 #include "regs/xe_reg_defs.h"
9 
10 #define GU_CNTL_PROTECTED			XE_REG(0x10100C)
11 #define   DRIVERINT_FLR_DIS			REG_BIT(31)
12 
13 #define GU_CNTL					XE_REG(0x101010)
14 #define   LMEM_INIT				REG_BIT(7)
15 #define   DRIVERFLR				REG_BIT(31)
16 
17 #define XEHP_CLOCK_GATE_DIS			XE_REG(0x101014)
18 #define   SGSI_SIDECLK_DIS			REG_BIT(17)
19 
20 #define GU_DEBUG				XE_REG(0x101018)
21 #define   DRIVERFLR_STATUS			REG_BIT(31)
22 
23 #define VIRTUAL_CTRL_REG			XE_REG(0x10108c)
24 #define   GUEST_GTT_UPDATE_EN			REG_BIT(8)
25 
26 #define XEHP_MTCFG_ADDR				XE_REG(0x101800)
27 #define   TILE_COUNT				REG_GENMASK(15, 8)
28 
29 #define GGC					XE_REG(0x108040)
30 #define   GMS_MASK				REG_GENMASK(15, 8)
31 #define   GGMS_MASK				REG_GENMASK(7, 6)
32 
33 #define DSMBASE					XE_REG(0x1080C0)
34 #define   BDSM_MASK				REG_GENMASK64(63, 20)
35 
36 #define GSMBASE					XE_REG(0x108100)
37 
38 #define STOLEN_RESERVED				XE_REG(0x1082c0)
39 #define   WOPCM_SIZE_MASK			REG_GENMASK64(9, 7)
40 
41 #define MTL_RP_STATE_CAP			XE_REG(0x138000)
42 
43 #define MTL_GT_RPA_FREQUENCY			XE_REG(0x138008)
44 #define MTL_GT_RPE_FREQUENCY			XE_REG(0x13800c)
45 
46 #define MTL_MEDIAP_STATE_CAP			XE_REG(0x138020)
47 #define   MTL_RPN_CAP_MASK			REG_GENMASK(24, 16)
48 #define   MTL_RP0_CAP_MASK			REG_GENMASK(8, 0)
49 
50 #define MTL_MPA_FREQUENCY			XE_REG(0x138028)
51 #define   MTL_RPA_MASK				REG_GENMASK(8, 0)
52 
53 #define MTL_MPE_FREQUENCY			XE_REG(0x13802c)
54 #define   MTL_RPE_MASK				REG_GENMASK(8, 0)
55 
56 #define VF_CAP_REG				XE_REG(0x1901f8, XE_REG_OPTION_VF)
57 #define   VF_CAP				REG_BIT(0)
58 
59 #define PVC_RP_STATE_CAP			XE_REG(0x281014)
60 
61 #endif
62