1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 #ifndef _ASMX86_DEBUGREG_H_ 3 #define _ASMX86_DEBUGREG_H_ 4 5 #include <bitops.h> 6 7 /* 8 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits (e.g. RTM), and is also 9 * the init/reset value for DR6. 10 */ 11 #define DR6_ACTIVE_LOW 0xffff0ff0 12 #define DR6_VOLATILE 0x0001e80f 13 #define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE) 14 15 #define DR6_TRAP0 BIT(0) /* DR0 matched */ 16 #define DR6_TRAP1 BIT(1) /* DR1 matched */ 17 #define DR6_TRAP2 BIT(2) /* DR2 matched */ 18 #define DR6_TRAP3 BIT(3) /* DR3 matched */ 19 #define DR6_TRAP_BITS (DR6_TRAP0|DR6_TRAP1|DR6_TRAP2|DR6_TRAP3) 20 21 #define DR6_BUS_LOCK BIT(11) /* Bus lock 0x800 */ 22 #define DR6_BD BIT(13) /* General Detect 0x2000 */ 23 #define DR6_BS BIT(14) /* Single-Step 0x4000 */ 24 #define DR6_BT BIT(15) /* Task Switch 0x8000 */ 25 #define DR6_RTM BIT(16) /* RTM / TSX 0x10000 */ 26 27 #define DR7_FIXED_1 0x00000400 /* init/reset value, too */ 28 #define DR7_VOLATILE 0xffff2bff 29 #define DR7_BP_EN_MASK 0x000000ff 30 #define DR7_LE BIT(8) /* Local Exact 0x100 */ 31 #define DR7_GE BIT(9) /* Global Exact 0x200 */ 32 #define DR7_RTM BIT(11) /* RTM / TSX 0x800 */ 33 #define DR7_GD BIT(13) /* General Detect 0x2000 */ 34 35 /* 36 * Enable bits for DR0-D3. Bits 0, 2, 4, and 6 are local enable bits (cleared 37 * by the CPU on task switch), bits 1, 3, 5, and 7 are global enable bits 38 * (never cleared by the CPU). 39 */ 40 #define DR7_LOCAL_ENABLE_DRx(x) (BIT(0) << (x)) 41 #define DR7_GLOBAL_ENABLE_DRx(x) (BIT(1) << (x)) 42 #define DR7_ENABLE_DRx(x) \ 43 (DR7_LOCAL_ENABLE_DRx(x) | DR7_GLOBAL_ENABLE_DRx(x)) 44 45 #define DR7_GLOBAL_ENABLE_DR0 DR7_GLOBAL_ENABLE_DRx(0) 46 #define DR7_GLOBAL_ENABLE_DR1 DR7_GLOBAL_ENABLE_DRx(1) 47 #define DR7_GLOBAL_ENABLE_DR2 DR7_GLOBAL_ENABLE_DRx(2) 48 #define DR7_GLOBAL_ENABLE_DR3 DR7_GLOBAL_ENABLE_DRx(3) 49 50 /* Condition/type of the breakpoint for DR0-3. */ 51 #define DR7_RW_TYPE_DRx(x, rw) ((rw) << (((x) * 4) + 16)) 52 #define DR7_EXECUTE_DRx(x) DR7_RW_TYPE_DRx(x, 0) 53 #define DR7_WRITE_DRx(x) DR7_RW_TYPE_DRx(x, 1) 54 #define DR7_PORT_IO_DRx(x) DR7_RW_TYPE_DRx(x, 2) 55 #define DR7_DATA_IO_DRx(x) DR7_RW_TYPE_DRx(x, 3) /* Read or Write */ 56 57 /* Length of the breakpoint for DR0-3. */ 58 #define DR7_LEN_DRx(x, enc) ((enc) << (((x) * 4) + 18)) 59 #define DR7_LEN_1_DRx(x) DR7_LEN_DRx(x, 0) 60 #define DR7_LEN_2_DRx(x) DR7_LEN_DRx(x, 1) 61 #define DR7_LEN_4_DRx(x) DR7_LEN_DRx(x, 3) 62 #define DR7_LEN_8_DRx(x) DR7_LEN_DRx(x, 2) /* Out of sequence, undefined for 32-bit CPUs. */ 63 64 #endif /* _ASMX86_DEBUGREG_H_ */ 65