1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_H_ 24 #define _DRM_DP_H_ 25 26 #include <linux/types.h> 27 28 /* 29 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 30 * DP and DPCD versions are independent. Differences from 1.0 are not noted, 31 * 1.0 devices basically don't exist in the wild. 32 * 33 * Abbreviations, in chronological order: 34 * 35 * eDP: Embedded DisplayPort version 1 36 * DPI: DisplayPort Interoperability Guideline v1.1a 37 * 1.2: DisplayPort 1.2 38 * MST: Multistream Transport - part of DP 1.2a 39 * 40 * 1.2 formally includes both eDP and DPI definitions. 41 */ 42 43 /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */ 44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0) 45 #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8) 46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9) 47 #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9) 48 #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9) 49 /* bits per component for non-RAW */ 50 #define DP_MSA_MISC_6_BPC (0 << 5) 51 #define DP_MSA_MISC_8_BPC (1 << 5) 52 #define DP_MSA_MISC_10_BPC (2 << 5) 53 #define DP_MSA_MISC_12_BPC (3 << 5) 54 #define DP_MSA_MISC_16_BPC (4 << 5) 55 /* bits per component for RAW */ 56 #define DP_MSA_MISC_RAW_6_BPC (1 << 5) 57 #define DP_MSA_MISC_RAW_7_BPC (2 << 5) 58 #define DP_MSA_MISC_RAW_8_BPC (3 << 5) 59 #define DP_MSA_MISC_RAW_10_BPC (4 << 5) 60 #define DP_MSA_MISC_RAW_12_BPC (5 << 5) 61 #define DP_MSA_MISC_RAW_14_BPC (6 << 5) 62 #define DP_MSA_MISC_RAW_16_BPC (7 << 5) 63 /* pixel encoding/colorimetry format */ 64 #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \ 65 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1)) 66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0) 67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0) 68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0) 69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1) 70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0) 71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0) 72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0) 73 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1) 74 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0) 75 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1) 76 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0) 77 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1) 78 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0) 79 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1) 80 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1) 81 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0) 82 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1) 83 #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14) 84 85 #define DP_AUX_MAX_PAYLOAD_BYTES 16 86 87 #define DP_AUX_I2C_WRITE 0x0 88 #define DP_AUX_I2C_READ 0x1 89 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 90 #define DP_AUX_I2C_MOT 0x4 91 #define DP_AUX_NATIVE_WRITE 0x8 92 #define DP_AUX_NATIVE_READ 0x9 93 94 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 95 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 96 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 97 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 98 99 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 100 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 101 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 102 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 103 104 /* DPCD Field Address Mapping */ 105 106 /* Receiver Capability */ 107 #define DP_DPCD_REV 0x000 108 # define DP_DPCD_REV_10 0x10 109 # define DP_DPCD_REV_11 0x11 110 # define DP_DPCD_REV_12 0x12 111 # define DP_DPCD_REV_13 0x13 112 # define DP_DPCD_REV_14 0x14 113 114 #define DP_MAX_LINK_RATE 0x001 115 116 #define DP_MAX_LANE_COUNT 0x002 117 # define DP_MAX_LANE_COUNT_MASK 0x1f 118 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 119 # define DP_ENHANCED_FRAME_CAP (1 << 7) 120 121 #define DP_MAX_DOWNSPREAD 0x003 122 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0) 123 # define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */ 124 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 125 # define DP_TPS4_SUPPORTED (1 << 7) 126 127 #define DP_NORP 0x004 128 129 #define DP_DOWNSTREAMPORT_PRESENT 0x005 130 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 131 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 132 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 133 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 134 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 135 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 136 # define DP_FORMAT_CONVERSION (1 << 3) 137 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 138 139 #define DP_MAIN_LINK_CHANNEL_CODING 0x006 140 # define DP_CAP_ANSI_8B10B (1 << 0) 141 # define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */ 142 143 #define DP_DOWN_STREAM_PORT_COUNT 0x007 144 # define DP_PORT_COUNT_MASK 0x0f 145 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 146 # define DP_OUI_SUPPORT (1 << 7) 147 148 #define DP_RECEIVE_PORT_0_CAP_0 0x008 149 # define DP_LOCAL_EDID_PRESENT (1 << 1) 150 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) 151 # define DP_HBLANK_EXPANSION_CAPABLE (1 << 3) 152 153 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 154 155 #define DP_RECEIVE_PORT_1_CAP_0 0x00a 156 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b 157 158 #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 159 # define DP_I2C_SPEED_1K 0x01 160 # define DP_I2C_SPEED_5K 0x02 161 # define DP_I2C_SPEED_10K 0x04 162 # define DP_I2C_SPEED_100K 0x08 163 # define DP_I2C_SPEED_400K 0x10 164 # define DP_I2C_SPEED_1M 0x20 165 166 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 167 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) 168 # define DP_FRAMING_CHANGE_CAP (1 << 1) 169 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ 170 171 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 172 # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */ 173 # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */ 174 175 #define DP_ADAPTER_CAP 0x00f /* 1.2 */ 176 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) 177 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) 178 179 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ 180 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ 181 182 /* Multiple stream transport */ 183 #define DP_FAUX_CAP 0x020 /* 1.2 */ 184 # define DP_FAUX_CAP_1 (1 << 0) 185 186 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */ 187 # define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0) 188 # define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1) 189 # define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2) 190 191 #define DP_MSTM_CAP 0x021 /* 1.2 */ 192 # define DP_MST_CAP (1 << 0) 193 # define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */ 194 195 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ 196 197 /* AV_SYNC_DATA_BLOCK 1.2 */ 198 #define DP_AV_GRANULARITY 0x023 199 # define DP_AG_FACTOR_MASK (0xf << 0) 200 # define DP_AG_FACTOR_3MS (0 << 0) 201 # define DP_AG_FACTOR_2MS (1 << 0) 202 # define DP_AG_FACTOR_1MS (2 << 0) 203 # define DP_AG_FACTOR_500US (3 << 0) 204 # define DP_AG_FACTOR_200US (4 << 0) 205 # define DP_AG_FACTOR_100US (5 << 0) 206 # define DP_AG_FACTOR_10US (6 << 0) 207 # define DP_AG_FACTOR_1US (7 << 0) 208 # define DP_VG_FACTOR_MASK (0xf << 4) 209 # define DP_VG_FACTOR_3MS (0 << 4) 210 # define DP_VG_FACTOR_2MS (1 << 4) 211 # define DP_VG_FACTOR_1MS (2 << 4) 212 # define DP_VG_FACTOR_500US (3 << 4) 213 # define DP_VG_FACTOR_200US (4 << 4) 214 # define DP_VG_FACTOR_100US (5 << 4) 215 216 #define DP_AUD_DEC_LAT0 0x024 217 #define DP_AUD_DEC_LAT1 0x025 218 219 #define DP_AUD_PP_LAT0 0x026 220 #define DP_AUD_PP_LAT1 0x027 221 222 #define DP_VID_INTER_LAT 0x028 223 224 #define DP_VID_PROG_LAT 0x029 225 226 #define DP_REP_LAT 0x02a 227 228 #define DP_AUD_DEL_INS0 0x02b 229 #define DP_AUD_DEL_INS1 0x02c 230 #define DP_AUD_DEL_INS2 0x02d 231 /* End of AV_SYNC_DATA_BLOCK */ 232 233 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ 234 # define DP_ALPM_CAP (1 << 0) 235 # define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */ 236 # define DP_ALPM_AUX_LESS_CAP (1 << 2) /* eDP 1.5 */ 237 238 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ 239 # define DP_AUX_FRAME_SYNC_CAP (1 << 0) 240 241 #define DP_GUID 0x030 /* 1.2 */ 242 243 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ 244 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) 245 # define DP_DSC_PASSTHROUGH_IS_SUPPORTED (1 << 1) 246 # define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) 247 # define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) 248 249 #define DP_DSC_REV 0x061 250 # define DP_DSC_MAJOR_MASK (0xf << 0) 251 # define DP_DSC_MINOR_MASK (0xf << 4) 252 # define DP_DSC_MAJOR_SHIFT 0 253 # define DP_DSC_MINOR_SHIFT 4 254 255 #define DP_DSC_RC_BUF_BLK_SIZE 0x062 256 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 257 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 258 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 259 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 260 261 #define DP_DSC_RC_BUF_SIZE 0x063 262 263 #define DP_DSC_SLICE_CAP_1 0x064 264 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) 265 # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) 266 # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) 267 # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) 268 # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) 269 # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) 270 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) 271 272 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 273 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) 274 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 275 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 276 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 277 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 278 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 279 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 280 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 281 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 282 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 283 284 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 285 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) 286 # define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) 287 288 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ 289 290 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ 291 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) 292 # define DP_DSC_MAX_BPP_DELTA_VERSION_MASK (0x3 << 5) /* eDP 1.5 & DP 2.0 */ 293 # define DP_DSC_MAX_BPP_DELTA_AVAILABILITY (1 << 7) /* eDP 1.5 & DP 2.0 */ 294 295 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 296 # define DP_DSC_RGB (1 << 0) 297 # define DP_DSC_YCbCr444 (1 << 1) 298 # define DP_DSC_YCbCr422_Simple (1 << 2) 299 # define DP_DSC_YCbCr422_Native (1 << 3) 300 # define DP_DSC_YCbCr420_Native (1 << 4) 301 302 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A 303 # define DP_DSC_8_BPC (1 << 1) 304 # define DP_DSC_10_BPC (1 << 2) 305 # define DP_DSC_12_BPC (1 << 3) 306 307 #define DP_DSC_PEAK_THROUGHPUT 0x06B 308 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) 309 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 310 # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0 311 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) 312 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) 313 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) 314 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) 315 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) 316 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) 317 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) 318 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) 319 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) 320 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) 321 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) 322 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) 323 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) 324 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) 325 # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ 326 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) 327 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 328 # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0 329 # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) 330 # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) 331 # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) 332 # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) 333 # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) 334 # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) 335 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) 336 # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) 337 # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) 338 # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) 339 # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) 340 # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) 341 # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) 342 # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) 343 # define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4) 344 345 #define DP_DSC_MAX_SLICE_WIDTH 0x06C 346 #define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560 347 #define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 348 349 #define DP_DSC_SLICE_CAP_2 0x06D 350 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) 351 # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) 352 # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) 353 354 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F 355 # define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f 356 # define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 357 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 358 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 359 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 360 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 361 # define DP_DSC_BITS_PER_PIXEL_1_1 0x4 362 # define DP_DSC_BITS_PER_PIXEL_MASK 0x7 363 364 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 365 # define DP_PSR_IS_SUPPORTED 1 366 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ 367 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ 368 # define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4 /* eDP 1.5, adopted eDP 1.4b SCR */ 369 370 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 371 # define DP_PSR_NO_TRAIN_ON_EXIT 1 372 # define DP_PSR_SETUP_TIME_330 (0 << 1) 373 # define DP_PSR_SETUP_TIME_275 (1 << 1) 374 # define DP_PSR_SETUP_TIME_220 (2 << 1) 375 # define DP_PSR_SETUP_TIME_165 (3 << 1) 376 # define DP_PSR_SETUP_TIME_110 (4 << 1) 377 # define DP_PSR_SETUP_TIME_55 (5 << 1) 378 # define DP_PSR_SETUP_TIME_0 (6 << 1) 379 # define DP_PSR_SETUP_TIME_MASK (7 << 1) 380 # define DP_PSR_SETUP_TIME_SHIFT 1 381 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ 382 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ 383 # define DP_PSR2_SU_AUX_FRAME_SYNC_NOT_NEEDED (1 << 6)/* eDP 1.5, adopted eDP 1.4b SCR */ 384 385 #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */ 386 #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ 387 388 /* 389 * 0x80-0x8f describe downstream port capabilities, but there are two layouts 390 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 391 * each port's descriptor is one byte wide. If it was set, each port's is 392 * four bytes wide, starting with the one byte from the base info. As of 393 * DP interop v1.1a only VGA defines additional detail. 394 */ 395 396 /* offset 0 */ 397 #define DP_DOWNSTREAM_PORT_0 0x80 398 # define DP_DS_PORT_TYPE_MASK (7 << 0) 399 # define DP_DS_PORT_TYPE_DP 0 400 # define DP_DS_PORT_TYPE_VGA 1 401 # define DP_DS_PORT_TYPE_DVI 2 402 # define DP_DS_PORT_TYPE_HDMI 3 403 # define DP_DS_PORT_TYPE_NON_EDID 4 404 # define DP_DS_PORT_TYPE_DP_DUALMODE 5 405 # define DP_DS_PORT_TYPE_WIRELESS 6 406 # define DP_DS_PORT_HPD (1 << 3) 407 # define DP_DS_NON_EDID_MASK (0xf << 4) 408 # define DP_DS_NON_EDID_720x480i_60 (1 << 4) 409 # define DP_DS_NON_EDID_720x480i_50 (2 << 4) 410 # define DP_DS_NON_EDID_1920x1080i_60 (3 << 4) 411 # define DP_DS_NON_EDID_1920x1080i_50 (4 << 4) 412 # define DP_DS_NON_EDID_1280x720_60 (5 << 4) 413 # define DP_DS_NON_EDID_1280x720_50 (7 << 4) 414 /* offset 1 for VGA is maximum megapixels per second / 8 */ 415 /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */ 416 /* offset 2 for VGA/DVI/HDMI */ 417 # define DP_DS_MAX_BPC_MASK (3 << 0) 418 # define DP_DS_8BPC 0 419 # define DP_DS_10BPC 1 420 # define DP_DS_12BPC 2 421 # define DP_DS_16BPC 3 422 /* HDMI2.1 PCON FRL CONFIGURATION */ 423 # define DP_PCON_MAX_FRL_BW (7 << 2) 424 # define DP_PCON_MAX_0GBPS (0 << 2) 425 # define DP_PCON_MAX_9GBPS (1 << 2) 426 # define DP_PCON_MAX_18GBPS (2 << 2) 427 # define DP_PCON_MAX_24GBPS (3 << 2) 428 # define DP_PCON_MAX_32GBPS (4 << 2) 429 # define DP_PCON_MAX_40GBPS (5 << 2) 430 # define DP_PCON_MAX_48GBPS (6 << 2) 431 # define DP_PCON_SOURCE_CTL_MODE (1 << 5) 432 433 /* offset 3 for DVI */ 434 # define DP_DS_DVI_DUAL_LINK (1 << 1) 435 # define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2) 436 /* offset 3 for HDMI */ 437 # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0) 438 # define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1) 439 # define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2) 440 # define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3) 441 # define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4) 442 443 /* 444 * VESA DP-to-HDMI PCON Specification adds caps for colorspace 445 * conversion in DFP cap DPCD 83h. Sec6.1 Table-3. 446 * Based on the available support the source can enable 447 * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2 448 * DPCD 3052h. 449 */ 450 # define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5) 451 # define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6) 452 # define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7) 453 454 #define DP_MAX_DOWNSTREAM_PORTS 0x10 455 456 /* DP Forward error Correction Registers */ 457 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */ 458 # define DP_FEC_CAPABLE (1 << 0) 459 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) 460 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) 461 # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) 462 #define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ 463 464 /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ 465 #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */ 466 #define DP_PCON_DSC_ENCODER 0x092 467 # define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0) 468 # define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1) 469 470 /* DP-HDMI2.1 PCON DSC Version */ 471 #define DP_PCON_DSC_VERSION 0x093 472 # define DP_PCON_DSC_MAJOR_MASK (0xF << 0) 473 # define DP_PCON_DSC_MINOR_MASK (0xF << 4) 474 # define DP_PCON_DSC_MAJOR_SHIFT 0 475 # define DP_PCON_DSC_MINOR_SHIFT 4 476 477 /* DP-HDMI2.1 PCON DSC RC Buffer block size */ 478 #define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094 479 # define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0) 480 # define DP_PCON_DSC_RC_BUF_BLK_1KB 0 481 # define DP_PCON_DSC_RC_BUF_BLK_4KB 1 482 # define DP_PCON_DSC_RC_BUF_BLK_16KB 2 483 # define DP_PCON_DSC_RC_BUF_BLK_64KB 3 484 485 /* DP-HDMI2.1 PCON DSC RC Buffer size */ 486 #define DP_PCON_DSC_RC_BUF_SIZE 0x095 487 488 /* DP-HDMI2.1 PCON DSC Slice capabilities-1 */ 489 #define DP_PCON_DSC_SLICE_CAP_1 0x096 490 # define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0) 491 # define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1) 492 # define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3) 493 # define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4) 494 # define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5) 495 # define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6) 496 # define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7) 497 498 #define DP_PCON_DSC_BUF_BIT_DEPTH 0x097 499 # define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0) 500 # define DP_PCON_DSC_DEPTH_9_BITS 0 501 # define DP_PCON_DSC_DEPTH_10_BITS 1 502 # define DP_PCON_DSC_DEPTH_11_BITS 2 503 # define DP_PCON_DSC_DEPTH_12_BITS 3 504 # define DP_PCON_DSC_DEPTH_13_BITS 4 505 # define DP_PCON_DSC_DEPTH_14_BITS 5 506 # define DP_PCON_DSC_DEPTH_15_BITS 6 507 # define DP_PCON_DSC_DEPTH_16_BITS 7 508 # define DP_PCON_DSC_DEPTH_8_BITS 8 509 510 #define DP_PCON_DSC_BLOCK_PREDICTION 0x098 511 # define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0) 512 513 #define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099 514 # define DP_PCON_DSC_ENC_RGB (0x1 << 0) 515 # define DP_PCON_DSC_ENC_YUV444 (0x1 << 1) 516 # define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2) 517 # define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3) 518 # define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4) 519 520 #define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A 521 # define DP_PCON_DSC_ENC_8BPC (0x1 << 1) 522 # define DP_PCON_DSC_ENC_10BPC (0x1 << 2) 523 # define DP_PCON_DSC_ENC_12BPC (0x1 << 3) 524 525 #define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B 526 527 /* DP-HDMI2.1 PCON DSC Slice capabilities-2 */ 528 #define DP_PCON_DSC_SLICE_CAP_2 0x09C 529 # define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0) 530 # define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1) 531 # define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2) 532 533 /* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */ 534 #define DP_PCON_DSC_BPP_INCR 0x09E 535 # define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0) 536 # define DP_PCON_DSC_ONE_16TH_BPP 0 537 # define DP_PCON_DSC_ONE_8TH_BPP 1 538 # define DP_PCON_DSC_ONE_4TH_BPP 2 539 # define DP_PCON_DSC_ONE_HALF_BPP 3 540 # define DP_PCON_DSC_ONE_BPP 4 541 542 /* DP Extended DSC Capabilities */ 543 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */ 544 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 545 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 546 547 /* DFP Capability Extension */ 548 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ 549 550 #define DP_PANEL_REPLAY_CAP_SUPPORT 0x0b0 /* DP 2.0 */ 551 # define DP_PANEL_REPLAY_SUPPORT (1 << 0) 552 # define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) 553 # define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT (1 << 2) /* eDP 1.5 */ 554 555 #define DP_PANEL_REPLAY_CAP_SIZE 7 556 557 #define DP_PANEL_REPLAY_CAP_CAPABILITY 0xb1 558 # define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT 1 /* DP 2.1a */ 559 # define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK (3 << DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT) 560 # define DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED 0x00 561 # define DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY 0x01 562 # define DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED 0x02 563 # define DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED 0x03 564 # define DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR (1 << 3) 565 # define DP_PANEL_REPLAY_DSC_CRC_OF_MULTIPLE_SUS_SUPPORTED (1 << 4) 566 # define DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5) 567 # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_SUPPORTED (1 << 6) 568 # define DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP (1 << 7) 569 570 #define DP_PANEL_REPLAY_CAP_X_GRANULARITY 0xb2 571 #define DP_PANEL_REPLAY_CAP_Y_GRANULARITY 0xb4 572 573 /* Link Configuration */ 574 #define DP_LINK_BW_SET 0x100 575 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ 576 # define DP_LINK_BW_1_62 0x06 577 # define DP_LINK_BW_2_7 0x0a 578 # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 579 # define DP_LINK_BW_8_1 0x1e /* 1.4 */ 580 # define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */ 581 # define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */ 582 # define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ 583 584 #define DP_LANE_COUNT_SET 0x101 585 # define DP_LANE_COUNT_MASK 0x0f 586 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 587 588 #define DP_TRAINING_PATTERN_SET 0x102 589 # define DP_TRAINING_PATTERN_DISABLE 0 590 # define DP_TRAINING_PATTERN_1 1 591 # define DP_TRAINING_PATTERN_2 2 592 # define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */ 593 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 594 # define DP_TRAINING_PATTERN_4 7 /* 1.4 */ 595 # define DP_TRAINING_PATTERN_MASK 0x3 596 # define DP_TRAINING_PATTERN_MASK_1_4 0xf 597 598 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ 599 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) 600 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) 601 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) 602 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) 603 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) 604 605 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 606 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 607 608 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 609 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 610 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 611 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 612 613 #define DP_TRAINING_LANE0_SET 0x103 614 #define DP_TRAINING_LANE1_SET 0x104 615 #define DP_TRAINING_LANE2_SET 0x105 616 #define DP_TRAINING_LANE3_SET 0x106 617 618 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 619 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 620 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 621 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 622 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 623 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 624 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 625 626 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 627 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 628 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 629 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 630 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 631 632 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 633 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 634 635 # define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */ 636 637 #define DP_DOWNSPREAD_CTRL 0x107 638 # define DP_SPREAD_AMP_0_5 (1 << 4) 639 # define DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE (1 << 6) 640 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 641 642 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 643 # define DP_SET_ANSI_8B10B (1 << 0) 644 # define DP_SET_ANSI_128B132B (1 << 1) 645 646 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 647 /* bitmask as for DP_I2C_SPEED_CAP */ 648 649 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 650 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) 651 # define DP_FRAMING_CHANGE_ENABLE (1 << 1) 652 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) 653 654 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ 655 #define DP_LINK_QUAL_LANE1_SET 0x10c 656 #define DP_LINK_QUAL_LANE2_SET 0x10d 657 #define DP_LINK_QUAL_LANE3_SET 0x10e 658 # define DP_LINK_QUAL_PATTERN_DISABLE 0 659 # define DP_LINK_QUAL_PATTERN_D10_2 1 660 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 661 # define DP_LINK_QUAL_PATTERN_PRBS7 3 662 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 663 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5 664 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6 665 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7 666 /* DP 2.0 UHBR10, UHBR13.5, UHBR20 */ 667 # define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08 668 # define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10 669 # define DP_LINK_QUAL_PATTERN_PRSBS9 0x18 670 # define DP_LINK_QUAL_PATTERN_PRSBS11 0x20 671 # define DP_LINK_QUAL_PATTERN_PRSBS15 0x28 672 # define DP_LINK_QUAL_PATTERN_PRSBS23 0x30 673 # define DP_LINK_QUAL_PATTERN_PRSBS31 0x38 674 # define DP_LINK_QUAL_PATTERN_CUSTOM 0x40 675 # define DP_LINK_QUAL_PATTERN_SQUARE 0x48 676 # define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DISABLED 0x49 677 # define DP_LINK_QUAL_PATTERN_SQUARE_DEEMPHASIS_DISABLED 0x4a 678 # define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED 0x4b 679 680 #define DP_TRAINING_LANE0_1_SET2 0x10f 681 #define DP_TRAINING_LANE2_3_SET2 0x110 682 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) 683 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) 684 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) 685 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) 686 687 #define DP_MSTM_CTRL 0x111 /* 1.2 */ 688 # define DP_MST_EN (1 << 0) 689 # define DP_UP_REQ_EN (1 << 1) 690 # define DP_UPSTREAM_IS_SRC (1 << 2) 691 692 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ 693 #define DP_AUDIO_DELAY1 0x113 694 #define DP_AUDIO_DELAY2 0x114 695 696 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ 697 # define DP_LINK_RATE_SET_SHIFT 0 698 # define DP_LINK_RATE_SET_MASK (7 << 0) 699 700 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ 701 # define DP_ALPM_ENABLE (1 << 0) 702 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) /* eDP 1.5 */ 703 # define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */ 704 705 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ 706 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) 707 # define DP_IRQ_HPD_ENABLE (1 << 1) 708 709 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ 710 # define DP_PWR_NOT_NEEDED (1 << 0) 711 712 #define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_GRANT 0x119 /* 1.4a */ 713 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_GRANTED (1 << 0) 714 715 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ 716 # define DP_FEC_READY (1 << 0) 717 # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) 718 # define DP_FEC_ERR_COUNT_DIS (0 << 1) 719 # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) 720 # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) 721 # define DP_FEC_BIT_ERROR_COUNT (3 << 1) 722 # define DP_FEC_LANE_SELECT_MASK (3 << 4) 723 # define DP_FEC_LANE_0_SELECT (0 << 4) 724 # define DP_FEC_LANE_1_SELECT (1 << 4) 725 # define DP_FEC_LANE_2_SELECT (2 << 4) 726 # define DP_FEC_LANE_3_SELECT (3 << 4) 727 728 #define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */ 729 #define DP_SDP_CRC16_128B132B_EN BIT(0) 730 731 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ 732 # define DP_AUX_FRAME_SYNC_VALID (1 << 0) 733 734 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ 735 # define DP_DECOMPRESSION_EN (1 << 0) 736 # define DP_DSC_PASSTHROUGH_EN (1 << 1) 737 #define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ 738 739 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 740 # define DP_PSR_ENABLE BIT(0) 741 # define DP_PSR_MAIN_LINK_ACTIVE BIT(1) 742 # define DP_PSR_CRC_VERIFICATION BIT(2) 743 # define DP_PSR_FRAME_CAPTURE BIT(3) 744 # define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */ 745 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */ 746 # define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */ 747 # define DP_PSR_ENABLE_SU_REGION_ET BIT(7) /* eDP 1.5 */ 748 749 #define DP_ADAPTER_CTRL 0x1a0 750 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 751 752 #define DP_BRANCH_DEVICE_CTRL 0x1a1 753 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 754 755 #define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */ 756 # define DP_PANEL_REPLAY_ENABLE (1 << 0) 757 # define DP_PANEL_REPLAY_VSC_SDP_CRC_EN (1 << 1) /* eDP 1.5 */ 758 # define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3) 759 # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) 760 # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) 761 # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) 762 # define DP_PANEL_REPLAY_ENABLE_SU_REGION_ET (1 << 7) /* DP 2.1 */ 763 764 #define PANEL_REPLAY_CONFIG2 0x1b1 /* eDP 1.5 */ 765 # define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED (1 << 0) 766 # define DP_PANEL_REPLAY_CRC_VERIFICATION (1 << 1) 767 # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_EN (1 << 2) 768 # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_SHIFT 3 769 # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK (0xf << 3) 770 # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE (1 << 7) 771 772 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 773 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 774 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 775 776 /* Link/Sink Device Status */ 777 #define DP_SINK_COUNT 0x200 778 /* prior to 1.2 bit 7 was reserved mbz */ 779 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 780 # define DP_SINK_CP_READY (1 << 6) 781 782 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 783 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 784 # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 785 # define DP_CP_IRQ (1 << 2) 786 # define DP_MCCS_IRQ (1 << 3) 787 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 788 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 789 # define DP_SINK_SPECIFIC_IRQ (1 << 6) 790 791 #define DP_LANE0_1_STATUS 0x202 792 #define DP_LANE2_3_STATUS 0x203 793 # define DP_LANE_CR_DONE (1 << 0) 794 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 795 # define DP_LANE_SYMBOL_LOCKED (1 << 2) 796 797 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 798 DP_LANE_CHANNEL_EQ_DONE | \ 799 DP_LANE_SYMBOL_LOCKED) 800 801 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 802 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 803 #define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */ 804 #define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */ 805 #define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */ 806 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 807 #define DP_LINK_STATUS_UPDATED (1 << 7) 808 809 #define DP_SINK_STATUS 0x205 810 # define DP_RECEIVE_PORT_0_STATUS (1 << 0) 811 # define DP_RECEIVE_PORT_1_STATUS (1 << 1) 812 # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ 813 # define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ 814 815 #define DP_ADJUST_REQUEST_LANE0_1 0x206 816 #define DP_ADJUST_REQUEST_LANE2_3 0x207 817 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 818 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 819 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 820 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 821 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 822 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 823 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 824 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 825 826 /* DP 2.0 128b/132b Link Layer */ 827 # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0) 828 # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0 829 # define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4) 830 # define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4 831 832 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c 833 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03 834 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0 835 # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c 836 # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2 837 # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30 838 # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4 839 # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0 840 # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6 841 842 #define DP_TEST_REQUEST 0x218 843 # define DP_TEST_LINK_TRAINING (1 << 0) 844 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 845 # define DP_TEST_LINK_EDID_READ (1 << 2) 846 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 847 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 848 # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */ 849 # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */ 850 851 #define DP_TEST_LINK_RATE 0x219 852 # define DP_LINK_RATE_162 (0x6) 853 # define DP_LINK_RATE_27 (0xa) 854 855 #define DP_TEST_LANE_COUNT 0x220 856 857 #define DP_TEST_PATTERN 0x221 858 # define DP_NO_TEST_PATTERN 0x0 859 # define DP_COLOR_RAMP 0x1 860 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 861 # define DP_COLOR_SQUARE 0x3 862 863 #define DP_TEST_H_TOTAL_HI 0x222 864 #define DP_TEST_H_TOTAL_LO 0x223 865 866 #define DP_TEST_V_TOTAL_HI 0x224 867 #define DP_TEST_V_TOTAL_LO 0x225 868 869 #define DP_TEST_H_START_HI 0x226 870 #define DP_TEST_H_START_LO 0x227 871 872 #define DP_TEST_V_START_HI 0x228 873 #define DP_TEST_V_START_LO 0x229 874 875 #define DP_TEST_HSYNC_HI 0x22A 876 # define DP_TEST_HSYNC_POLARITY (1 << 7) 877 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) 878 #define DP_TEST_HSYNC_WIDTH_LO 0x22B 879 880 #define DP_TEST_VSYNC_HI 0x22C 881 # define DP_TEST_VSYNC_POLARITY (1 << 7) 882 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) 883 #define DP_TEST_VSYNC_WIDTH_LO 0x22D 884 885 #define DP_TEST_H_WIDTH_HI 0x22E 886 #define DP_TEST_H_WIDTH_LO 0x22F 887 888 #define DP_TEST_V_HEIGHT_HI 0x230 889 #define DP_TEST_V_HEIGHT_LO 0x231 890 891 #define DP_TEST_MISC0 0x232 892 # define DP_TEST_SYNC_CLOCK (1 << 0) 893 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1) 894 # define DP_TEST_COLOR_FORMAT_SHIFT 1 895 # define DP_COLOR_FORMAT_RGB (0 << 1) 896 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1) 897 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1) 898 # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3) 899 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) 900 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) 901 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) 902 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) 903 # define DP_TEST_BIT_DEPTH_MASK (7 << 5) 904 # define DP_TEST_BIT_DEPTH_SHIFT 5 905 # define DP_TEST_BIT_DEPTH_6 (0 << 5) 906 # define DP_TEST_BIT_DEPTH_8 (1 << 5) 907 # define DP_TEST_BIT_DEPTH_10 (2 << 5) 908 # define DP_TEST_BIT_DEPTH_12 (3 << 5) 909 # define DP_TEST_BIT_DEPTH_16 (4 << 5) 910 911 #define DP_TEST_MISC1 0x233 912 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0) 913 # define DP_TEST_INTERLACED (1 << 1) 914 915 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 916 917 #define DP_TEST_MISC0 0x232 918 919 #define DP_TEST_CRC_R_CR 0x240 920 #define DP_TEST_CRC_G_Y 0x242 921 #define DP_TEST_CRC_B_CB 0x244 922 923 #define DP_TEST_SINK_MISC 0x246 924 # define DP_TEST_CRC_SUPPORTED (1 << 5) 925 # define DP_TEST_COUNT_MASK 0xf 926 927 #define DP_PHY_TEST_PATTERN 0x248 928 # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7 929 # define DP_PHY_TEST_PATTERN_NONE 0x0 930 # define DP_PHY_TEST_PATTERN_D10_2 0x1 931 # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 932 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 933 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 934 # define DP_PHY_TEST_PATTERN_CP2520 0x5 935 936 #define DP_PHY_SQUARE_PATTERN 0x249 937 938 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A 939 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 940 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 941 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 942 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 943 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 944 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 945 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 946 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 947 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 948 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 949 950 #define DP_TEST_RESPONSE 0x260 951 # define DP_TEST_ACK (1 << 0) 952 # define DP_TEST_NAK (1 << 1) 953 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 954 955 #define DP_TEST_EDID_CHECKSUM 0x261 956 957 #define DP_TEST_SINK 0x270 958 # define DP_TEST_SINK_START (1 << 0) 959 #define DP_TEST_AUDIO_MODE 0x271 960 #define DP_TEST_AUDIO_PATTERN_TYPE 0x272 961 #define DP_TEST_AUDIO_PERIOD_CH1 0x273 962 #define DP_TEST_AUDIO_PERIOD_CH2 0x274 963 #define DP_TEST_AUDIO_PERIOD_CH3 0x275 964 #define DP_TEST_AUDIO_PERIOD_CH4 0x276 965 #define DP_TEST_AUDIO_PERIOD_CH5 0x277 966 #define DP_TEST_AUDIO_PERIOD_CH6 0x278 967 #define DP_TEST_AUDIO_PERIOD_CH7 0x279 968 #define DP_TEST_AUDIO_PERIOD_CH8 0x27A 969 970 #define DP_FEC_STATUS 0x280 /* 1.4 */ 971 # define DP_FEC_DECODE_EN_DETECTED (1 << 0) 972 # define DP_FEC_DECODE_DIS_DETECTED (1 << 1) 973 974 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */ 975 976 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */ 977 # define DP_FEC_ERROR_COUNT_MASK 0x7F 978 # define DP_FEC_ERR_COUNT_VALID (1 << 7) 979 980 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 981 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 982 # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 983 984 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 985 /* up to ID_SLOT_63 at 0x2ff */ 986 987 /* Source Device-specific */ 988 #define DP_SOURCE_OUI 0x300 989 990 /* Sink Device-specific */ 991 #define DP_SINK_OUI 0x400 992 993 /* Branch Device-specific */ 994 #define DP_BRANCH_OUI 0x500 995 #define DP_BRANCH_ID 0x503 996 #define DP_BRANCH_REVISION_START 0x509 997 #define DP_BRANCH_HW_REV 0x509 998 #define DP_BRANCH_SW_REV 0x50A 999 1000 /* Link/Sink Device Power Control */ 1001 #define DP_SET_POWER 0x600 1002 # define DP_SET_POWER_D0 0x1 1003 # define DP_SET_POWER_D3 0x2 1004 # define DP_SET_POWER_MASK 0x3 1005 # define DP_SET_POWER_D3_AUX_ON 0x5 1006 1007 /* eDP-specific */ 1008 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ 1009 # define DP_EDP_11 0x00 1010 # define DP_EDP_12 0x01 1011 # define DP_EDP_13 0x02 1012 # define DP_EDP_14 0x03 1013 # define DP_EDP_14a 0x04 /* eDP 1.4a */ 1014 # define DP_EDP_14b 0x05 /* eDP 1.4b */ 1015 # define DP_EDP_15 0x06 /* eDP 1.5 */ 1016 1017 #define DP_EDP_GENERAL_CAP_1 0x701 1018 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) 1019 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) 1020 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) 1021 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) 1022 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) 1023 # define DP_EDP_FRC_ENABLE_CAP (1 << 5) 1024 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) 1025 # define DP_EDP_SET_POWER_CAP (1 << 7) 1026 1027 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 1028 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) 1029 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) 1030 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) 1031 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) 1032 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) 1033 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) 1034 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) 1035 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) 1036 1037 #define DP_EDP_GENERAL_CAP_2 0x703 1038 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) 1039 # define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4) 1040 # define DP_EDP_SMOOTH_BRIGHTNESS_CAPABLE (1 << 6) /* eDP 2.0 */ 1041 1042 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ 1043 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) 1044 # define DP_EDP_X_REGION_CAP_SHIFT 0 1045 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) 1046 # define DP_EDP_Y_REGION_CAP_SHIFT 4 1047 1048 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 1049 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) 1050 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) 1051 # define DP_EDP_FRC_ENABLE (1 << 2) 1052 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) 1053 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) 1054 1055 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 1056 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) 1057 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) 1058 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) 1059 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) 1060 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) 1061 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) 1062 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) 1063 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) 1064 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) 1065 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ 1066 # define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1 << 7) 1067 1068 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 1069 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 1070 1071 #define DP_EDP_PWMGEN_BIT_COUNT 0x724 1072 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 1073 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 1074 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) 1075 1076 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 1077 1078 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 1079 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 1080 1081 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a 1082 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b 1083 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c 1084 1085 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d 1086 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e 1087 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f 1088 1089 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 1090 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 1091 #define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734 1092 1093 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ 1094 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ 1095 1096 #define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */ 1097 # define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0) 1098 # define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0 1099 # define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3) 1100 1101 /* Sideband MSG Buffers */ 1102 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 1103 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 1104 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 1105 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 1106 1107 /* DPRX Event Status Indicator */ 1108 #define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */ 1109 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */ 1110 1111 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 1112 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) 1113 # define DP_LOCK_ACQUISITION_REQUEST (1 << 1) 1114 # define DP_CEC_IRQ (1 << 2) 1115 1116 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 1117 # define RX_CAP_CHANGED (1 << 0) 1118 # define LINK_STATUS_CHANGED (1 << 1) 1119 # define STREAM_STATUS_CHANGED (1 << 2) 1120 # define HDMI_LINK_STATUS_CHANGED (1 << 3) 1121 # define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4) 1122 # define DP_TUNNELING_IRQ (1 << 5) 1123 1124 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 1125 # define DP_PSR_LINK_CRC_ERROR (1 << 0) 1126 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 1127 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ 1128 1129 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 1130 # define DP_PSR_CAPS_CHANGE (1 << 0) 1131 1132 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 1133 # define DP_PSR_SINK_INACTIVE 0 1134 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 1135 # define DP_PSR_SINK_ACTIVE_RFB 2 1136 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 1137 # define DP_PSR_SINK_ACTIVE_RESYNC 4 1138 # define DP_PSR_SINK_INTERNAL_ERROR 7 1139 # define DP_PSR_SINK_STATE_MASK 0x07 1140 1141 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ 1142 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) 1143 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 1144 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) 1145 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 1146 1147 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */ 1148 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */ 1149 # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */ 1150 # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */ 1151 # define DP_SU_VALID (1 << 3) /* eDP 1.4 */ 1152 # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */ 1153 # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */ 1154 # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */ 1155 1156 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ 1157 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) 1158 1159 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ 1160 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ 1161 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ 1162 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ 1163 1164 #define DP_PANEL_REPLAY_ERROR_STATUS 0x2020 /* DP 2.1*/ 1165 # define DP_PANEL_REPLAY_LINK_CRC_ERROR (1 << 0) 1166 # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 1) 1167 # define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) 1168 1169 #define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS 0x2022 /* DP 2.1 */ 1170 # define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0) 1171 # define DP_SINK_FRAME_LOCKED_SHIFT 3 1172 # define DP_SINK_FRAME_LOCKED_MASK (3 << 3) 1173 # define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT 5 1174 # define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK (1 << 5) 1175 1176 /* Extended Receiver Capability: See DP_DPCD_REV for definitions */ 1177 #define DP_DP13_DPCD_REV 0x2200 1178 1179 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ 1180 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */ 1181 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ 1182 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ 1183 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ 1184 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ 1185 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ 1186 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ 1187 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ 1188 1189 #define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST 0x2211 /* 1.4a */ 1190 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_MASK 0xff 1191 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_1_MS 0x00 1192 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_20_MS 0x01 1193 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_40_MS 0x02 1194 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_60_MS 0x03 1195 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS 0x04 1196 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS 0x05 1197 1198 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ 1199 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0) 1200 # define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0) 1201 # define DP_ADAPTIVE_SYNC_SDP_LENGTH GENMASK(5, 0) 1202 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1) 1203 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4) 1204 1205 #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ 1206 # define DP_UHBR10 (1 << 0) 1207 # define DP_UHBR20 (1 << 1) 1208 # define DP_UHBR13_5 (1 << 2) 1209 1210 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ 1211 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7) 1212 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f 1213 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00 1214 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01 1215 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02 1216 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03 1217 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04 1218 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05 1219 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06 1220 1221 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 1222 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 1223 1224 /* DSC Extended Capability Branch Total DSC Resources */ 1225 #define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ 1226 # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) 1227 # define DP_DSC_DECODER_COUNT_SHIFT 5 1228 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ 1229 # define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) 1230 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) 1231 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 1232 1233 /* Protocol Converter Extension */ 1234 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ 1235 #define DP_CEC_TUNNELING_CAPABILITY 0x3000 1236 # define DP_CEC_TUNNELING_CAPABLE (1 << 0) 1237 # define DP_CEC_SNOOPING_CAPABLE (1 << 1) 1238 # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) 1239 1240 #define DP_CEC_TUNNELING_CONTROL 0x3001 1241 # define DP_CEC_TUNNELING_ENABLE (1 << 0) 1242 # define DP_CEC_SNOOPING_ENABLE (1 << 1) 1243 1244 #define DP_CEC_RX_MESSAGE_INFO 0x3002 1245 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) 1246 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 1247 # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) 1248 # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) 1249 # define DP_CEC_RX_MESSAGE_ACKED (1 << 6) 1250 # define DP_CEC_RX_MESSAGE_ENDED (1 << 7) 1251 1252 #define DP_CEC_TX_MESSAGE_INFO 0x3003 1253 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) 1254 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 1255 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) 1256 # define DP_CEC_TX_RETRY_COUNT_SHIFT 4 1257 # define DP_CEC_TX_MESSAGE_SEND (1 << 7) 1258 1259 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 1260 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) 1261 # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) 1262 # define DP_CEC_TX_MESSAGE_SENT (1 << 4) 1263 # define DP_CEC_TX_LINE_ERROR (1 << 5) 1264 # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) 1265 # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) 1266 1267 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ 1268 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) 1269 # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) 1270 # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) 1271 # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) 1272 # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) 1273 # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) 1274 # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) 1275 # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) 1276 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ 1277 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) 1278 # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) 1279 # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) 1280 # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) 1281 # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) 1282 # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) 1283 # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) 1284 # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) 1285 1286 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010 1287 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 1288 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 1289 1290 /* PCON CONFIGURE-1 FRL FOR HDMI SINK */ 1291 #define DP_PCON_HDMI_LINK_CONFIG_1 0x305A 1292 # define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0) 1293 # define DP_PCON_ENABLE_MAX_BW_0GBPS 0 1294 # define DP_PCON_ENABLE_MAX_BW_9GBPS 1 1295 # define DP_PCON_ENABLE_MAX_BW_18GBPS 2 1296 # define DP_PCON_ENABLE_MAX_BW_24GBPS 3 1297 # define DP_PCON_ENABLE_MAX_BW_32GBPS 4 1298 # define DP_PCON_ENABLE_MAX_BW_40GBPS 5 1299 # define DP_PCON_ENABLE_MAX_BW_48GBPS 6 1300 # define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) 1301 # define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) 1302 # define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) 1303 # define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) 1304 # define DP_PCON_ENABLE_HPD_READY (1 << 6) 1305 # define DP_PCON_ENABLE_HDMI_LINK (1 << 7) 1306 1307 /* PCON CONFIGURE-2 FRL FOR HDMI SINK */ 1308 #define DP_PCON_HDMI_LINK_CONFIG_2 0x305B 1309 # define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0) 1310 # define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0) 1311 # define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1) 1312 # define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2) 1313 # define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3) 1314 # define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) 1315 # define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) 1316 # define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) 1317 # define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) 1318 1319 /* PCON HDMI LINK STATUS */ 1320 #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B 1321 # define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0) 1322 # define DP_PCON_FRL_READY (1 << 1) 1323 1324 /* PCON HDMI POST FRL STATUS */ 1325 #define DP_PCON_HDMI_POST_FRL_STATUS 0x3036 1326 # define DP_PCON_HDMI_LINK_MODE (1 << 0) 1327 # define DP_PCON_HDMI_MODE_TMDS 0 1328 # define DP_PCON_HDMI_MODE_FRL 1 1329 # define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1) 1330 # define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1) 1331 # define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2) 1332 # define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3) 1333 # define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4) 1334 # define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) 1335 # define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) 1336 1337 #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */ 1338 # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */ 1339 #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */ 1340 # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */ 1341 # define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */ 1342 # define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */ 1343 # define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */ 1344 #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */ 1345 # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */ 1346 # define DP_PCON_ENABLE_DSC_ENCODER (1 << 1) 1347 # define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2) 1348 # define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0 1349 # define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1 1350 # define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2 1351 # define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4) 1352 # define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4) 1353 # define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5) 1354 # define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6) 1355 1356 /* PCON Downstream HDMI ERROR Status per Lane */ 1357 #define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037 1358 #define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038 1359 #define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039 1360 #define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A 1361 # define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0) 1362 # define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0) 1363 # define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1) 1364 # define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2) 1365 1366 /* PCON HDMI CONFIG PPS Override Buffer 1367 * Valid Offsets to be added to Base : 0-127 1368 */ 1369 #define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100 1370 1371 /* PCON HDMI CONFIG PPS Override Parameter: Slice height 1372 * Offset-0 8LSBs of the Slice height. 1373 * Offset-1 8MSBs of the Slice height. 1374 */ 1375 #define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180 1376 1377 /* PCON HDMI CONFIG PPS Override Parameter: Slice width 1378 * Offset-0 8LSBs of the Slice width. 1379 * Offset-1 8MSBs of the Slice width. 1380 */ 1381 #define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182 1382 1383 /* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel 1384 * Offset-0 8LSBs of the bits_per_pixel. 1385 * Offset-1 2MSBs of the bits_per_pixel. 1386 */ 1387 #define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184 1388 1389 /* HDCP 1.3 and HDCP 2.2 */ 1390 #define DP_AUX_HDCP_BKSV 0x68000 1391 #define DP_AUX_HDCP_RI_PRIME 0x68005 1392 #define DP_AUX_HDCP_AKSV 0x68007 1393 #define DP_AUX_HDCP_AN 0x6800C 1394 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) 1395 #define DP_AUX_HDCP_BCAPS 0x68028 1396 # define DP_BCAPS_REPEATER_PRESENT BIT(1) 1397 # define DP_BCAPS_HDCP_CAPABLE BIT(0) 1398 #define DP_AUX_HDCP_BSTATUS 0x68029 1399 # define DP_BSTATUS_REAUTH_REQ BIT(3) 1400 # define DP_BSTATUS_LINK_FAILURE BIT(2) 1401 # define DP_BSTATUS_R0_PRIME_READY BIT(1) 1402 # define DP_BSTATUS_READY BIT(0) 1403 #define DP_AUX_HDCP_BINFO 0x6802A 1404 #define DP_AUX_HDCP_KSV_FIFO 0x6802C 1405 #define DP_AUX_HDCP_AINFO 0x6803B 1406 1407 /* DP HDCP2.2 parameter offsets in DPCD address space */ 1408 #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 1409 #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 1410 #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B 1411 #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 1412 #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D 1413 #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 1414 #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 1415 #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 1416 #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 1417 #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 1418 #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 1419 #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 1420 #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 1421 #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 1422 #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 1423 #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 1424 #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 1425 #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 1426 #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 1427 #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 1428 #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 1429 #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 1430 #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 1431 #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 1432 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 1433 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 1434 1435 /* DP-tunneling */ 1436 #define DP_TUNNELING_OUI 0xe0000 1437 #define DP_TUNNELING_OUI_BYTES 3 1438 1439 #define DP_TUNNELING_DEV_ID 0xe0003 1440 #define DP_TUNNELING_DEV_ID_BYTES 6 1441 1442 #define DP_TUNNELING_HW_REV 0xe0009 1443 #define DP_TUNNELING_HW_REV_MAJOR_SHIFT 4 1444 #define DP_TUNNELING_HW_REV_MAJOR_MASK (0xf << DP_TUNNELING_HW_REV_MAJOR_SHIFT) 1445 #define DP_TUNNELING_HW_REV_MINOR_SHIFT 0 1446 #define DP_TUNNELING_HW_REV_MINOR_MASK (0xf << DP_TUNNELING_HW_REV_MINOR_SHIFT) 1447 1448 #define DP_TUNNELING_SW_REV_MAJOR 0xe000a 1449 #define DP_TUNNELING_SW_REV_MINOR 0xe000b 1450 1451 #define DP_TUNNELING_CAPABILITIES 0xe000d 1452 #define DP_IN_BW_ALLOCATION_MODE_SUPPORT (1 << 7) 1453 #define DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT (1 << 6) 1454 #define DP_TUNNELING_SUPPORT (1 << 0) 1455 1456 #define DP_IN_ADAPTER_INFO 0xe000e 1457 #define DP_IN_ADAPTER_NUMBER_BITS 7 1458 #define DP_IN_ADAPTER_NUMBER_MASK ((1 << DP_IN_ADAPTER_NUMBER_BITS) - 1) 1459 1460 #define DP_USB4_DRIVER_ID 0xe000f 1461 #define DP_USB4_DRIVER_ID_BITS 4 1462 #define DP_USB4_DRIVER_ID_MASK ((1 << DP_USB4_DRIVER_ID_BITS) - 1) 1463 1464 #define DP_USB4_DRIVER_BW_CAPABILITY 0xe0020 1465 #define DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT (1 << 7) 1466 1467 #define DP_IN_ADAPTER_TUNNEL_INFORMATION 0xe0021 1468 #define DP_GROUP_ID_BITS 3 1469 #define DP_GROUP_ID_MASK ((1 << DP_GROUP_ID_BITS) - 1) 1470 1471 #define DP_BW_GRANULARITY 0xe0022 1472 #define DP_BW_GRANULARITY_MASK 0x3 1473 1474 #define DP_ESTIMATED_BW 0xe0023 1475 #define DP_ALLOCATED_BW 0xe0024 1476 1477 #define DP_TUNNELING_STATUS 0xe0025 1478 #define DP_BW_ALLOCATION_CAPABILITY_CHANGED (1 << 3) 1479 #define DP_ESTIMATED_BW_CHANGED (1 << 2) 1480 #define DP_BW_REQUEST_SUCCEEDED (1 << 1) 1481 #define DP_BW_REQUEST_FAILED (1 << 0) 1482 1483 #define DP_TUNNELING_MAX_LINK_RATE 0xe0028 1484 1485 #define DP_TUNNELING_MAX_LANE_COUNT 0xe0029 1486 #define DP_TUNNELING_MAX_LANE_COUNT_MASK 0x1f 1487 1488 #define DP_DPTX_BW_ALLOCATION_MODE_CONTROL 0xe0030 1489 #define DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE (1 << 7) 1490 #define DP_UNMASK_BW_ALLOCATION_IRQ (1 << 6) 1491 1492 #define DP_REQUEST_BW 0xe0031 1493 #define MAX_DP_REQUEST_BW 255 1494 1495 /* LTTPR: Link Training (LT)-tunable PHY Repeaters */ 1496 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ 1497 #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ 1498 #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ 1499 #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ 1500 #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ 1501 #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ 1502 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ 1503 # define DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK 0x7f 1504 # define DP_EXTENDED_WAKE_TIMEOUT_GRANT (1 << 7) 1505 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ 1506 # define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) 1507 /* See DP_128B132B_SUPPORTED_LINK_RATES for values */ 1508 #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ 1509 #define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */ 1510 1511 enum drm_dp_phy { 1512 DP_PHY_DPRX, 1513 1514 DP_PHY_LTTPR1, 1515 DP_PHY_LTTPR2, 1516 DP_PHY_LTTPR3, 1517 DP_PHY_LTTPR4, 1518 DP_PHY_LTTPR5, 1519 DP_PHY_LTTPR6, 1520 DP_PHY_LTTPR7, 1521 DP_PHY_LTTPR8, 1522 1523 DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8, 1524 }; 1525 1526 #define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i)) 1527 1528 #define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */ 1529 #define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */ 1530 #define DP_LTTPR_BASE(dp_phy) \ 1531 (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \ 1532 ((dp_phy) - DP_PHY_LTTPR1)) 1533 1534 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ 1535 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg)) 1536 1537 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ 1538 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ 1539 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1) 1540 1541 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ 1542 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ 1543 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1) 1544 1545 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ 1546 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ 1547 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ 1548 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ 1549 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ 1550 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) 1551 1552 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ 1553 # define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0) 1554 # define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1) 1555 1556 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */ 1557 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ 1558 DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) 1559 /* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */ 1560 1561 #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ 1562 #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \ 1563 DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1) 1564 1565 #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ 1566 1567 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ 1568 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ 1569 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ 1570 #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ 1571 #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ 1572 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ 1573 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ 1574 1575 #define DP_OUI_PHY_REPEATER1 0xf003d /* 1.3 */ 1576 #define DP_OUI_PHY_REPEATER(dp_phy) \ 1577 DP_LTTPR_REG(dp_phy, DP_OUI_PHY_REPEATER1) 1578 1579 #define __DP_FEC1_BASE 0xf0290 /* 1.4 */ 1580 #define __DP_FEC2_BASE 0xf0298 /* 1.4 */ 1581 #define DP_FEC_BASE(dp_phy) \ 1582 (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \ 1583 ((dp_phy) - DP_PHY_LTTPR1))) 1584 1585 #define DP_FEC_REG(dp_phy, fec1_reg) \ 1586 (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg) 1587 1588 #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ 1589 #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ 1590 DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1) 1591 1592 #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */ 1593 #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */ 1594 1595 #define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */ 1596 1597 #define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */ 1598 1599 /* Repeater modes */ 1600 #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ 1601 #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ 1602 1603 /* DP HDCP message start offsets in DPCD address space */ 1604 #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET 1605 #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET 1606 #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 1607 #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 1608 #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET 1609 #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ 1610 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 1611 #define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET 1612 #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET 1613 #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 1614 #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET 1615 #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET 1616 #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 1617 #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET 1618 1619 #define HDCP_2_2_DP_RXSTATUS_LEN 1 1620 #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) 1621 #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) 1622 #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) 1623 #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) 1624 #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) 1625 1626 /* DP 1.2 Sideband message defines */ 1627 /* peer device type - DP 1.2a Table 2-92 */ 1628 #define DP_PEER_DEVICE_NONE 0x0 1629 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 1630 #define DP_PEER_DEVICE_MST_BRANCHING 0x2 1631 #define DP_PEER_DEVICE_SST_SINK 0x3 1632 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 1633 1634 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 1635 #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */ 1636 #define DP_LINK_ADDRESS 0x01 1637 #define DP_CONNECTION_STATUS_NOTIFY 0x02 1638 #define DP_ENUM_PATH_RESOURCES 0x10 1639 #define DP_ALLOCATE_PAYLOAD 0x11 1640 #define DP_QUERY_PAYLOAD 0x12 1641 #define DP_RESOURCE_STATUS_NOTIFY 0x13 1642 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 1643 #define DP_REMOTE_DPCD_READ 0x20 1644 #define DP_REMOTE_DPCD_WRITE 0x21 1645 #define DP_REMOTE_I2C_READ 0x22 1646 #define DP_REMOTE_I2C_WRITE 0x23 1647 #define DP_POWER_UP_PHY 0x24 1648 #define DP_POWER_DOWN_PHY 0x25 1649 #define DP_SINK_EVENT_NOTIFY 0x30 1650 #define DP_QUERY_STREAM_ENC_STATUS 0x38 1651 #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 1652 #define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 1653 #define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2 1654 1655 /* DP 1.2 MST sideband reply types */ 1656 #define DP_SIDEBAND_REPLY_ACK 0x00 1657 #define DP_SIDEBAND_REPLY_NAK 0x01 1658 1659 /* DP 1.2 MST sideband nak reasons - table 2.84 */ 1660 #define DP_NAK_WRITE_FAILURE 0x01 1661 #define DP_NAK_INVALID_READ 0x02 1662 #define DP_NAK_CRC_FAILURE 0x03 1663 #define DP_NAK_BAD_PARAM 0x04 1664 #define DP_NAK_DEFER 0x05 1665 #define DP_NAK_LINK_FAILURE 0x06 1666 #define DP_NAK_NO_RESOURCES 0x07 1667 #define DP_NAK_DPCD_FAIL 0x08 1668 #define DP_NAK_I2C_NAK 0x09 1669 #define DP_NAK_ALLOCATE_FAIL 0x0a 1670 1671 #define MODE_I2C_START 1 1672 #define MODE_I2C_WRITE 2 1673 #define MODE_I2C_READ 4 1674 #define MODE_I2C_STOP 8 1675 1676 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ 1677 #define DP_MST_PHYSICAL_PORT_0 0 1678 #define DP_MST_LOGICAL_PORT_0 8 1679 1680 #define DP_LINK_CONSTANT_N_VALUE 0x8000 1681 #define DP_LINK_STATUS_SIZE 6 1682 1683 #define DP_BRANCH_OUI_HEADER_SIZE 0xc 1684 #define DP_RECEIVER_CAP_SIZE 0xf 1685 #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */ 1686 #define EDP_PSR_RECEIVER_CAP_SIZE 2 1687 #define EDP_DISPLAY_CTL_CAP_SIZE 5 1688 #define DP_LTTPR_COMMON_CAP_SIZE 8 1689 #define DP_LTTPR_PHY_CAP_SIZE 3 1690 1691 #define DP_SDP_AUDIO_TIMESTAMP 0x01 1692 #define DP_SDP_AUDIO_STREAM 0x02 1693 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ 1694 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ 1695 #define DP_SDP_ISRC 0x06 /* DP 1.2 */ 1696 #define DP_SDP_VSC 0x07 /* DP 1.2 */ 1697 #define DP_SDP_ADAPTIVE_SYNC 0x22 /* DP 1.4 */ 1698 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ 1699 #define DP_SDP_PPS 0x10 /* DP 1.4 */ 1700 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ 1701 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ 1702 1703 /* 0x80+ CEA-861 infoframe types */ 1704 1705 #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b 1706 1707 /** 1708 * struct dp_sdp_header - DP secondary data packet header 1709 * @HB0: Secondary Data Packet ID 1710 * @HB1: Secondary Data Packet Type 1711 * @HB2: Secondary Data Packet Specific header, Byte 0 1712 * @HB3: Secondary Data packet Specific header, Byte 1 1713 */ 1714 struct dp_sdp_header { 1715 u8 HB0; 1716 u8 HB1; 1717 u8 HB2; 1718 u8 HB3; 1719 } __packed; 1720 1721 #define EDP_SDP_HEADER_REVISION_MASK 0x1F 1722 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F 1723 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F 1724 1725 /** 1726 * struct dp_sdp - DP secondary data packet 1727 * @sdp_header: DP secondary data packet header 1728 * @db: DP secondaray data packet data blocks 1729 * VSC SDP Payload for PSR 1730 * db[0]: Stereo Interface 1731 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid 1732 * db[2]: CRC value bits 7:0 of the R or Cr component 1733 * db[3]: CRC value bits 15:8 of the R or Cr component 1734 * db[4]: CRC value bits 7:0 of the G or Y component 1735 * db[5]: CRC value bits 15:8 of the G or Y component 1736 * db[6]: CRC value bits 7:0 of the B or Cb component 1737 * db[7]: CRC value bits 15:8 of the B or Cb component 1738 * db[8] - db[31]: Reserved 1739 * VSC SDP Payload for Pixel Encoding/Colorimetry Format 1740 * db[0] - db[15]: Reserved 1741 * db[16]: Pixel Encoding and Colorimetry Formats 1742 * db[17]: Dynamic Range and Component Bit Depth 1743 * db[18]: Content Type 1744 * db[19] - db[31]: Reserved 1745 */ 1746 struct dp_sdp { 1747 struct dp_sdp_header sdp_header; 1748 u8 db[32]; 1749 } __packed; 1750 1751 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) 1752 #define EDP_VSC_PSR_UPDATE_RFB (1<<1) 1753 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) 1754 1755 /** 1756 * enum dp_pixelformat - drm DP Pixel encoding formats 1757 * 1758 * This enum is used to indicate DP VSC SDP Pixel encoding formats. 1759 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through 1760 * DB18] 1761 * 1762 * @DP_PIXELFORMAT_RGB: RGB pixel encoding format 1763 * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format 1764 * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format 1765 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format 1766 * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format 1767 * @DP_PIXELFORMAT_RAW: RAW pixel encoding format 1768 * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format 1769 */ 1770 enum dp_pixelformat { 1771 DP_PIXELFORMAT_RGB = 0, 1772 DP_PIXELFORMAT_YUV444 = 0x1, 1773 DP_PIXELFORMAT_YUV422 = 0x2, 1774 DP_PIXELFORMAT_YUV420 = 0x3, 1775 DP_PIXELFORMAT_Y_ONLY = 0x4, 1776 DP_PIXELFORMAT_RAW = 0x5, 1777 DP_PIXELFORMAT_RESERVED = 0x6, 1778 }; 1779 1780 /** 1781 * enum dp_colorimetry - drm DP Colorimetry formats 1782 * 1783 * This enum is used to indicate DP VSC SDP Colorimetry formats. 1784 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through 1785 * DB18] and a name of enum member follows enum drm_colorimetry definition. 1786 * 1787 * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or 1788 * ITU-R BT.601 colorimetry format 1789 * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format 1790 * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format 1791 * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point 1792 * (scRGB (IEC 61966-2-2)) colorimetry format 1793 * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format 1794 * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format 1795 * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format 1796 * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format 1797 * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format 1798 * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format 1799 * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format 1800 * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format 1801 * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format 1802 * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format 1803 */ 1804 enum dp_colorimetry { 1805 DP_COLORIMETRY_DEFAULT = 0, 1806 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1, 1807 DP_COLORIMETRY_BT709_YCC = 0x1, 1808 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2, 1809 DP_COLORIMETRY_XVYCC_601 = 0x2, 1810 DP_COLORIMETRY_OPRGB = 0x3, 1811 DP_COLORIMETRY_XVYCC_709 = 0x3, 1812 DP_COLORIMETRY_DCI_P3_RGB = 0x4, 1813 DP_COLORIMETRY_SYCC_601 = 0x4, 1814 DP_COLORIMETRY_RGB_CUSTOM = 0x5, 1815 DP_COLORIMETRY_OPYCC_601 = 0x5, 1816 DP_COLORIMETRY_BT2020_RGB = 0x6, 1817 DP_COLORIMETRY_BT2020_CYCC = 0x6, 1818 DP_COLORIMETRY_BT2020_YCC = 0x7, 1819 }; 1820 1821 /** 1822 * enum dp_dynamic_range - drm DP Dynamic Range 1823 * 1824 * This enum is used to indicate DP VSC SDP Dynamic Range. 1825 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through 1826 * DB18] 1827 * 1828 * @DP_DYNAMIC_RANGE_VESA: VESA range 1829 * @DP_DYNAMIC_RANGE_CTA: CTA range 1830 */ 1831 enum dp_dynamic_range { 1832 DP_DYNAMIC_RANGE_VESA = 0, 1833 DP_DYNAMIC_RANGE_CTA = 1, 1834 }; 1835 1836 /** 1837 * enum dp_content_type - drm DP Content Type 1838 * 1839 * This enum is used to indicate DP VSC SDP Content Types. 1840 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through 1841 * DB18] 1842 * CTA-861-G defines content types and expected processing by a sink device 1843 * 1844 * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type 1845 * @DP_CONTENT_TYPE_GRAPHICS: Graphics type 1846 * @DP_CONTENT_TYPE_PHOTO: Photo type 1847 * @DP_CONTENT_TYPE_VIDEO: Video type 1848 * @DP_CONTENT_TYPE_GAME: Game type 1849 */ 1850 enum dp_content_type { 1851 DP_CONTENT_TYPE_NOT_DEFINED = 0x00, 1852 DP_CONTENT_TYPE_GRAPHICS = 0x01, 1853 DP_CONTENT_TYPE_PHOTO = 0x02, 1854 DP_CONTENT_TYPE_VIDEO = 0x03, 1855 DP_CONTENT_TYPE_GAME = 0x04, 1856 }; 1857 1858 enum operation_mode { 1859 DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00, 1860 DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01, 1861 DP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02, 1862 DP_AS_SDP_FAVT_TRR_REACHED = 0x03 1863 }; 1864 1865 #endif /* _DRM_DP_H_ */ 1866