1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 */
6
7 #include <linux/ethtool.h>
8 #include <linux/kernel.h>
9 #include <linux/mii.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/delay.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/bitfield.h>
17 #include <linux/nvmem-consumer.h>
18
19 #include <dt-bindings/net/ti-dp83867.h>
20
21 #define DP83867_PHY_ID 0x2000a231
22 #define DP83867_DEVADDR 0x1f
23
24 #define MII_DP83867_PHYCTRL 0x10
25 #define MII_DP83867_PHYSTS 0x11
26 #define MII_DP83867_MICR 0x12
27 #define MII_DP83867_ISR 0x13
28 #define DP83867_CFG2 0x14
29 #define DP83867_LEDCR1 0x18
30 #define DP83867_LEDCR2 0x19
31 #define DP83867_CFG3 0x1e
32 #define DP83867_CTRL 0x1f
33
34 /* Extended Registers */
35 #define DP83867_FLD_THR_CFG 0x002e
36 #define DP83867_CFG4 0x0031
37 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
38 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
39 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
40 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
41 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
42
43 #define DP83867_RGMIICTL 0x0032
44 #define DP83867_STRAP_STS1 0x006E
45 #define DP83867_STRAP_STS2 0x006f
46 #define DP83867_RGMIIDCTL 0x0086
47 #define DP83867_DSP_FFE_CFG 0x012c
48 #define DP83867_RXFCFG 0x0134
49 #define DP83867_RXFPMD1 0x0136
50 #define DP83867_RXFPMD2 0x0137
51 #define DP83867_RXFPMD3 0x0138
52 #define DP83867_RXFSOP1 0x0139
53 #define DP83867_RXFSOP2 0x013A
54 #define DP83867_RXFSOP3 0x013B
55 #define DP83867_IO_MUX_CFG 0x0170
56 #define DP83867_SGMIICTL 0x00D3
57 #define DP83867_10M_SGMII_CFG 0x016F
58 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
59
60 #define DP83867_SW_RESET BIT(15)
61 #define DP83867_SW_RESTART BIT(14)
62
63 /* MICR Interrupt bits */
64 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
65 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
66 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
67 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
68 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
69 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
70 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
71 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
72 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
73 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
74 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
75 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
76
77 /* RGMIICTL bits */
78 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
79 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
80
81 /* SGMIICTL bits */
82 #define DP83867_SGMII_TYPE BIT(14)
83
84 /* RXFCFG bits*/
85 #define DP83867_WOL_MAGIC_EN BIT(0)
86 #define DP83867_WOL_BCAST_EN BIT(2)
87 #define DP83867_WOL_UCAST_EN BIT(4)
88 #define DP83867_WOL_SEC_EN BIT(5)
89 #define DP83867_WOL_ENH_MAC BIT(7)
90
91 /* STRAP_STS1 bits */
92 #define DP83867_STRAP_STS1_RESERVED BIT(11)
93
94 /* STRAP_STS2 bits */
95 #define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
96
97 /* PHY CTRL bits */
98 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
99 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
100 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
101 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
102 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
103 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
104 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
105
106 /* RGMIIDCTL bits */
107 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
108 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
109 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
110 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
111
112 /* IO_MUX_CFG bits */
113 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
114 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
115 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
116 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
117 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
118 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
119
120 /* PHY STS bits */
121 #define DP83867_PHYSTS_1000 BIT(15)
122 #define DP83867_PHYSTS_100 BIT(14)
123 #define DP83867_PHYSTS_DUPLEX BIT(13)
124 #define DP83867_PHYSTS_LINK BIT(10)
125
126 /* CFG2 bits */
127 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
128 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
129 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0
130 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1
131 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2
132 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3
133 #define DP83867_DOWNSHIFT_1_COUNT 1
134 #define DP83867_DOWNSHIFT_2_COUNT 2
135 #define DP83867_DOWNSHIFT_4_COUNT 4
136 #define DP83867_DOWNSHIFT_8_COUNT 8
137 #define DP83867_SGMII_AUTONEG_EN BIT(7)
138
139 /* CFG3 bits */
140 #define DP83867_CFG3_INT_OE BIT(7)
141 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
142
143 /* CFG4 bits */
144 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
145
146 /* FLD_THR_CFG */
147 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
148
149 #define DP83867_LED_COUNT 4
150
151 /* LED_DRV bits */
152 #define DP83867_LED_DRV_EN(x) BIT((x) * 4)
153 #define DP83867_LED_DRV_VAL(x) BIT((x) * 4 + 1)
154 #define DP83867_LED_POLARITY(x) BIT((x) * 4 + 2)
155
156 #define DP83867_LED_FN(idx, val) (((val) & 0xf) << ((idx) * 4))
157 #define DP83867_LED_FN_MASK(idx) (0xf << ((idx) * 4))
158 #define DP83867_LED_FN_RX_ERR 0xe /* Receive Error */
159 #define DP83867_LED_FN_RX_TX_ERR 0xd /* Receive Error or Transmit Error */
160 #define DP83867_LED_FN_LINK_RX_TX 0xb /* Link established, blink for rx or tx activity */
161 #define DP83867_LED_FN_FULL_DUPLEX 0xa /* Full duplex */
162 #define DP83867_LED_FN_LINK_100_1000_BT 0x9 /* 100/1000BT link established */
163 #define DP83867_LED_FN_LINK_10_100_BT 0x8 /* 10/100BT link established */
164 #define DP83867_LED_FN_LINK_10_BT 0x7 /* 10BT link established */
165 #define DP83867_LED_FN_LINK_100_BTX 0x6 /* 100 BTX link established */
166 #define DP83867_LED_FN_LINK_1000_BT 0x5 /* 1000 BT link established */
167 #define DP83867_LED_FN_COLLISION 0x4 /* Collision detected */
168 #define DP83867_LED_FN_RX 0x3 /* Receive activity */
169 #define DP83867_LED_FN_TX 0x2 /* Transmit activity */
170 #define DP83867_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */
171 #define DP83867_LED_FN_LINK 0x0 /* Link established */
172
173 enum {
174 DP83867_PORT_MIRROING_KEEP,
175 DP83867_PORT_MIRROING_EN,
176 DP83867_PORT_MIRROING_DIS,
177 };
178
179 struct dp83867_private {
180 u32 rx_id_delay;
181 u32 tx_id_delay;
182 u32 tx_fifo_depth;
183 u32 rx_fifo_depth;
184 int io_impedance;
185 int port_mirroring;
186 bool rxctrl_strap_quirk;
187 bool set_clk_output;
188 u32 clk_output_sel;
189 bool sgmii_ref_clk_en;
190 };
191
dp83867_ack_interrupt(struct phy_device * phydev)192 static int dp83867_ack_interrupt(struct phy_device *phydev)
193 {
194 int err = phy_read(phydev, MII_DP83867_ISR);
195
196 if (err < 0)
197 return err;
198
199 return 0;
200 }
201
dp83867_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)202 static int dp83867_set_wol(struct phy_device *phydev,
203 struct ethtool_wolinfo *wol)
204 {
205 struct net_device *ndev = phydev->attached_dev;
206 u16 val_rxcfg, val_micr;
207 const u8 *mac;
208
209 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
210 val_micr = phy_read(phydev, MII_DP83867_MICR);
211
212 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
213 WAKE_BCAST)) {
214 val_rxcfg |= DP83867_WOL_ENH_MAC;
215 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
216
217 if (wol->wolopts & WAKE_MAGIC) {
218 mac = (const u8 *)ndev->dev_addr;
219
220 if (!is_valid_ether_addr(mac))
221 return -EINVAL;
222
223 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
224 (mac[1] << 8 | mac[0]));
225 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
226 (mac[3] << 8 | mac[2]));
227 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
228 (mac[5] << 8 | mac[4]));
229
230 val_rxcfg |= DP83867_WOL_MAGIC_EN;
231 } else {
232 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
233 }
234
235 if (wol->wolopts & WAKE_MAGICSECURE) {
236 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
237 (wol->sopass[1] << 8) | wol->sopass[0]);
238 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
239 (wol->sopass[3] << 8) | wol->sopass[2]);
240 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
241 (wol->sopass[5] << 8) | wol->sopass[4]);
242
243 val_rxcfg |= DP83867_WOL_SEC_EN;
244 } else {
245 val_rxcfg &= ~DP83867_WOL_SEC_EN;
246 }
247
248 if (wol->wolopts & WAKE_UCAST)
249 val_rxcfg |= DP83867_WOL_UCAST_EN;
250 else
251 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
252
253 if (wol->wolopts & WAKE_BCAST)
254 val_rxcfg |= DP83867_WOL_BCAST_EN;
255 else
256 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
257 } else {
258 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
259 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
260 }
261
262 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
263 phy_write(phydev, MII_DP83867_MICR, val_micr);
264
265 return 0;
266 }
267
dp83867_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)268 static void dp83867_get_wol(struct phy_device *phydev,
269 struct ethtool_wolinfo *wol)
270 {
271 u16 value, sopass_val;
272
273 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
274 WAKE_MAGICSECURE);
275 wol->wolopts = 0;
276
277 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
278
279 if (value & DP83867_WOL_UCAST_EN)
280 wol->wolopts |= WAKE_UCAST;
281
282 if (value & DP83867_WOL_BCAST_EN)
283 wol->wolopts |= WAKE_BCAST;
284
285 if (value & DP83867_WOL_MAGIC_EN)
286 wol->wolopts |= WAKE_MAGIC;
287
288 if (value & DP83867_WOL_SEC_EN) {
289 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
290 DP83867_RXFSOP1);
291 wol->sopass[0] = (sopass_val & 0xff);
292 wol->sopass[1] = (sopass_val >> 8);
293
294 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
295 DP83867_RXFSOP2);
296 wol->sopass[2] = (sopass_val & 0xff);
297 wol->sopass[3] = (sopass_val >> 8);
298
299 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
300 DP83867_RXFSOP3);
301 wol->sopass[4] = (sopass_val & 0xff);
302 wol->sopass[5] = (sopass_val >> 8);
303
304 wol->wolopts |= WAKE_MAGICSECURE;
305 }
306
307 if (!(value & DP83867_WOL_ENH_MAC))
308 wol->wolopts = 0;
309 }
310
dp83867_config_intr(struct phy_device * phydev)311 static int dp83867_config_intr(struct phy_device *phydev)
312 {
313 int micr_status, err;
314
315 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
316 err = dp83867_ack_interrupt(phydev);
317 if (err)
318 return err;
319
320 micr_status = phy_read(phydev, MII_DP83867_MICR);
321 if (micr_status < 0)
322 return micr_status;
323
324 micr_status |=
325 (MII_DP83867_MICR_AN_ERR_INT_EN |
326 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
327 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
328 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
329 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
330 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
331
332 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
333 } else {
334 micr_status = 0x0;
335 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
336 if (err)
337 return err;
338
339 err = dp83867_ack_interrupt(phydev);
340 }
341
342 return err;
343 }
344
dp83867_handle_interrupt(struct phy_device * phydev)345 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
346 {
347 int irq_status, irq_enabled;
348
349 irq_status = phy_read(phydev, MII_DP83867_ISR);
350 if (irq_status < 0) {
351 phy_error(phydev);
352 return IRQ_NONE;
353 }
354
355 irq_enabled = phy_read(phydev, MII_DP83867_MICR);
356 if (irq_enabled < 0) {
357 phy_error(phydev);
358 return IRQ_NONE;
359 }
360
361 if (!(irq_status & irq_enabled))
362 return IRQ_NONE;
363
364 phy_trigger_machine(phydev);
365
366 return IRQ_HANDLED;
367 }
368
dp83867_read_status(struct phy_device * phydev)369 static int dp83867_read_status(struct phy_device *phydev)
370 {
371 int status = phy_read(phydev, MII_DP83867_PHYSTS);
372 int ret;
373
374 ret = genphy_read_status(phydev);
375 if (ret)
376 return ret;
377
378 if (status < 0)
379 return status;
380
381 if (status & DP83867_PHYSTS_DUPLEX)
382 phydev->duplex = DUPLEX_FULL;
383 else
384 phydev->duplex = DUPLEX_HALF;
385
386 if (status & DP83867_PHYSTS_1000)
387 phydev->speed = SPEED_1000;
388 else if (status & DP83867_PHYSTS_100)
389 phydev->speed = SPEED_100;
390 else
391 phydev->speed = SPEED_10;
392
393 return 0;
394 }
395
dp83867_get_downshift(struct phy_device * phydev,u8 * data)396 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
397 {
398 int val, cnt, enable, count;
399
400 val = phy_read(phydev, DP83867_CFG2);
401 if (val < 0)
402 return val;
403
404 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
405 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
406
407 switch (cnt) {
408 case DP83867_DOWNSHIFT_1_COUNT_VAL:
409 count = DP83867_DOWNSHIFT_1_COUNT;
410 break;
411 case DP83867_DOWNSHIFT_2_COUNT_VAL:
412 count = DP83867_DOWNSHIFT_2_COUNT;
413 break;
414 case DP83867_DOWNSHIFT_4_COUNT_VAL:
415 count = DP83867_DOWNSHIFT_4_COUNT;
416 break;
417 case DP83867_DOWNSHIFT_8_COUNT_VAL:
418 count = DP83867_DOWNSHIFT_8_COUNT;
419 break;
420 default:
421 return -EINVAL;
422 }
423
424 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
425
426 return 0;
427 }
428
dp83867_set_downshift(struct phy_device * phydev,u8 cnt)429 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
430 {
431 int val, count;
432
433 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
434 return -E2BIG;
435
436 if (!cnt)
437 return phy_clear_bits(phydev, DP83867_CFG2,
438 DP83867_DOWNSHIFT_EN);
439
440 switch (cnt) {
441 case DP83867_DOWNSHIFT_1_COUNT:
442 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
443 break;
444 case DP83867_DOWNSHIFT_2_COUNT:
445 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
446 break;
447 case DP83867_DOWNSHIFT_4_COUNT:
448 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
449 break;
450 case DP83867_DOWNSHIFT_8_COUNT:
451 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
452 break;
453 default:
454 phydev_err(phydev,
455 "Downshift count must be 1, 2, 4 or 8\n");
456 return -EINVAL;
457 }
458
459 val = DP83867_DOWNSHIFT_EN;
460 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
461
462 return phy_modify(phydev, DP83867_CFG2,
463 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
464 val);
465 }
466
dp83867_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)467 static int dp83867_get_tunable(struct phy_device *phydev,
468 struct ethtool_tunable *tuna, void *data)
469 {
470 switch (tuna->id) {
471 case ETHTOOL_PHY_DOWNSHIFT:
472 return dp83867_get_downshift(phydev, data);
473 default:
474 return -EOPNOTSUPP;
475 }
476 }
477
dp83867_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)478 static int dp83867_set_tunable(struct phy_device *phydev,
479 struct ethtool_tunable *tuna, const void *data)
480 {
481 switch (tuna->id) {
482 case ETHTOOL_PHY_DOWNSHIFT:
483 return dp83867_set_downshift(phydev, *(const u8 *)data);
484 default:
485 return -EOPNOTSUPP;
486 }
487 }
488
dp83867_config_port_mirroring(struct phy_device * phydev)489 static int dp83867_config_port_mirroring(struct phy_device *phydev)
490 {
491 struct dp83867_private *dp83867 = phydev->priv;
492
493 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
494 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
495 DP83867_CFG4_PORT_MIRROR_EN);
496 else
497 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
498 DP83867_CFG4_PORT_MIRROR_EN);
499 return 0;
500 }
501
502 #if IS_ENABLED(CONFIG_OF_MDIO)
dp83867_of_init_io_impedance(struct phy_device * phydev)503 static int dp83867_of_init_io_impedance(struct phy_device *phydev)
504 {
505 struct dp83867_private *dp83867 = phydev->priv;
506 struct device *dev = &phydev->mdio.dev;
507 struct device_node *of_node = dev->of_node;
508 struct nvmem_cell *cell;
509 u8 *buf, val;
510 int ret;
511
512 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl");
513 if (IS_ERR(cell)) {
514 ret = PTR_ERR(cell);
515 if (ret != -ENOENT && ret != -EOPNOTSUPP)
516 return phydev_err_probe(phydev, ret,
517 "failed to get nvmem cell io_impedance_ctrl\n");
518
519 /* If no nvmem cell, check for the boolean properties. */
520 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
521 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
522 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
523 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
524 else
525 dp83867->io_impedance = -1; /* leave at default */
526
527 return 0;
528 }
529
530 buf = nvmem_cell_read(cell, NULL);
531 nvmem_cell_put(cell);
532
533 if (IS_ERR(buf))
534 return PTR_ERR(buf);
535
536 val = *buf;
537 kfree(buf);
538
539 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) {
540 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");
541 return -ERANGE;
542 }
543 dp83867->io_impedance = val;
544
545 return 0;
546 }
547
dp83867_of_init(struct phy_device * phydev)548 static int dp83867_of_init(struct phy_device *phydev)
549 {
550 struct dp83867_private *dp83867 = phydev->priv;
551 struct device *dev = &phydev->mdio.dev;
552 struct device_node *of_node = dev->of_node;
553 int ret;
554
555 if (!of_node)
556 return -ENODEV;
557
558 /* Optional configuration */
559 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
560 &dp83867->clk_output_sel);
561 /* If not set, keep default */
562 if (!ret) {
563 dp83867->set_clk_output = true;
564 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
565 * DP83867_CLK_O_SEL_OFF.
566 */
567 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
568 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
569 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
570 dp83867->clk_output_sel);
571 return -EINVAL;
572 }
573 }
574
575 ret = dp83867_of_init_io_impedance(phydev);
576 if (ret)
577 return ret;
578
579 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
580 "ti,dp83867-rxctrl-strap-quirk");
581
582 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
583 "ti,sgmii-ref-clock-output-enable");
584
585 dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_00_NS;
586 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
587 &dp83867->rx_id_delay);
588 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
589 phydev_err(phydev,
590 "ti,rx-internal-delay value of %u out of range\n",
591 dp83867->rx_id_delay);
592 return -EINVAL;
593 }
594
595 dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_00_NS;
596 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
597 &dp83867->tx_id_delay);
598 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
599 phydev_err(phydev,
600 "ti,tx-internal-delay value of %u out of range\n",
601 dp83867->tx_id_delay);
602 return -EINVAL;
603 }
604
605 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
606 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
607
608 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
609 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
610
611 ret = of_property_read_u32(of_node, "ti,fifo-depth",
612 &dp83867->tx_fifo_depth);
613 if (ret) {
614 ret = of_property_read_u32(of_node, "tx-fifo-depth",
615 &dp83867->tx_fifo_depth);
616 if (ret)
617 dp83867->tx_fifo_depth =
618 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
619 }
620
621 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
622 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
623 dp83867->tx_fifo_depth);
624 return -EINVAL;
625 }
626
627 ret = of_property_read_u32(of_node, "rx-fifo-depth",
628 &dp83867->rx_fifo_depth);
629 if (ret)
630 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
631
632 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
633 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
634 dp83867->rx_fifo_depth);
635 return -EINVAL;
636 }
637
638 return 0;
639 }
640 #else
dp83867_of_init(struct phy_device * phydev)641 static int dp83867_of_init(struct phy_device *phydev)
642 {
643 struct dp83867_private *dp83867 = phydev->priv;
644 u16 delay;
645
646 /* For non-OF device, the RX and TX ID values are either strapped
647 * or take from default value. So, we init RX & TX ID values here
648 * so that the RGMIIDCTL is configured correctly later in
649 * dp83867_config_init();
650 */
651 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
652 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
653 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
654 DP83867_RGMII_TX_CLK_DELAY_MAX;
655
656 /* Per datasheet, IO impedance is default to 50-ohm, so we set the
657 * same here or else the default '0' means highest IO impedance
658 * which is wrong.
659 */
660 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
661
662 /* For non-OF device, the RX and TX FIFO depths are taken from
663 * default value. So, we init RX & TX FIFO depths here
664 * so that it is configured correctly later in dp83867_config_init();
665 */
666 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
667 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
668
669 return 0;
670 }
671 #endif /* CONFIG_OF_MDIO */
672
dp83867_suspend(struct phy_device * phydev)673 static int dp83867_suspend(struct phy_device *phydev)
674 {
675 /* Disable PHY Interrupts */
676 if (phy_interrupt_is_valid(phydev)) {
677 phydev->interrupts = PHY_INTERRUPT_DISABLED;
678 dp83867_config_intr(phydev);
679 }
680
681 return genphy_suspend(phydev);
682 }
683
dp83867_resume(struct phy_device * phydev)684 static int dp83867_resume(struct phy_device *phydev)
685 {
686 /* Enable PHY Interrupts */
687 if (phy_interrupt_is_valid(phydev)) {
688 phydev->interrupts = PHY_INTERRUPT_ENABLED;
689 dp83867_config_intr(phydev);
690 }
691
692 genphy_resume(phydev);
693
694 return 0;
695 }
696
dp83867_probe(struct phy_device * phydev)697 static int dp83867_probe(struct phy_device *phydev)
698 {
699 struct dp83867_private *dp83867;
700
701 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
702 GFP_KERNEL);
703 if (!dp83867)
704 return -ENOMEM;
705
706 phydev->priv = dp83867;
707
708 return dp83867_of_init(phydev);
709 }
710
dp83867_config_init(struct phy_device * phydev)711 static int dp83867_config_init(struct phy_device *phydev)
712 {
713 struct dp83867_private *dp83867 = phydev->priv;
714 int ret, val, bs;
715
716 /* Force speed optimization for the PHY even if it strapped */
717 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
718 DP83867_DOWNSHIFT_EN);
719 if (ret)
720 return ret;
721
722 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
723 if (dp83867->rxctrl_strap_quirk)
724 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
725 BIT(7));
726
727 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
728 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
729 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
730 * be set to 0x2. This may causes the PHY link to be unstable -
731 * the default value 0x1 need to be restored.
732 */
733 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
734 DP83867_FLD_THR_CFG,
735 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
736 0x1);
737 if (ret)
738 return ret;
739 }
740
741 if (phy_interface_is_rgmii(phydev) ||
742 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
743 val = phy_read(phydev, MII_DP83867_PHYCTRL);
744 if (val < 0)
745 return val;
746
747 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
748 val |= (dp83867->tx_fifo_depth <<
749 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
750
751 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
752 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
753 val |= (dp83867->rx_fifo_depth <<
754 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
755 }
756
757 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
758 if (ret)
759 return ret;
760 }
761
762 if (phy_interface_is_rgmii(phydev)) {
763 val = phy_read(phydev, MII_DP83867_PHYCTRL);
764 if (val < 0)
765 return val;
766
767 /* The code below checks if "port mirroring" N/A MODE4 has been
768 * enabled during power on bootstrap.
769 *
770 * Such N/A mode enabled by mistake can put PHY IC in some
771 * internal testing mode and disable RGMII transmission.
772 *
773 * In this particular case one needs to check STRAP_STS1
774 * register's bit 11 (marked as RESERVED).
775 */
776
777 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
778 if (bs & DP83867_STRAP_STS1_RESERVED)
779 val &= ~DP83867_PHYCR_RESERVED_MASK;
780
781 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
782 if (ret)
783 return ret;
784
785 /* Set up RGMII delays */
786 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
787
788 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
789 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
790 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
791
792 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
793 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
794
795 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
796 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
797
798 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
799
800 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
801 dp83867->rx_id_delay |
802 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
803 }
804
805 /* If specified, set io impedance */
806 if (dp83867->io_impedance >= 0)
807 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
808 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
809 dp83867->io_impedance);
810
811 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
812 /* For support SPEED_10 in SGMII mode
813 * DP83867_10M_SGMII_RATE_ADAPT bit
814 * has to be cleared by software. That
815 * does not affect SPEED_100 and
816 * SPEED_1000.
817 */
818 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
819 DP83867_10M_SGMII_CFG,
820 DP83867_10M_SGMII_RATE_ADAPT_MASK,
821 0);
822 if (ret)
823 return ret;
824
825 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
826 * are 01). That is not enough to finalize autoneg on some
827 * devices. Increase this timer duration to maximum 16ms.
828 */
829 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
830 DP83867_CFG4,
831 DP83867_CFG4_SGMII_ANEG_MASK,
832 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
833
834 if (ret)
835 return ret;
836
837 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
838 /* SGMII type is set to 4-wire mode by default.
839 * If we place appropriate property in dts (see above)
840 * switch on 6-wire mode.
841 */
842 if (dp83867->sgmii_ref_clk_en)
843 val |= DP83867_SGMII_TYPE;
844 else
845 val &= ~DP83867_SGMII_TYPE;
846 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
847
848 /* This is a SW workaround for link instability if RX_CTRL is
849 * not strapped to mode 3 or 4 in HW. This is required for SGMII
850 * in addition to clearing bit 7, handled above.
851 */
852 if (dp83867->rxctrl_strap_quirk)
853 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
854 BIT(8));
855 }
856
857 val = phy_read(phydev, DP83867_CFG3);
858 /* Enable Interrupt output INT_OE in CFG3 register */
859 if (phy_interrupt_is_valid(phydev))
860 val |= DP83867_CFG3_INT_OE;
861
862 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
863 phy_write(phydev, DP83867_CFG3, val);
864
865 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
866 dp83867_config_port_mirroring(phydev);
867
868 /* Clock output selection if muxing property is set */
869 if (dp83867->set_clk_output) {
870 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
871
872 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
873 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
874 } else {
875 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
876 val = dp83867->clk_output_sel <<
877 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
878 }
879
880 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
881 mask, val);
882 }
883
884 return 0;
885 }
886
dp83867_phy_reset(struct phy_device * phydev)887 static int dp83867_phy_reset(struct phy_device *phydev)
888 {
889 int err;
890
891 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
892 if (err < 0)
893 return err;
894
895 usleep_range(10, 20);
896
897 err = phy_modify(phydev, MII_DP83867_PHYCTRL,
898 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
899 if (err < 0)
900 return err;
901
902 /* Configure the DSP Feedforward Equalizer Configuration register to
903 * improve short cable (< 1 meter) performance. This will not affect
904 * long cable performance.
905 */
906 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,
907 0x0e81);
908 if (err < 0)
909 return err;
910
911 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
912 if (err < 0)
913 return err;
914
915 usleep_range(10, 20);
916
917 return 0;
918 }
919
dp83867_link_change_notify(struct phy_device * phydev)920 static void dp83867_link_change_notify(struct phy_device *phydev)
921 {
922 /* There is a limitation in DP83867 PHY device where SGMII AN is
923 * only triggered once after the device is booted up. Even after the
924 * PHY TPI is down and up again, SGMII AN is not triggered and
925 * hence no new in-band message from PHY to MAC side SGMII.
926 * This could cause an issue during power up, when PHY is up prior
927 * to MAC. At this condition, once MAC side SGMII is up, MAC side
928 * SGMII wouldn`t receive new in-band message from TI PHY with
929 * correct link status, speed and duplex info.
930 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
931 * whenever there is a link change.
932 */
933 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
934 int val = 0;
935
936 val = phy_clear_bits(phydev, DP83867_CFG2,
937 DP83867_SGMII_AUTONEG_EN);
938 if (val < 0)
939 return;
940
941 phy_set_bits(phydev, DP83867_CFG2,
942 DP83867_SGMII_AUTONEG_EN);
943 }
944 }
945
dp83867_loopback(struct phy_device * phydev,bool enable,int speed)946 static int dp83867_loopback(struct phy_device *phydev, bool enable, int speed)
947 {
948 if (enable && speed)
949 return -EOPNOTSUPP;
950
951 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
952 enable ? BMCR_LOOPBACK : 0);
953 }
954
955 static int
dp83867_led_brightness_set(struct phy_device * phydev,u8 index,enum led_brightness brightness)956 dp83867_led_brightness_set(struct phy_device *phydev,
957 u8 index, enum led_brightness brightness)
958 {
959 u32 val;
960
961 if (index >= DP83867_LED_COUNT)
962 return -EINVAL;
963
964 /* DRV_EN==1: output is DRV_VAL */
965 val = DP83867_LED_DRV_EN(index);
966
967 if (brightness)
968 val |= DP83867_LED_DRV_VAL(index);
969
970 return phy_modify(phydev, DP83867_LEDCR2,
971 DP83867_LED_DRV_VAL(index) |
972 DP83867_LED_DRV_EN(index),
973 val);
974 }
975
dp83867_led_mode(u8 index,unsigned long rules)976 static int dp83867_led_mode(u8 index, unsigned long rules)
977 {
978 if (index >= DP83867_LED_COUNT)
979 return -EINVAL;
980
981 switch (rules) {
982 case BIT(TRIGGER_NETDEV_LINK):
983 return DP83867_LED_FN_LINK;
984 case BIT(TRIGGER_NETDEV_LINK_10):
985 return DP83867_LED_FN_LINK_10_BT;
986 case BIT(TRIGGER_NETDEV_LINK_100):
987 return DP83867_LED_FN_LINK_100_BTX;
988 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
989 return DP83867_LED_FN_FULL_DUPLEX;
990 case BIT(TRIGGER_NETDEV_TX):
991 return DP83867_LED_FN_TX;
992 case BIT(TRIGGER_NETDEV_RX):
993 return DP83867_LED_FN_RX;
994 case BIT(TRIGGER_NETDEV_LINK_1000):
995 return DP83867_LED_FN_LINK_1000_BT;
996 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
997 return DP83867_LED_FN_RX_TX;
998 case BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000):
999 return DP83867_LED_FN_LINK_100_1000_BT;
1000 case BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100):
1001 return DP83867_LED_FN_LINK_10_100_BT;
1002 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1003 return DP83867_LED_FN_LINK_RX_TX;
1004 default:
1005 return -EOPNOTSUPP;
1006 }
1007 }
1008
dp83867_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)1009 static int dp83867_led_hw_is_supported(struct phy_device *phydev, u8 index,
1010 unsigned long rules)
1011 {
1012 int ret;
1013
1014 ret = dp83867_led_mode(index, rules);
1015 if (ret < 0)
1016 return ret;
1017
1018 return 0;
1019 }
1020
dp83867_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)1021 static int dp83867_led_hw_control_set(struct phy_device *phydev, u8 index,
1022 unsigned long rules)
1023 {
1024 int mode, ret;
1025
1026 mode = dp83867_led_mode(index, rules);
1027 if (mode < 0)
1028 return mode;
1029
1030 ret = phy_modify(phydev, DP83867_LEDCR1, DP83867_LED_FN_MASK(index),
1031 DP83867_LED_FN(index, mode));
1032 if (ret)
1033 return ret;
1034
1035 return phy_modify(phydev, DP83867_LEDCR2, DP83867_LED_DRV_EN(index), 0);
1036 }
1037
dp83867_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)1038 static int dp83867_led_hw_control_get(struct phy_device *phydev, u8 index,
1039 unsigned long *rules)
1040 {
1041 int val;
1042
1043 val = phy_read(phydev, DP83867_LEDCR1);
1044 if (val < 0)
1045 return val;
1046
1047 val &= DP83867_LED_FN_MASK(index);
1048 val >>= index * 4;
1049
1050 switch (val) {
1051 case DP83867_LED_FN_LINK:
1052 *rules = BIT(TRIGGER_NETDEV_LINK);
1053 break;
1054 case DP83867_LED_FN_LINK_10_BT:
1055 *rules = BIT(TRIGGER_NETDEV_LINK_10);
1056 break;
1057 case DP83867_LED_FN_LINK_100_BTX:
1058 *rules = BIT(TRIGGER_NETDEV_LINK_100);
1059 break;
1060 case DP83867_LED_FN_FULL_DUPLEX:
1061 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1062 break;
1063 case DP83867_LED_FN_TX:
1064 *rules = BIT(TRIGGER_NETDEV_TX);
1065 break;
1066 case DP83867_LED_FN_RX:
1067 *rules = BIT(TRIGGER_NETDEV_RX);
1068 break;
1069 case DP83867_LED_FN_LINK_1000_BT:
1070 *rules = BIT(TRIGGER_NETDEV_LINK_1000);
1071 break;
1072 case DP83867_LED_FN_RX_TX:
1073 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
1074 break;
1075 case DP83867_LED_FN_LINK_100_1000_BT:
1076 *rules = BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000);
1077 break;
1078 case DP83867_LED_FN_LINK_10_100_BT:
1079 *rules = BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100);
1080 break;
1081 case DP83867_LED_FN_LINK_RX_TX:
1082 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
1083 BIT(TRIGGER_NETDEV_RX);
1084 break;
1085 default:
1086 *rules = 0;
1087 break;
1088 }
1089
1090 return 0;
1091 }
1092
dp83867_led_polarity_set(struct phy_device * phydev,int index,unsigned long modes)1093 static int dp83867_led_polarity_set(struct phy_device *phydev, int index,
1094 unsigned long modes)
1095 {
1096 /* Default active high */
1097 u16 polarity = DP83867_LED_POLARITY(index);
1098 u32 mode;
1099
1100 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
1101 switch (mode) {
1102 case PHY_LED_ACTIVE_LOW:
1103 polarity = 0;
1104 break;
1105 default:
1106 return -EINVAL;
1107 }
1108 }
1109 return phy_modify(phydev, DP83867_LEDCR2,
1110 DP83867_LED_POLARITY(index), polarity);
1111 }
1112
1113 static struct phy_driver dp83867_driver[] = {
1114 {
1115 .phy_id = DP83867_PHY_ID,
1116 .phy_id_mask = 0xfffffff0,
1117 .name = "TI DP83867",
1118 /* PHY_GBIT_FEATURES */
1119
1120 .probe = dp83867_probe,
1121 .config_init = dp83867_config_init,
1122 .soft_reset = dp83867_phy_reset,
1123
1124 .read_status = dp83867_read_status,
1125 .get_tunable = dp83867_get_tunable,
1126 .set_tunable = dp83867_set_tunable,
1127
1128 .get_wol = dp83867_get_wol,
1129 .set_wol = dp83867_set_wol,
1130
1131 /* IRQ related */
1132 .config_intr = dp83867_config_intr,
1133 .handle_interrupt = dp83867_handle_interrupt,
1134
1135 .suspend = dp83867_suspend,
1136 .resume = dp83867_resume,
1137
1138 .link_change_notify = dp83867_link_change_notify,
1139 .set_loopback = dp83867_loopback,
1140
1141 .led_brightness_set = dp83867_led_brightness_set,
1142 .led_hw_is_supported = dp83867_led_hw_is_supported,
1143 .led_hw_control_set = dp83867_led_hw_control_set,
1144 .led_hw_control_get = dp83867_led_hw_control_get,
1145 .led_polarity_set = dp83867_led_polarity_set,
1146 },
1147 };
1148 module_phy_driver(dp83867_driver);
1149
1150 static const struct mdio_device_id __maybe_unused dp83867_tbl[] = {
1151 { DP83867_PHY_ID, 0xfffffff0 },
1152 { }
1153 };
1154
1155 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
1156
1157 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
1158 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
1159 MODULE_LICENSE("GPL v2");
1160