1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ/G2L Clock Pulse Generator 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 */ 8 9 #ifndef __RENESAS_RZG2L_CPG_H__ 10 #define __RENESAS_RZG2L_CPG_H__ 11 12 #include <linux/notifier.h> 13 14 #define CPG_SIPLL5_STBY (0x140) 15 #define CPG_SIPLL5_CLK1 (0x144) 16 #define CPG_SIPLL5_CLK3 (0x14C) 17 #define CPG_SIPLL5_CLK4 (0x150) 18 #define CPG_SIPLL5_CLK5 (0x154) 19 #define CPG_SIPLL5_MON (0x15C) 20 #define CPG_PL1_DDIV (0x200) 21 #define CPG_PL2_DDIV (0x204) 22 #define CPG_PL3A_DDIV (0x208) 23 #define CPG_PL6_DDIV (0x210) 24 #define CPG_PL3C_SDIV (0x214) 25 #define CPG_CLKSTATUS (0x280) 26 #define CPG_PL3_SSEL (0x408) 27 #define CPG_PL6_SSEL (0x414) 28 #define CPG_PL6_ETH_SSEL (0x418) 29 #define CPG_PL5_SDIV (0x420) 30 #define CPG_RST_MON (0x680) 31 #define CPG_BUS_ACPU_MSTOP (0xB60) 32 #define CPG_BUS_MCPU1_MSTOP (0xB64) 33 #define CPG_BUS_MCPU2_MSTOP (0xB68) 34 #define CPG_BUS_PERI_COM_MSTOP (0xB6C) 35 #define CPG_BUS_PERI_CPU_MSTOP (0xB70) 36 #define CPG_BUS_PERI_DDR_MSTOP (0xB74) 37 #define CPG_BUS_REG0_MSTOP (0xB7C) 38 #define CPG_BUS_REG1_MSTOP (0xB80) 39 #define CPG_BUS_TZCDDR_MSTOP (0xB84) 40 #define CPG_MHU_MSTOP (0xB88) 41 #define CPG_BUS_MCPU3_MSTOP (0xB90) 42 #define CPG_BUS_PERI_CPU2_MSTOP (0xB94) 43 #define CPG_OTHERFUNC1_REG (0xBE8) 44 45 #define CPG_SIPLL5_STBY_RESETB BIT(0) 46 #define CPG_SIPLL5_STBY_RESETB_WEN BIT(16) 47 #define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18) 48 #define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20) 49 #define CPG_SIPLL5_CLK4_RESV_LSB (0xFF) 50 #define CPG_SIPLL5_MON_PLL5_LOCK BIT(4) 51 52 #define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16) 53 54 #define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16) 55 #define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24) 56 57 #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) 58 #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) 59 60 /* n = 0/1/2 for PLL1/4/6 */ 61 #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) 62 #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) 63 64 #define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) 65 66 #define DDIV_PACK(offset, bitpos, size) \ 67 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 68 #define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) 69 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) 70 #define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2) 71 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) 72 #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) 73 #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) 74 #define DIVPL3E DDIV_PACK(CPG_PL3C_SDIV, 8, 5) 75 #define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) 76 77 #define SEL_PLL_PACK(offset, bitpos, size) \ 78 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 79 80 #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) 81 #define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1) 82 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) 83 #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) 84 85 #define EXTAL_FREQ_IN_MEGA_HZ (24) 86 87 /** 88 * Definitions of CPG Core Clocks 89 * 90 * These include: 91 * - Clock outputs exported to DT 92 * - External input clocks 93 * - Internal CPG clocks 94 */ 95 struct cpg_core_clk { 96 const char *name; 97 unsigned int id; 98 unsigned int parent; 99 unsigned int div; 100 unsigned int mult; 101 unsigned int type; 102 unsigned int conf; 103 unsigned int sconf; 104 const struct clk_div_table *dtable; 105 const u32 *mtable; 106 const unsigned long invalid_rate; 107 union { 108 const unsigned long max_rate; 109 const unsigned long default_rate; 110 }; 111 const char * const *parent_names; 112 notifier_fn_t notifier; 113 u32 flag; 114 u32 mux_flags; 115 int num_parents; 116 }; 117 118 enum clk_types { 119 /* Generic */ 120 CLK_TYPE_IN, /* External Clock Input */ 121 CLK_TYPE_FF, /* Fixed Factor Clock */ 122 CLK_TYPE_SAM_PLL, 123 CLK_TYPE_G3S_PLL, 124 125 /* Clock with divider */ 126 CLK_TYPE_DIV, 127 CLK_TYPE_G3S_DIV, 128 129 /* Clock with clock source selector */ 130 CLK_TYPE_MUX, 131 132 /* Clock with SD clock source selector */ 133 CLK_TYPE_SD_MUX, 134 135 /* Clock for SIPLL5 */ 136 CLK_TYPE_SIPLL5, 137 138 /* Clock for PLL5_4 clock source selector */ 139 CLK_TYPE_PLL5_4_MUX, 140 141 /* Clock for DSI divider */ 142 CLK_TYPE_DSI_DIV, 143 144 }; 145 146 #define DEF_TYPE(_name, _id, _type...) \ 147 { .name = _name, .id = _id, .type = _type } 148 #define DEF_BASE(_name, _id, _type, _parent...) \ 149 DEF_TYPE(_name, _id, _type, .parent = _parent) 150 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ 151 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) 152 #define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \ 153 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \ 154 .default_rate = _default_rate) 155 #define DEF_INPUT(_name, _id) \ 156 DEF_TYPE(_name, _id, CLK_TYPE_IN) 157 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 158 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 159 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ 160 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 161 .parent = _parent, .dtable = _dtable, \ 162 .flag = CLK_DIVIDER_HIWORD_MASK) 163 #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ 164 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 165 .parent = _parent, .dtable = _dtable, \ 166 .flag = CLK_DIVIDER_READ_ONLY) 167 #define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \ 168 _max_rate, _clk_flags, _notif) \ 169 DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \ 170 .parent = _parent, .dtable = _dtable, \ 171 .invalid_rate = _invalid_rate, \ 172 .max_rate = _max_rate, .flag = (_clk_flags), \ 173 .notifier = _notif) 174 #define DEF_MUX(_name, _id, _conf, _parent_names) \ 175 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 176 .parent_names = _parent_names, \ 177 .num_parents = ARRAY_SIZE(_parent_names), \ 178 .mux_flags = CLK_MUX_HIWORD_MASK) 179 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ 180 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 181 .parent_names = _parent_names, \ 182 .num_parents = ARRAY_SIZE(_parent_names), \ 183 .mux_flags = CLK_MUX_READ_ONLY) 184 #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \ 185 DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \ 186 .parent_names = _parent_names, \ 187 .num_parents = ARRAY_SIZE(_parent_names), \ 188 .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier) 189 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ 190 DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) 191 #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ 192 DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ 193 .parent_names = _parent_names, \ 194 .num_parents = ARRAY_SIZE(_parent_names)) 195 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ 196 DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) 197 198 /** 199 * struct rzg2l_mod_clk - Module Clocks definitions 200 * 201 * @name: handle between common and hardware-specific interfaces 202 * @id: clock index in array containing all Core and Module Clocks 203 * @parent: id of parent clock 204 * @off: register offset 205 * @bit: ON/MON bit 206 * @is_coupled: flag to indicate coupled clock 207 */ 208 struct rzg2l_mod_clk { 209 const char *name; 210 unsigned int id; 211 unsigned int parent; 212 u16 off; 213 u8 bit; 214 bool is_coupled; 215 }; 216 217 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ 218 { \ 219 .name = _name, \ 220 .id = MOD_CLK_BASE + (_id), \ 221 .parent = (_parent), \ 222 .off = (_off), \ 223 .bit = (_bit), \ 224 .is_coupled = (_is_coupled), \ 225 } 226 227 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ 228 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false) 229 230 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ 231 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true) 232 233 /** 234 * struct rzg2l_reset - Reset definitions 235 * 236 * @off: register offset 237 * @bit: reset bit 238 * @monbit: monitor bit in CPG_RST_MON register, -1 if none 239 */ 240 struct rzg2l_reset { 241 u16 off; 242 u8 bit; 243 s8 monbit; 244 }; 245 246 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ 247 [_id] = { \ 248 .off = (_off), \ 249 .bit = (_bit), \ 250 .monbit = (_monbit) \ 251 } 252 #define DEF_RST(_id, _off, _bit) \ 253 DEF_RST_MON(_id, _off, _bit, -1) 254 255 /** 256 * struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure 257 * @off: register offset 258 * @mask: register mask 259 */ 260 struct rzg2l_cpg_reg_conf { 261 u16 off; 262 u16 mask; 263 }; 264 265 #define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) }) 266 267 /** 268 * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure 269 * @mstop: MSTOP register configuration 270 */ 271 struct rzg2l_cpg_pm_domain_conf { 272 struct rzg2l_cpg_reg_conf mstop; 273 }; 274 275 /** 276 * struct rzg2l_cpg_pm_domain_init_data - PM domain init data 277 * @name: PM domain name 278 * @conf: PM domain configuration 279 * @genpd_flags: genpd flags (see GENPD_FLAG_*) 280 * @id: PM domain ID (similar to the ones defined in 281 * include/dt-bindings/clock/<soc-id>-cpg.h) 282 */ 283 struct rzg2l_cpg_pm_domain_init_data { 284 const char * const name; 285 struct rzg2l_cpg_pm_domain_conf conf; 286 u32 genpd_flags; 287 u16 id; 288 }; 289 290 #define DEF_PD(_name, _id, _mstop_conf, _flags) \ 291 { \ 292 .name = (_name), \ 293 .id = (_id), \ 294 .conf = { \ 295 .mstop = (_mstop_conf), \ 296 }, \ 297 .genpd_flags = (_flags), \ 298 } 299 300 /** 301 * struct rzg2l_cpg_info - SoC-specific CPG Description 302 * 303 * @core_clks: Array of Core Clock definitions 304 * @num_core_clks: Number of entries in core_clks[] 305 * @last_dt_core_clk: ID of the last Core Clock exported to DT 306 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 307 * 308 * @mod_clks: Array of Module Clock definitions 309 * @num_mod_clks: Number of entries in mod_clks[] 310 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 311 * 312 * @resets: Array of Module Reset definitions 313 * @num_resets: Number of entries in resets[] 314 * 315 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that 316 * should not be disabled without a knowledgeable driver 317 * @num_crit_mod_clks: Number of entries in crit_mod_clks[] 318 * @pm_domains: PM domains init data array 319 * @num_pm_domains: Number of PM domains 320 * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers 321 */ 322 struct rzg2l_cpg_info { 323 /* Core Clocks */ 324 const struct cpg_core_clk *core_clks; 325 unsigned int num_core_clks; 326 unsigned int last_dt_core_clk; 327 unsigned int num_total_core_clks; 328 329 /* Module Clocks */ 330 const struct rzg2l_mod_clk *mod_clks; 331 unsigned int num_mod_clks; 332 unsigned int num_hw_mod_clks; 333 334 /* No PM Module Clocks */ 335 const unsigned int *no_pm_mod_clks; 336 unsigned int num_no_pm_mod_clks; 337 338 /* Resets */ 339 const struct rzg2l_reset *resets; 340 unsigned int num_resets; 341 342 /* Critical Module Clocks that should not be disabled */ 343 const unsigned int *crit_mod_clks; 344 unsigned int num_crit_mod_clks; 345 346 /* Power domain. */ 347 const struct rzg2l_cpg_pm_domain_init_data *pm_domains; 348 unsigned int num_pm_domains; 349 350 bool has_clk_mon_regs; 351 }; 352 353 extern const struct rzg2l_cpg_info r9a07g043_cpg_info; 354 extern const struct rzg2l_cpg_info r9a07g044_cpg_info; 355 extern const struct rzg2l_cpg_info r9a07g054_cpg_info; 356 extern const struct rzg2l_cpg_info r9a08g045_cpg_info; 357 extern const struct rzg2l_cpg_info r9a09g011_cpg_info; 358 359 int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data); 360 int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); 361 362 #endif 363