1 // include/asm-arm/mach-omap/usb.h
2
3 #ifndef __ASM_ARCH_OMAP_USB_H
4 #define __ASM_ARCH_OMAP_USB_H
5
6 #include <linux/usb/musb.h>
7 #include <plat/board.h>
8
9 #define OMAP3_HS_USB_PORTS 3
10
11 enum usbhs_omap_port_mode {
12 OMAP_USBHS_PORT_MODE_UNUSED,
13 OMAP_EHCI_PORT_MODE_PHY,
14 OMAP_EHCI_PORT_MODE_TLL,
15 OMAP_EHCI_PORT_MODE_HSIC,
16 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
17 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
18 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
19 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
20 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
21 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
22 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
23 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
24 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
25 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
26 };
27
28 struct usbhs_omap_board_data {
29 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
30
31 /* have to be valid if phy_reset is true and portx is in phy mode */
32 int reset_gpio_port[OMAP3_HS_USB_PORTS];
33
34 /* Set this to true for ES2.x silicon */
35 unsigned es2_compatibility:1;
36
37 unsigned phy_reset:1;
38
39 /*
40 * Regulators for USB PHYs.
41 * Each PHY can have a separate regulator.
42 */
43 struct regulator *regulator[OMAP3_HS_USB_PORTS];
44 };
45
46 struct ehci_hcd_omap_platform_data {
47 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
48 int reset_gpio_port[OMAP3_HS_USB_PORTS];
49 struct regulator *regulator[OMAP3_HS_USB_PORTS];
50 unsigned phy_reset:1;
51 };
52
53 struct ohci_hcd_omap_platform_data {
54 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
55 unsigned es2_compatibility:1;
56 };
57
58 struct usbhs_omap_platform_data {
59 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
60
61 struct ehci_hcd_omap_platform_data *ehci_data;
62 struct ohci_hcd_omap_platform_data *ohci_data;
63 };
64 /*-------------------------------------------------------------------------*/
65
66 #define OMAP1_OTG_BASE 0xfffb0400
67 #define OMAP1_UDC_BASE 0xfffb4000
68 #define OMAP1_OHCI_BASE 0xfffba000
69
70 #define OMAP2_OHCI_BASE 0x4805e000
71 #define OMAP2_UDC_BASE 0x4805e200
72 #define OMAP2_OTG_BASE 0x4805e300
73
74 #ifdef CONFIG_ARCH_OMAP1
75
76 #define OTG_BASE OMAP1_OTG_BASE
77 #define UDC_BASE OMAP1_UDC_BASE
78 #define OMAP_OHCI_BASE OMAP1_OHCI_BASE
79
80 #else
81
82 #define OTG_BASE OMAP2_OTG_BASE
83 #define UDC_BASE OMAP2_UDC_BASE
84 #define OMAP_OHCI_BASE OMAP2_OHCI_BASE
85
86 struct omap_musb_board_data {
87 u8 interface_type;
88 u8 mode;
89 u16 power;
90 unsigned extvbus:1;
91 void (*set_phy_power)(u8 on);
92 void (*clear_irq)(void);
93 void (*set_mode)(u8 mode);
94 void (*reset)(void);
95 };
96
97 enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
98
99 extern void usb_musb_init(struct omap_musb_board_data *board_data);
100
101 extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
102
103 extern int omap4430_phy_power(struct device *dev, int ID, int on);
104 extern int omap4430_phy_set_clk(struct device *dev, int on);
105 extern int omap4430_phy_init(struct device *dev);
106 extern int omap4430_phy_exit(struct device *dev);
107 extern int omap4430_phy_suspend(struct device *dev, int suspend);
108 #endif
109
110 extern void am35x_musb_reset(void);
111 extern void am35x_musb_phy_power(u8 on);
112 extern void am35x_musb_clear_irq(void);
113 extern void am35x_set_mode(u8 musb_mode);
114 extern void ti81xx_musb_phy_power(u8 on);
115
116 /*
117 * FIXME correct answer depends on hmc_mode,
118 * as does (on omap1) any nonzero value for config->otg port number
119 */
120 #ifdef CONFIG_USB_GADGET_OMAP
121 #define is_usb0_device(config) 1
122 #else
123 #define is_usb0_device(config) 0
124 #endif
125
126 void omap_otg_init(struct omap_usb_config *config);
127
128 #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
129 void omap1_usb_init(struct omap_usb_config *pdata);
130 #else
omap1_usb_init(struct omap_usb_config * pdata)131 static inline void omap1_usb_init(struct omap_usb_config *pdata)
132 {
133 }
134 #endif
135
136 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
137 void omap2_usbfs_init(struct omap_usb_config *pdata);
138 #else
omap2_usbfs_init(struct omap_usb_config * pdata)139 static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
140 {
141 }
142 #endif
143
144 /*-------------------------------------------------------------------------*/
145
146 /*
147 * OTG and transceiver registers, for OMAPs starting with ARM926
148 */
149 #define OTG_REV (OTG_BASE + 0x00)
150 #define OTG_SYSCON_1 (OTG_BASE + 0x04)
151 # define USB2_TRX_MODE(w) (((w)>>24)&0x07)
152 # define USB1_TRX_MODE(w) (((w)>>20)&0x07)
153 # define USB0_TRX_MODE(w) (((w)>>16)&0x07)
154 # define OTG_IDLE_EN (1 << 15)
155 # define HST_IDLE_EN (1 << 14)
156 # define DEV_IDLE_EN (1 << 13)
157 # define OTG_RESET_DONE (1 << 2)
158 # define OTG_SOFT_RESET (1 << 1)
159 #define OTG_SYSCON_2 (OTG_BASE + 0x08)
160 # define OTG_EN (1 << 31)
161 # define USBX_SYNCHRO (1 << 30)
162 # define OTG_MST16 (1 << 29)
163 # define SRP_GPDATA (1 << 28)
164 # define SRP_GPDVBUS (1 << 27)
165 # define SRP_GPUVBUS(w) (((w)>>24)&0x07)
166 # define A_WAIT_VRISE(w) (((w)>>20)&0x07)
167 # define B_ASE_BRST(w) (((w)>>16)&0x07)
168 # define SRP_DPW (1 << 14)
169 # define SRP_DATA (1 << 13)
170 # define SRP_VBUS (1 << 12)
171 # define OTG_PADEN (1 << 10)
172 # define HMC_PADEN (1 << 9)
173 # define UHOST_EN (1 << 8)
174 # define HMC_TLLSPEED (1 << 7)
175 # define HMC_TLLATTACH (1 << 6)
176 # define OTG_HMC(w) (((w)>>0)&0x3f)
177 #define OTG_CTRL (OTG_BASE + 0x0c)
178 # define OTG_USB2_EN (1 << 29)
179 # define OTG_USB2_DP (1 << 28)
180 # define OTG_USB2_DM (1 << 27)
181 # define OTG_USB1_EN (1 << 26)
182 # define OTG_USB1_DP (1 << 25)
183 # define OTG_USB1_DM (1 << 24)
184 # define OTG_USB0_EN (1 << 23)
185 # define OTG_USB0_DP (1 << 22)
186 # define OTG_USB0_DM (1 << 21)
187 # define OTG_ASESSVLD (1 << 20)
188 # define OTG_BSESSEND (1 << 19)
189 # define OTG_BSESSVLD (1 << 18)
190 # define OTG_VBUSVLD (1 << 17)
191 # define OTG_ID (1 << 16)
192 # define OTG_DRIVER_SEL (1 << 15)
193 # define OTG_A_SETB_HNPEN (1 << 12)
194 # define OTG_A_BUSREQ (1 << 11)
195 # define OTG_B_HNPEN (1 << 9)
196 # define OTG_B_BUSREQ (1 << 8)
197 # define OTG_BUSDROP (1 << 7)
198 # define OTG_PULLDOWN (1 << 5)
199 # define OTG_PULLUP (1 << 4)
200 # define OTG_DRV_VBUS (1 << 3)
201 # define OTG_PD_VBUS (1 << 2)
202 # define OTG_PU_VBUS (1 << 1)
203 # define OTG_PU_ID (1 << 0)
204 #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
205 # define DRIVER_SWITCH (1 << 15)
206 # define A_VBUS_ERR (1 << 13)
207 # define A_REQ_TMROUT (1 << 12)
208 # define A_SRP_DETECT (1 << 11)
209 # define B_HNP_FAIL (1 << 10)
210 # define B_SRP_TMROUT (1 << 9)
211 # define B_SRP_DONE (1 << 8)
212 # define B_SRP_STARTED (1 << 7)
213 # define OPRT_CHG (1 << 0)
214 #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
215 // same bits as in IRQ_EN
216 #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
217 # define OTGVPD (1 << 14)
218 # define OTGVPU (1 << 13)
219 # define OTGPUID (1 << 12)
220 # define USB2VDR (1 << 10)
221 # define USB2PDEN (1 << 9)
222 # define USB2PUEN (1 << 8)
223 # define USB1VDR (1 << 6)
224 # define USB1PDEN (1 << 5)
225 # define USB1PUEN (1 << 4)
226 # define USB0VDR (1 << 2)
227 # define USB0PDEN (1 << 1)
228 # define USB0PUEN (1 << 0)
229 #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
230 #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
231
232 /*-------------------------------------------------------------------------*/
233
234 /* OMAP1 */
235 #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
236 # define CONF_USB2_UNI_R (1 << 8)
237 # define CONF_USB1_UNI_R (1 << 7)
238 # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
239 # define CONF_USB0_ISOLATE_R (1 << 3)
240 # define CONF_USB_PWRDN_DM_R (1 << 2)
241 # define CONF_USB_PWRDN_DP_R (1 << 1)
242
243 /* OMAP2 */
244 # define USB_UNIDIR 0x0
245 # define USB_UNIDIR_TLL 0x1
246 # define USB_BIDIR 0x2
247 # define USB_BIDIR_TLL 0x3
248 # define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
249 # define USBT2TLL5PI (1 << 17)
250 # define USB0PUENACTLOI (1 << 16)
251 # define USBSTANDBYCTRL (1 << 15)
252 /* AM35x */
253 /* USB 2.0 PHY Control */
254 #define CONF2_PHY_GPIOMODE (1 << 23)
255 #define CONF2_OTGMODE (3 << 14)
256 #define CONF2_NO_OVERRIDE (0 << 14)
257 #define CONF2_FORCE_HOST (1 << 14)
258 #define CONF2_FORCE_DEVICE (2 << 14)
259 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
260 #define CONF2_SESENDEN (1 << 13)
261 #define CONF2_VBDTCTEN (1 << 12)
262 #define CONF2_REFFREQ_24MHZ (2 << 8)
263 #define CONF2_REFFREQ_26MHZ (7 << 8)
264 #define CONF2_REFFREQ_13MHZ (6 << 8)
265 #define CONF2_REFFREQ (0xf << 8)
266 #define CONF2_PHYCLKGD (1 << 7)
267 #define CONF2_VBUSSENSE (1 << 6)
268 #define CONF2_PHY_PLLON (1 << 5)
269 #define CONF2_RESET (1 << 4)
270 #define CONF2_PHYPWRDN (1 << 3)
271 #define CONF2_OTGPWRDN (1 << 2)
272 #define CONF2_DATPOL (1 << 1)
273
274 /* TI81XX specific definitions */
275 #define USBCTRL0 0x620
276 #define USBSTAT0 0x624
277
278 /* TI816X PHY controls bits */
279 #define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
280 #define TI816X_USBPHY_REFCLK_OSC (1 << 8)
281
282 /* TI814X PHY controls bits */
283 #define USBPHY_CM_PWRDN (1 << 0)
284 #define USBPHY_OTG_PWRDN (1 << 1)
285 #define USBPHY_CHGDET_DIS (1 << 2)
286 #define USBPHY_CHGDET_RSTRT (1 << 3)
287 #define USBPHY_SRCONDM (1 << 4)
288 #define USBPHY_SINKONDP (1 << 5)
289 #define USBPHY_CHGISINK_EN (1 << 6)
290 #define USBPHY_CHGVSRC_EN (1 << 7)
291 #define USBPHY_DMPULLUP (1 << 8)
292 #define USBPHY_DPPULLUP (1 << 9)
293 #define USBPHY_CDET_EXTCTL (1 << 10)
294 #define USBPHY_GPIO_MODE (1 << 12)
295 #define USBPHY_DPOPBUFCTL (1 << 13)
296 #define USBPHY_DMOPBUFCTL (1 << 14)
297 #define USBPHY_DPINPUT (1 << 15)
298 #define USBPHY_DMINPUT (1 << 16)
299 #define USBPHY_DPGPIO_PD (1 << 17)
300 #define USBPHY_DMGPIO_PD (1 << 18)
301 #define USBPHY_OTGVDET_EN (1 << 19)
302 #define USBPHY_OTGSESSEND_EN (1 << 20)
303 #define USBPHY_DATA_POLARITY (1 << 23)
304
305 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
306 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
307 u32 omap1_usb1_init(unsigned nwires);
308 u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
309 #else
omap1_usb0_init(unsigned nwires,unsigned is_device)310 static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
311 {
312 return 0;
313 }
omap1_usb1_init(unsigned nwires)314 static inline u32 omap1_usb1_init(unsigned nwires)
315 {
316 return 0;
317
318 }
omap1_usb2_init(unsigned nwires,unsigned alt_pingroup)319 static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
320 {
321 return 0;
322 }
323 #endif
324
325 #endif /* __ASM_ARCH_OMAP_USB_H */
326