1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DCN20_DCCG_H__ 27 #define __DCN20_DCCG_H__ 28 29 #include "dccg.h" 30 31 #define DCCG_COMMON_REG_LIST_DCN_BASE() \ 32 SR(DPPCLK_DTO_CTRL),\ 33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ 34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ 35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ 36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ 37 SR(REFCLK_CNTL),\ 38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ 39 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ 40 SR(DISPCLK_FREQ_CHANGE_CNTL),\ 41 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ 42 SR(MICROSECOND_TIME_BASE_DIV),\ 43 SR(MILLISECOND_TIME_BASE_DIV),\ 44 SR(DCCG_GATE_DISABLE_CNTL),\ 45 SR(DCCG_GATE_DISABLE_CNTL2) 46 47 #define DCCG_REG_LIST_DCN2() \ 48 DCCG_COMMON_REG_LIST_DCN_BASE(),\ 49 DCCG_SRII(DTO_PARAM, DPPCLK, 4),\ 50 DCCG_SRII(DTO_PARAM, DPPCLK, 5),\ 51 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ 52 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ 53 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\ 54 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5) 55 56 #define DCCG_SF(reg_name, field_name, post_fix)\ 57 .field_name = reg_name ## __ ## field_name ## post_fix 58 59 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ 60 .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix 61 62 #define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ 63 .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix 64 65 #define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ 66 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ 67 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ 68 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ 69 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ 70 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\ 71 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ 72 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\ 73 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ 74 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ 75 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ 76 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ 77 DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\ 78 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ 79 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ 80 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ 81 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ 82 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ 83 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ 84 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ 85 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\ 86 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ 87 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ 88 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ 89 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\ 90 DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 91 92 93 94 95 #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \ 96 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 97 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ 98 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ 99 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ 100 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\ 101 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ 102 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ 103 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\ 104 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\ 105 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\ 106 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\ 107 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\ 108 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh) 109 110 #define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \ 111 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 112 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ 113 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ 114 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ 115 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\ 116 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ 117 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ 118 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\ 119 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh) 120 121 122 #define DCCG_REG_FIELD_LIST(type) \ 123 type DPPCLK0_DTO_PHASE;\ 124 type DPPCLK0_DTO_MODULO;\ 125 type DPPCLK_DTO_ENABLE[6];\ 126 type DPPCLK_DTO_DB_EN[6];\ 127 type REFCLK_CLOCK_EN;\ 128 type REFCLK_SRC_SEL;\ 129 type DISPCLK_STEP_DELAY;\ 130 type DISPCLK_STEP_SIZE;\ 131 type DISPCLK_FREQ_RAMP_DONE;\ 132 type DISPCLK_MAX_ERRDET_CYCLES;\ 133 type DCCG_FIFO_ERRDET_RESET;\ 134 type DCCG_FIFO_ERRDET_STATE;\ 135 type DCCG_FIFO_ERRDET_OVR_EN;\ 136 type DISPCLK_CHG_FWD_CORR_DISABLE;\ 137 type DISPCLK_FREQ_CHANGE_CNTL;\ 138 type OTG_ADD_PIXEL[MAX_PIPES];\ 139 type OTG_DROP_PIXEL[MAX_PIPES];\ 140 type DC_MEM_GLOBAL_PWR_REQ_DIS; 141 142 #define DCCG3_REG_FIELD_LIST(type) \ 143 type HDMICHARCLK0_EN;\ 144 type HDMICHARCLK0_SRC_SEL;\ 145 type PHYASYMCLK_FORCE_EN;\ 146 type PHYASYMCLK_FORCE_SRC_SEL;\ 147 type PHYBSYMCLK_FORCE_EN;\ 148 type PHYBSYMCLK_FORCE_SRC_SEL;\ 149 type PHYCSYMCLK_FORCE_EN;\ 150 type PHYCSYMCLK_FORCE_SRC_SEL; 151 152 #define DCCG31_REG_FIELD_LIST(type) \ 153 type PHYDSYMCLK_FORCE_EN;\ 154 type PHYDSYMCLK_FORCE_SRC_SEL;\ 155 type PHYESYMCLK_FORCE_EN;\ 156 type PHYESYMCLK_FORCE_SRC_SEL;\ 157 type DPSTREAMCLK_PIPE0_EN;\ 158 type DPSTREAMCLK_PIPE1_EN;\ 159 type DPSTREAMCLK_PIPE2_EN;\ 160 type DPSTREAMCLK_PIPE3_EN;\ 161 type HDMISTREAMCLK0_SRC_SEL;\ 162 type HDMISTREAMCLK0_DTO_FORCE_DIS;\ 163 type SYMCLK32_SE0_SRC_SEL;\ 164 type SYMCLK32_SE1_SRC_SEL;\ 165 type SYMCLK32_SE2_SRC_SEL;\ 166 type SYMCLK32_SE3_SRC_SEL;\ 167 type SYMCLK32_SE0_EN;\ 168 type SYMCLK32_SE1_EN;\ 169 type SYMCLK32_SE2_EN;\ 170 type SYMCLK32_SE3_EN;\ 171 type SYMCLK32_LE0_SRC_SEL;\ 172 type SYMCLK32_LE1_SRC_SEL;\ 173 type SYMCLK32_LE0_EN;\ 174 type SYMCLK32_LE1_EN;\ 175 type DTBCLK_DTO_ENABLE[MAX_PIPES];\ 176 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\ 177 type PIPE_DTO_SRC_SEL[MAX_PIPES];\ 178 type DTBCLK_DTO_DIV[MAX_PIPES];\ 179 type DCCG_AUDIO_DTO_SEL;\ 180 type DCCG_AUDIO_DTO0_SOURCE_SEL;\ 181 type DENTIST_DISPCLK_CHG_MODE;\ 182 type DSCCLK0_DTO_PHASE;\ 183 type DSCCLK0_DTO_MODULO;\ 184 type DSCCLK1_DTO_PHASE;\ 185 type DSCCLK1_DTO_MODULO;\ 186 type DSCCLK2_DTO_PHASE;\ 187 type DSCCLK2_DTO_MODULO;\ 188 type DSCCLK0_DTO_ENABLE;\ 189 type DSCCLK1_DTO_ENABLE;\ 190 type DSCCLK2_DTO_ENABLE;\ 191 type SYMCLK32_ROOT_SE0_GATE_DISABLE;\ 192 type SYMCLK32_ROOT_SE1_GATE_DISABLE;\ 193 type SYMCLK32_ROOT_SE2_GATE_DISABLE;\ 194 type SYMCLK32_ROOT_SE3_GATE_DISABLE;\ 195 type SYMCLK32_SE0_GATE_DISABLE;\ 196 type SYMCLK32_SE1_GATE_DISABLE;\ 197 type SYMCLK32_SE2_GATE_DISABLE;\ 198 type SYMCLK32_SE3_GATE_DISABLE;\ 199 type SYMCLK32_ROOT_LE0_GATE_DISABLE;\ 200 type SYMCLK32_ROOT_LE1_GATE_DISABLE;\ 201 type SYMCLK32_LE0_GATE_DISABLE;\ 202 type SYMCLK32_LE1_GATE_DISABLE;\ 203 type DPSTREAMCLK_ROOT_GATE_DISABLE;\ 204 type DPSTREAMCLK_GATE_DISABLE;\ 205 type HDMISTREAMCLK0_DTO_PHASE;\ 206 type HDMISTREAMCLK0_DTO_MODULO;\ 207 type HDMICHARCLK0_GATE_DISABLE;\ 208 type HDMICHARCLK0_ROOT_GATE_DISABLE; \ 209 type PHYASYMCLK_GATE_DISABLE; \ 210 type PHYBSYMCLK_GATE_DISABLE; \ 211 type PHYCSYMCLK_GATE_DISABLE; \ 212 type PHYDSYMCLK_GATE_DISABLE; \ 213 type PHYESYMCLK_GATE_DISABLE; 214 215 #define DCCG314_REG_FIELD_LIST(type) \ 216 type DSCCLK3_DTO_PHASE;\ 217 type DSCCLK3_DTO_MODULO;\ 218 type DSCCLK3_DTO_ENABLE;\ 219 type DENTIST_DISPCLK_RDIVIDER;\ 220 type DENTIST_DISPCLK_WDIVIDER; 221 222 #define DCCG32_REG_FIELD_LIST(type) \ 223 type DPSTREAMCLK0_EN;\ 224 type DPSTREAMCLK1_EN;\ 225 type DPSTREAMCLK2_EN;\ 226 type DPSTREAMCLK3_EN;\ 227 type DPSTREAMCLK0_SRC_SEL;\ 228 type DPSTREAMCLK1_SRC_SEL;\ 229 type DPSTREAMCLK2_SRC_SEL;\ 230 type DPSTREAMCLK3_SRC_SEL;\ 231 type HDMISTREAMCLK0_EN;\ 232 type OTG0_PIXEL_RATE_DIVK1;\ 233 type OTG0_PIXEL_RATE_DIVK2;\ 234 type OTG1_PIXEL_RATE_DIVK1;\ 235 type OTG1_PIXEL_RATE_DIVK2;\ 236 type OTG2_PIXEL_RATE_DIVK1;\ 237 type OTG2_PIXEL_RATE_DIVK2;\ 238 type OTG3_PIXEL_RATE_DIVK1;\ 239 type OTG3_PIXEL_RATE_DIVK2;\ 240 type DTBCLK_P0_SRC_SEL;\ 241 type DTBCLK_P0_EN;\ 242 type DTBCLK_P1_SRC_SEL;\ 243 type DTBCLK_P1_EN;\ 244 type DTBCLK_P2_SRC_SEL;\ 245 type DTBCLK_P2_EN;\ 246 type DTBCLK_P3_SRC_SEL;\ 247 type DTBCLK_P3_EN;\ 248 type DENTIST_DISPCLK_CHG_DONE; 249 250 #define DCCG35_REG_FIELD_LIST(type) \ 251 type DPPCLK0_EN;\ 252 type DPPCLK1_EN;\ 253 type DPPCLK2_EN;\ 254 type DPPCLK3_EN;\ 255 type DSCCLK0_EN;\ 256 type DSCCLK1_EN;\ 257 type DSCCLK2_EN;\ 258 type DSCCLK3_EN;\ 259 type DISPCLK_DCCG_GATE_DISABLE;\ 260 type DCCG_GLOBAL_FGCG_REP_DIS; \ 261 type PHYASYMCLK_EN;\ 262 type PHYASYMCLK_SRC_SEL;\ 263 type PHYBSYMCLK_EN;\ 264 type PHYBSYMCLK_SRC_SEL;\ 265 type PHYCSYMCLK_EN;\ 266 type PHYCSYMCLK_SRC_SEL;\ 267 type PHYDSYMCLK_EN;\ 268 type PHYDSYMCLK_SRC_SEL;\ 269 type PHYESYMCLK_EN;\ 270 type PHYESYMCLK_SRC_SEL;\ 271 type PHYASYMCLK_ROOT_GATE_DISABLE;\ 272 type PHYBSYMCLK_ROOT_GATE_DISABLE;\ 273 type PHYCSYMCLK_ROOT_GATE_DISABLE;\ 274 type PHYDSYMCLK_ROOT_GATE_DISABLE;\ 275 type PHYESYMCLK_ROOT_GATE_DISABLE;\ 276 type HDMISTREAMCLK0_GATE_DISABLE;\ 277 type HDMISTREAMCLK1_GATE_DISABLE;\ 278 type HDMISTREAMCLK2_GATE_DISABLE;\ 279 type HDMISTREAMCLK3_GATE_DISABLE;\ 280 type HDMISTREAMCLK4_GATE_DISABLE;\ 281 type HDMISTREAMCLK5_GATE_DISABLE;\ 282 type SYMCLKA_CLOCK_ENABLE;\ 283 type SYMCLKB_CLOCK_ENABLE;\ 284 type SYMCLKC_CLOCK_ENABLE;\ 285 type SYMCLKD_CLOCK_ENABLE;\ 286 type SYMCLKE_CLOCK_ENABLE;\ 287 type SYMCLKA_FE_EN;\ 288 type SYMCLKB_FE_EN;\ 289 type SYMCLKC_FE_EN;\ 290 type SYMCLKD_FE_EN;\ 291 type SYMCLKE_FE_EN;\ 292 type SYMCLKA_SRC_SEL;\ 293 type SYMCLKB_SRC_SEL;\ 294 type SYMCLKC_SRC_SEL;\ 295 type SYMCLKD_SRC_SEL;\ 296 type SYMCLKE_SRC_SEL;\ 297 type SYMCLKA_FE_SRC_SEL;\ 298 type SYMCLKB_FE_SRC_SEL;\ 299 type SYMCLKC_FE_SRC_SEL;\ 300 type SYMCLKD_FE_SRC_SEL;\ 301 type SYMCLKE_FE_SRC_SEL;\ 302 type DTBCLK_P0_GATE_DISABLE;\ 303 type DTBCLK_P1_GATE_DISABLE;\ 304 type DTBCLK_P2_GATE_DISABLE;\ 305 type DTBCLK_P3_GATE_DISABLE;\ 306 type DSCCLK0_ROOT_GATE_DISABLE;\ 307 type DSCCLK1_ROOT_GATE_DISABLE;\ 308 type DSCCLK2_ROOT_GATE_DISABLE;\ 309 type DSCCLK3_ROOT_GATE_DISABLE;\ 310 type SYMCLKA_FE_ROOT_GATE_DISABLE;\ 311 type SYMCLKB_FE_ROOT_GATE_DISABLE;\ 312 type SYMCLKC_FE_ROOT_GATE_DISABLE;\ 313 type SYMCLKD_FE_ROOT_GATE_DISABLE;\ 314 type SYMCLKE_FE_ROOT_GATE_DISABLE;\ 315 type DPPCLK0_ROOT_GATE_DISABLE;\ 316 type DPPCLK1_ROOT_GATE_DISABLE;\ 317 type DPPCLK2_ROOT_GATE_DISABLE;\ 318 type DPPCLK3_ROOT_GATE_DISABLE;\ 319 type HDMISTREAMCLK0_ROOT_GATE_DISABLE;\ 320 type SYMCLKA_ROOT_GATE_DISABLE;\ 321 type SYMCLKB_ROOT_GATE_DISABLE;\ 322 type SYMCLKC_ROOT_GATE_DISABLE;\ 323 type SYMCLKD_ROOT_GATE_DISABLE;\ 324 type SYMCLKE_ROOT_GATE_DISABLE;\ 325 type PHYA_REFCLK_ROOT_GATE_DISABLE;\ 326 type PHYB_REFCLK_ROOT_GATE_DISABLE;\ 327 type PHYC_REFCLK_ROOT_GATE_DISABLE;\ 328 type PHYD_REFCLK_ROOT_GATE_DISABLE;\ 329 type PHYE_REFCLK_ROOT_GATE_DISABLE;\ 330 type DPSTREAMCLK0_ROOT_GATE_DISABLE;\ 331 type DPSTREAMCLK1_ROOT_GATE_DISABLE;\ 332 type DPSTREAMCLK2_ROOT_GATE_DISABLE;\ 333 type DPSTREAMCLK3_ROOT_GATE_DISABLE;\ 334 type DPSTREAMCLK0_GATE_DISABLE;\ 335 type DPSTREAMCLK1_GATE_DISABLE;\ 336 type DPSTREAMCLK2_GATE_DISABLE;\ 337 type DPSTREAMCLK3_GATE_DISABLE;\ 338 type SYMCLKA_FE_GATE_DISABLE;\ 339 type SYMCLKB_FE_GATE_DISABLE;\ 340 type SYMCLKC_FE_GATE_DISABLE;\ 341 type SYMCLKD_FE_GATE_DISABLE;\ 342 type SYMCLKE_FE_GATE_DISABLE;\ 343 type SYMCLKA_GATE_DISABLE;\ 344 type SYMCLKB_GATE_DISABLE;\ 345 type SYMCLKC_GATE_DISABLE;\ 346 type SYMCLKD_GATE_DISABLE;\ 347 type SYMCLKE_GATE_DISABLE;\ 348 349 350 #define DCCG401_REG_FIELD_LIST(type) \ 351 type OTG0_TMDS_PIXEL_RATE_DIV;\ 352 type DPDTO0_INT;\ 353 type OTG1_TMDS_PIXEL_RATE_DIV;\ 354 type DPDTO1_INT;\ 355 type OTG2_TMDS_PIXEL_RATE_DIV;\ 356 type DPDTO2_INT;\ 357 type OTG3_TMDS_PIXEL_RATE_DIV;\ 358 type DPDTO3_INT;\ 359 type SYMCLK32_ROOT_LE2_GATE_DISABLE;\ 360 type SYMCLK32_ROOT_LE3_GATE_DISABLE;\ 361 type SYMCLK32_LE2_GATE_DISABLE;\ 362 type SYMCLK32_LE3_GATE_DISABLE;\ 363 type SYMCLK32_LE2_SRC_SEL;\ 364 type SYMCLK32_LE3_SRC_SEL;\ 365 type SYMCLK32_LE2_EN;\ 366 type SYMCLK32_LE3_EN;\ 367 type DP_DTO_ENABLE[MAX_PIPES]; 368 369 struct dccg_shift { 370 DCCG_REG_FIELD_LIST(uint8_t) 371 DCCG3_REG_FIELD_LIST(uint8_t) 372 DCCG31_REG_FIELD_LIST(uint8_t) 373 DCCG314_REG_FIELD_LIST(uint8_t) 374 DCCG32_REG_FIELD_LIST(uint8_t) 375 DCCG35_REG_FIELD_LIST(uint8_t) 376 DCCG401_REG_FIELD_LIST(uint8_t) 377 }; 378 379 struct dccg_mask { 380 DCCG_REG_FIELD_LIST(uint32_t) 381 DCCG3_REG_FIELD_LIST(uint32_t) 382 DCCG31_REG_FIELD_LIST(uint32_t) 383 DCCG314_REG_FIELD_LIST(uint32_t) 384 DCCG32_REG_FIELD_LIST(uint32_t) 385 DCCG35_REG_FIELD_LIST(uint32_t) 386 DCCG401_REG_FIELD_LIST(uint32_t) 387 }; 388 389 #define DCCG_REG_VARIABLE_LIST \ 390 uint32_t DPPCLK_DTO_CTRL; \ 391 uint32_t DPPCLK_DTO_PARAM[6]; \ 392 uint32_t REFCLK_CNTL; \ 393 uint32_t DISPCLK_FREQ_CHANGE_CNTL; \ 394 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \ 395 uint32_t HDMICHARCLK_CLOCK_CNTL[6]; \ 396 uint32_t PHYASYMCLK_CLOCK_CNTL; \ 397 uint32_t PHYBSYMCLK_CLOCK_CNTL; \ 398 uint32_t PHYCSYMCLK_CLOCK_CNTL; \ 399 uint32_t PHYDSYMCLK_CLOCK_CNTL; \ 400 uint32_t PHYESYMCLK_CLOCK_CNTL; \ 401 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \ 402 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \ 403 uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; \ 404 uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; \ 405 uint32_t DCCG_AUDIO_DTO_SOURCE; \ 406 uint32_t DPSTREAMCLK_CNTL; \ 407 uint32_t HDMISTREAMCLK_CNTL; \ 408 uint32_t SYMCLK32_SE_CNTL; \ 409 uint32_t SYMCLK32_LE_CNTL; \ 410 uint32_t DENTIST_DISPCLK_CNTL; \ 411 uint32_t DSCCLK_DTO_CTRL; \ 412 uint32_t DSCCLK0_DTO_PARAM; \ 413 uint32_t DSCCLK1_DTO_PARAM; \ 414 uint32_t DSCCLK2_DTO_PARAM; \ 415 uint32_t DSCCLK3_DTO_PARAM; \ 416 uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; \ 417 uint32_t DPSTREAMCLK_GATE_DISABLE; \ 418 uint32_t DCCG_GATE_DISABLE_CNTL; \ 419 uint32_t DCCG_GATE_DISABLE_CNTL2; \ 420 uint32_t DCCG_GATE_DISABLE_CNTL3; \ 421 uint32_t HDMISTREAMCLK0_DTO_PARAM; \ 422 uint32_t DCCG_GATE_DISABLE_CNTL4; \ 423 uint32_t OTG_PIXEL_RATE_DIV; \ 424 uint32_t DTBCLK_P_CNTL; \ 425 uint32_t DPPCLK_CTRL; \ 426 uint32_t DCCG_GATE_DISABLE_CNTL5; \ 427 uint32_t DCCG_GATE_DISABLE_CNTL6; \ 428 uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; \ 429 uint32_t SYMCLKA_CLOCK_ENABLE; \ 430 uint32_t SYMCLKB_CLOCK_ENABLE; \ 431 uint32_t SYMCLKC_CLOCK_ENABLE; \ 432 uint32_t SYMCLKD_CLOCK_ENABLE; \ 433 uint32_t SYMCLKE_CLOCK_ENABLE; \ 434 uint32_t DP_DTO_MODULO[MAX_PIPES]; \ 435 uint32_t DP_DTO_PHASE[MAX_PIPES]; \ 436 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; \ 437 uint32_t DCCG_AUDIO_DTO0_MODULE; \ 438 uint32_t DCCG_AUDIO_DTO0_PHASE; \ 439 uint32_t DCCG_AUDIO_DTO1_MODULE; \ 440 uint32_t DCCG_AUDIO_DTO1_PHASE; \ 441 uint32_t DCCG_CAC_STATUS; \ 442 uint32_t DCCG_CAC_STATUS2; \ 443 uint32_t DCCG_DISP_CNTL_REG; \ 444 uint32_t DCCG_DS_CNTL; \ 445 uint32_t DCCG_DS_DTO_INCR; \ 446 uint32_t DCCG_DS_DTO_MODULO; \ 447 uint32_t DCCG_DS_HW_CAL_INTERVAL; \ 448 uint32_t DCCG_GTC_CNTL; \ 449 uint32_t DCCG_GTC_CURRENT; \ 450 uint32_t DCCG_GTC_DTO_INCR; \ 451 uint32_t DCCG_GTC_DTO_MODULO; \ 452 uint32_t DCCG_PERFMON_CNTL; \ 453 uint32_t DCCG_PERFMON_CNTL2; \ 454 uint32_t DCCG_SOFT_RESET; \ 455 uint32_t DCCG_TEST_CLK_SEL; \ 456 uint32_t DCCG_VSYNC_CNT_CTRL; \ 457 uint32_t DCCG_VSYNC_CNT_INT_CTRL; \ 458 uint32_t DCCG_VSYNC_OTG0_LATCH_VALUE; \ 459 uint32_t DCCG_VSYNC_OTG1_LATCH_VALUE; \ 460 uint32_t DCCG_VSYNC_OTG2_LATCH_VALUE; \ 461 uint32_t DCCG_VSYNC_OTG3_LATCH_VALUE; \ 462 uint32_t DCCG_VSYNC_OTG4_LATCH_VALUE; \ 463 uint32_t DCCG_VSYNC_OTG5_LATCH_VALUE; \ 464 uint32_t DISPCLK_CGTT_BLK_CTRL_REG; \ 465 uint32_t DP_DTO_DBUF_EN; \ 466 uint32_t DPIACLK_540M_DTO_MODULO; \ 467 uint32_t DPIACLK_540M_DTO_PHASE; \ 468 uint32_t DPIACLK_810M_DTO_MODULO; \ 469 uint32_t DPIACLK_810M_DTO_PHASE; \ 470 uint32_t DPIACLK_DTO_CNTL; \ 471 uint32_t DPIASYMCLK_CNTL; \ 472 uint32_t DPPCLK_CGTT_BLK_CTRL_REG; \ 473 uint32_t DPREFCLK_CGTT_BLK_CTRL_REG; \ 474 uint32_t DPREFCLK_CNTL; \ 475 uint32_t DTBCLK_DTO_DBUF_EN; \ 476 uint32_t FORCE_SYMCLK_DISABLE; \ 477 uint32_t HDMICHARCLK0_CLOCK_CNTL; \ 478 uint32_t MICROSECOND_TIME_BASE_DIV; \ 479 uint32_t MILLISECOND_TIME_BASE_DIV; \ 480 uint32_t OTG0_PHYPLL_PIXEL_RATE_CNTL; \ 481 uint32_t OTG0_PIXEL_RATE_CNTL; \ 482 uint32_t OTG1_PHYPLL_PIXEL_RATE_CNTL; \ 483 uint32_t OTG1_PIXEL_RATE_CNTL; \ 484 uint32_t OTG2_PHYPLL_PIXEL_RATE_CNTL; \ 485 uint32_t OTG2_PIXEL_RATE_CNTL; \ 486 uint32_t OTG3_PHYPLL_PIXEL_RATE_CNTL; \ 487 uint32_t OTG3_PIXEL_RATE_CNTL; \ 488 uint32_t PHYPLLA_PIXCLK_RESYNC_CNTL; \ 489 uint32_t PHYPLLB_PIXCLK_RESYNC_CNTL; \ 490 uint32_t PHYPLLC_PIXCLK_RESYNC_CNTL; \ 491 uint32_t PHYPLLD_PIXCLK_RESYNC_CNTL; \ 492 uint32_t PHYPLLE_PIXCLK_RESYNC_CNTL; \ 493 uint32_t REFCLK_CGTT_BLK_CTRL_REG; \ 494 uint32_t SOCCLK_CGTT_BLK_CTRL_REG; \ 495 uint32_t SYMCLK_CGTT_BLK_CTRL_REG; \ 496 uint32_t SYMCLK_PSP_CNTL 497 498 struct dccg_registers { 499 DCCG_REG_VARIABLE_LIST; 500 }; 501 502 struct dcn_dccg { 503 struct dccg base; 504 const struct dccg_registers *regs; 505 const struct dccg_shift *dccg_shift; 506 const struct dccg_mask *dccg_mask; 507 }; 508 509 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk); 510 511 void dccg2_get_dccg_ref_freq(struct dccg *dccg, 512 unsigned int xtalin_freq_inKhz, 513 unsigned int *dccg_ref_freq_inKhz); 514 515 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, 516 bool en); 517 void dccg2_otg_add_pixel(struct dccg *dccg, 518 uint32_t otg_inst); 519 void dccg2_otg_drop_pixel(struct dccg *dccg, 520 uint32_t otg_inst); 521 522 523 void dccg2_init(struct dccg *dccg); 524 525 void dccg2_refclk_setup(struct dccg *dccg); 526 void dccg2_allow_clock_gating(struct dccg *dccg, bool allow); 527 void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable); 528 bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg); 529 530 struct dccg *dccg2_create( 531 struct dc_context *ctx, 532 const struct dccg_registers *regs, 533 const struct dccg_shift *dccg_shift, 534 const struct dccg_mask *dccg_mask); 535 536 void dcn_dccg_destroy(struct dccg **dccg); 537 538 #endif //__DCN20_DCCG_H__ 539