1 /*
2 * QEMU CXL Devices
3 *
4 * Copyright (c) 2020 Intel
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #ifndef CXL_DEVICE_H
11 #define CXL_DEVICE_H
12
13 #include "hw/cxl/cxl_component.h"
14 #include "hw/pci/pci_device.h"
15 #include "hw/register.h"
16 #include "hw/cxl/cxl_events.h"
17
18 /*
19 * The following is how a CXL device's Memory Device registers are laid out.
20 * The only requirement from the spec is that the capabilities array and the
21 * capability headers start at offset 0 and are contiguously packed. The headers
22 * themselves provide offsets to the register fields. For this emulation, the
23 * actual registers * will start at offset 0x80 (m == 0x80). No secondary
24 * mailbox is implemented which means that the offset of the start of the
25 * mailbox payload (n) is given by
26 * n = m + sizeof(mailbox registers) + sizeof(device registers).
27 *
28 * +---------------------------------+
29 * | |
30 * | Memory Device Registers |
31 * | |
32 * n + PAYLOAD_SIZE_MAX -----------------------------------
33 * ^ | |
34 * | | |
35 * | | |
36 * | | |
37 * | | |
38 * | | Mailbox Payload |
39 * | | |
40 * | | |
41 * | | |
42 * n -----------------------------------
43 * ^ | Mailbox Registers |
44 * | | |
45 * | -----------------------------------
46 * | | |
47 * | | Device Registers |
48 * | | |
49 * m ---------------------------------->
50 * ^ | Memory Device Capability Header|
51 * | -----------------------------------
52 * | | Mailbox Capability Header |
53 * | -----------------------------------
54 * | | Device Capability Header |
55 * | -----------------------------------
56 * | | Device Cap Array Register |
57 * 0 +---------------------------------+
58 *
59 */
60
61 /* CXL r3.1 Figure 8-12: CXL Device Registers */
62 #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10
63 /* CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register */
64 #define CXL_DEVICE_CAP_REG_SIZE 0x10
65
66 /*
67 * CXL r3.1 Section 8.2.8.2.1: CXL Device Capabilities +
68 * CXL r3.1 Section 8.2.8.5: Memory Device Capabilities
69 */
70 #define CXL_DEVICE_CAPS_MAX 4
71 #define CXL_CAPS_SIZE \
72 (CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */
73
74 #define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */
75 /*
76 * CXL r3.1 Section 8.2.8.3: Device Status Registers
77 * As it is the only Device Status Register in CXL r3.1
78 */
79 #define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8
80
81 #define CXL_MAILBOX_REGISTERS_OFFSET \
82 (CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH)
83 /* CXL r3.1 Figure 8-13: Mailbox Registers */
84 #define CXL_MAILBOX_REGISTERS_SIZE 0x20
85 #define CXL_MAILBOX_PAYLOAD_SHIFT 11
86 #define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT)
87 #define CXL_MAILBOX_REGISTERS_LENGTH \
88 (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE)
89
90 #define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \
91 (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH)
92 #define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8
93
94 #define CXL_MMIO_SIZE \
95 (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH + \
96 CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH)
97
98 /* CXL r3.1 Table 8-34: Command Return Codes */
99 typedef enum {
100 CXL_MBOX_SUCCESS = 0x0,
101 CXL_MBOX_BG_STARTED = 0x1,
102 CXL_MBOX_INVALID_INPUT = 0x2,
103 CXL_MBOX_UNSUPPORTED = 0x3,
104 CXL_MBOX_INTERNAL_ERROR = 0x4,
105 CXL_MBOX_RETRY_REQUIRED = 0x5,
106 CXL_MBOX_BUSY = 0x6,
107 CXL_MBOX_MEDIA_DISABLED = 0x7,
108 CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8,
109 CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9,
110 CXL_MBOX_FW_AUTH_FAILED = 0xa,
111 CXL_MBOX_FW_INVALID_SLOT = 0xb,
112 CXL_MBOX_FW_ROLLEDBACK = 0xc,
113 CXL_MBOX_FW_REST_REQD = 0xd,
114 CXL_MBOX_INVALID_HANDLE = 0xe,
115 CXL_MBOX_INVALID_PA = 0xf,
116 CXL_MBOX_INJECT_POISON_LIMIT = 0x10,
117 CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11,
118 CXL_MBOX_ABORTED = 0x12,
119 CXL_MBOX_INVALID_SECURITY_STATE = 0x13,
120 CXL_MBOX_INCORRECT_PASSPHRASE = 0x14,
121 CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15,
122 CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16,
123 CXL_MBOX_INVALID_LOG = 0x17,
124 CXL_MBOX_INTERRUPTED = 0x18,
125 CXL_MBOX_UNSUPPORTED_FEATURE_VERSION = 0x19,
126 CXL_MBOX_UNSUPPORTED_FEATURE_SELECTION_VALUE = 0x1a,
127 CXL_MBOX_FEATURE_TRANSFER_IN_PROGRESS = 0x1b,
128 CXL_MBOX_FEATURE_TRANSFER_OUT_OF_ORDER = 0x1c,
129 CXL_MBOX_RESOURCES_EXHAUSTED = 0x1d,
130 CXL_MBOX_INVALID_EXTENT_LIST = 0x1e,
131 CXL_MBOX_TRANSFER_OUT_OF_ORDER = 0x1f,
132 CXL_MBOX_REQUEST_ABORT_NOTSUP = 0x20,
133 CXL_MBOX_MAX = 0x20
134 } CXLRetCode;
135
136 typedef struct CXLCCI CXLCCI;
137 typedef struct cxl_device_state CXLDeviceState;
138 struct cxl_cmd;
139 typedef CXLRetCode (*opcode_handler)(const struct cxl_cmd *cmd,
140 uint8_t *payload_in, size_t len_in,
141 uint8_t *payload_out, size_t *len_out,
142 CXLCCI *cci);
143 struct cxl_cmd {
144 const char *name;
145 opcode_handler handler;
146 ssize_t in;
147 uint16_t effect; /* Reported in CEL */
148 };
149
150 typedef struct CXLEvent {
151 CXLEventRecordRaw data;
152 QSIMPLEQ_ENTRY(CXLEvent) node;
153 } CXLEvent;
154
155 typedef struct CXLEventLog {
156 uint16_t next_handle;
157 uint16_t overflow_err_count;
158 uint64_t first_overflow_timestamp;
159 uint64_t last_overflow_timestamp;
160 bool irq_enabled;
161 int irq_vec;
162 QemuMutex lock;
163 QSIMPLEQ_HEAD(, CXLEvent) events;
164 } CXLEventLog;
165
166 typedef struct CXLCCI {
167 struct cxl_cmd cxl_cmd_set[256][256];
168 struct cel_log {
169 uint16_t opcode;
170 uint16_t effect;
171 } cel_log[1 << 16];
172 size_t cel_size;
173
174 /* background command handling (times in ms) */
175 struct {
176 uint16_t opcode;
177 uint16_t complete_pct;
178 uint16_t ret_code; /* Current value of retcode */
179 bool aborted;
180 uint64_t starttime;
181 /* set by each bg cmd, cleared by the bg_timer when complete */
182 uint64_t runtime;
183 QEMUTimer *timer;
184 QemuMutex lock; /* serializes mbox abort vs timer cb */
185 } bg;
186
187 /* firmware update */
188 struct {
189 uint8_t active_slot;
190 uint8_t staged_slot;
191 bool slot[4];
192 uint8_t curr_action;
193 uint8_t curr_slot;
194 /* handle partial transfers */
195 bool transferring;
196 size_t prev_offset;
197 size_t prev_len;
198 time_t last_partxfer;
199 } fw;
200
201 size_t payload_max;
202 /* Pointer to device hosting the CCI */
203 DeviceState *d;
204 /* Pointer to the device hosting the protocol conversion */
205 DeviceState *intf;
206 bool initialized;
207 } CXLCCI;
208
209 typedef struct cxl_device_state {
210 MemoryRegion device_registers;
211
212 /* CXL r3.1 Section 8.2.8.3: Device Status Registers */
213 struct {
214 MemoryRegion device;
215 union {
216 uint8_t dev_reg_state[CXL_DEVICE_STATUS_REGISTERS_LENGTH];
217 uint16_t dev_reg_state16[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 2];
218 uint32_t dev_reg_state32[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 4];
219 uint64_t dev_reg_state64[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 8];
220 };
221 uint64_t event_status;
222 };
223 MemoryRegion memory_device;
224 struct {
225 MemoryRegion caps;
226 union {
227 uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4];
228 uint64_t caps_reg_state64[CXL_CAPS_SIZE / 8];
229 };
230 };
231
232 /* CXL r3.1 Section 8.2.8.4: Mailbox Registers */
233 struct {
234 MemoryRegion mailbox;
235 uint16_t payload_size;
236 uint8_t mbox_msi_n;
237 union {
238 uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH];
239 uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2];
240 uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4];
241 uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8];
242 };
243 };
244
245 /* Stash the memory device status value */
246 uint64_t memdev_status;
247
248 struct {
249 bool set;
250 uint64_t last_set;
251 uint64_t host_set;
252 } timestamp;
253
254 /* memory region size, HDM */
255 uint64_t static_mem_size;
256 uint64_t pmem_size;
257 uint64_t vmem_size;
258
259 const struct cxl_cmd (*cxl_cmd_set)[256];
260 CXLEventLog event_logs[CXL_EVENT_TYPE_MAX];
261 } CXLDeviceState;
262
263 /* Initialize the register block for a device */
264 void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev,
265 CXLCCI *cci);
266
267 typedef struct CXLType3Dev CXLType3Dev;
268 typedef struct CSWMBCCIDev CSWMBCCIDev;
269 /* Set up default values for the register block */
270 void cxl_device_register_init_t3(CXLType3Dev *ct3d, int msi_n);
271 void cxl_device_register_init_swcci(CSWMBCCIDev *sw, int msi_n);
272
273 /*
274 * CXL r3.1 Section 8.2.8.1: CXL Device Capabilities Array Register
275 * Documented as a 128 bit register, but 64 bit accesses and the second
276 * 64 bits are currently reserved.
277 */
278 REG64(CXL_DEV_CAP_ARRAY, 0)
279 FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16)
280 FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8)
281 FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16)
282
283 void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type,
284 bool available);
285
286 /*
287 * Helper macro to initialize capability headers for CXL devices.
288 *
289 * In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is
290 * listed as a 128b register, but in CXL r3.1 Section 8.2.8: CXL Device Register
291 * Interface, it says:
292 * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that
293 * > is the maximum access size allowed for these registers. If this rule is not
294 * > followed, the behavior is undefined.
295 *
296 * > To illustrate how the fields fit together, the layouts ... are shown as
297 * > wider than a 64 bit register. Implementations are expected to use any size
298 * > accesses for this information up to 64 bits without lost of functionality
299 *
300 * Here we've chosen to make it 4 dwords.
301 */
302 #define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \
303 REG32(CXL_DEV_##n##_CAP_HDR0, offset) \
304 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \
305 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \
306 REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \
307 FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \
308 REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \
309 FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32)
310
311 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET)
312 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
313 CXL_DEVICE_CAP_REG_SIZE)
314 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE,
315 CXL_DEVICE_CAP_HDR1_OFFSET +
316 CXL_DEVICE_CAP_REG_SIZE * 2)
317
318 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max);
319 void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf,
320 DeviceState *d, size_t payload_max);
321 void cxl_init_cci(CXLCCI *cci, size_t payload_max);
322 void cxl_destroy_cci(CXLCCI *cci);
323 void cxl_add_cci_commands(CXLCCI *cci, const struct cxl_cmd (*cxl_cmd_set)[256],
324 size_t payload_max);
325 int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
326 size_t len_in, uint8_t *pl_in,
327 size_t *len_out, uint8_t *pl_out,
328 bool *bg_started);
329 void cxl_initialize_t3_fm_owned_ld_mctpcci(CXLCCI *cci, DeviceState *d,
330 DeviceState *intf,
331 size_t payload_max);
332
333 void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState *d,
334 DeviceState *intf, size_t payload_max);
335
336 #define cxl_device_cap_init(dstate, reg, cap_id, ver) \
337 do { \
338 uint32_t *cap_hdrs = dstate->caps_reg_state32; \
339 int which = R_CXL_DEV_##reg##_CAP_HDR0; \
340 cap_hdrs[which] = \
341 FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, \
342 CAP_ID, cap_id); \
343 cap_hdrs[which] = FIELD_DP32( \
344 cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, ver); \
345 cap_hdrs[which + 1] = \
346 FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \
347 CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \
348 cap_hdrs[which + 2] = \
349 FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \
350 CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \
351 } while (0)
352
353 /* CXL r3.2 Section 8.2.8.3.1: Event Status Register */
354 #define CXL_DEVICE_STATUS_VERSION 2
355 REG64(CXL_DEV_EVENT_STATUS, 0)
356 FIELD(CXL_DEV_EVENT_STATUS, EVENT_STATUS, 0, 32)
357
358 #define CXL_DEV_MAILBOX_VERSION 1
359 /* CXL r3.1 Section 8.2.8.4.3: Mailbox Capabilities Register */
360 REG32(CXL_DEV_MAILBOX_CAP, 0)
361 FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5)
362 FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)
363 FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1)
364 FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4)
365 FIELD(CXL_DEV_MAILBOX_CAP, MBOX_READY_TIME, 11, 8)
366 FIELD(CXL_DEV_MAILBOX_CAP, TYPE, 19, 4)
367
368 /* CXL r3.1 Section 8.2.8.4.4: Mailbox Control Register */
369 REG32(CXL_DEV_MAILBOX_CTRL, 4)
370 FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1)
371 FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1)
372 FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1)
373
374 /* CXL r3.1 Section 8.2.8.4.5: Command Register */
375 REG64(CXL_DEV_MAILBOX_CMD, 8)
376 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8)
377 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8)
378 FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20)
379
380 /* CXL r3.1 Section 8.2.8.4.6: Mailbox Status Register */
381 REG64(CXL_DEV_MAILBOX_STS, 0x10)
382 FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1)
383 FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16)
384 FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16)
385
386 /* CXL r3.1 Section 8.2.8.4.7: Background Command Status Register */
387 REG64(CXL_DEV_BG_CMD_STS, 0x18)
388 FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16)
389 FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7)
390 FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16)
391 FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16)
392
393 /* CXL r3.1 Section 8.2.8.4.8: Command Payload Registers */
394 REG32(CXL_DEV_CMD_PAYLOAD, 0x20)
395
396 /* CXL r3.1 Section 8.2.8.4.1: Memory Device Status Registers */
397 #define CXL_MEM_DEV_STATUS_VERSION 1
398 REG64(CXL_MEM_DEV_STS, 0)
399 FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1)
400 FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1)
401 FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2)
402 FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
403 FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
404
__toggle_media(CXLDeviceState * cxl_dstate,int val)405 static inline void __toggle_media(CXLDeviceState *cxl_dstate, int val)
406 {
407 uint64_t dev_status_reg;
408
409 dev_status_reg = cxl_dstate->memdev_status;
410 dev_status_reg = FIELD_DP64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS,
411 val);
412 cxl_dstate->memdev_status = dev_status_reg;
413 }
414 #define cxl_dev_disable_media(cxlds) \
415 do { __toggle_media((cxlds), 0x3); } while (0)
416 #define cxl_dev_enable_media(cxlds) \
417 do { __toggle_media((cxlds), 0x1); } while (0)
418
cxl_dev_media_disabled(CXLDeviceState * cxl_dstate)419 static inline bool cxl_dev_media_disabled(CXLDeviceState *cxl_dstate)
420 {
421 uint64_t dev_status_reg = cxl_dstate->mbox_reg_state64[R_CXL_MEM_DEV_STS];
422 return FIELD_EX64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS) == 0x3;
423 }
scan_media_running(CXLCCI * cci)424 static inline bool scan_media_running(CXLCCI *cci)
425 {
426 return !!cci->bg.runtime && cci->bg.opcode == 0x4304;
427 }
428
429 typedef struct CXLError {
430 QTAILQ_ENTRY(CXLError) node;
431 int type; /* Error code as per FE definition */
432 uint32_t header[CXL_RAS_ERR_HEADER_NUM];
433 } CXLError;
434
435 typedef QTAILQ_HEAD(, CXLError) CXLErrorList;
436
437 typedef struct CXLPoison {
438 uint64_t start, length;
439 uint8_t type;
440 #define CXL_POISON_TYPE_EXTERNAL 0x1
441 #define CXL_POISON_TYPE_INTERNAL 0x2
442 #define CXL_POISON_TYPE_INJECTED 0x3
443 QLIST_ENTRY(CXLPoison) node;
444 } CXLPoison;
445
446 typedef QLIST_HEAD(, CXLPoison) CXLPoisonList;
447 #define CXL_POISON_LIST_LIMIT 256
448
449 /* CXL memory device patrol scrub control attributes */
450 typedef struct CXLMemPatrolScrubReadAttrs {
451 uint8_t scrub_cycle_cap;
452 uint16_t scrub_cycle;
453 uint8_t scrub_flags;
454 } QEMU_PACKED CXLMemPatrolScrubReadAttrs;
455
456 typedef struct CXLMemPatrolScrubWriteAttrs {
457 uint8_t scrub_cycle_hr;
458 uint8_t scrub_flags;
459 } QEMU_PACKED CXLMemPatrolScrubWriteAttrs;
460
461 #define CXL_MEMDEV_PS_GET_FEATURE_VERSION 0x01
462 #define CXL_MEMDEV_PS_SET_FEATURE_VERSION 0x01
463 #define CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT BIT(0)
464 #define CXL_MEMDEV_PS_SCRUB_REALTIME_REPORT_CAP_DEFAULT BIT(1)
465 #define CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_DEFAULT 12
466 #define CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_DEFAULT 1
467 #define CXL_MEMDEV_PS_ENABLE_DEFAULT 0
468
469 /* CXL memory device DDR5 ECS control attributes */
470 #define CXL_ECS_GET_FEATURE_VERSION 0x01
471 #define CXL_ECS_SET_FEATURE_VERSION 0x01
472 #define CXL_ECS_LOG_ENTRY_TYPE_DEFAULT 0x01
473 #define CXL_ECS_REALTIME_REPORT_CAP_DEFAULT 1
474 #define CXL_ECS_THRESHOLD_COUNT_DEFAULT 3 /* 3: 256, 4: 1024, 5: 4096 */
475 #define CXL_ECS_MODE_DEFAULT 0
476 #define CXL_ECS_NUM_MEDIA_FRUS 3 /* Default */
477
478 typedef struct CXLMemECSFRUReadAttrs {
479 uint8_t ecs_cap;
480 uint16_t ecs_config;
481 uint8_t ecs_flags;
482 } QEMU_PACKED CXLMemECSFRUReadAttrs;
483
484 typedef struct CXLMemECSReadAttrs {
485 uint8_t ecs_log_cap;
486 CXLMemECSFRUReadAttrs fru_attrs[CXL_ECS_NUM_MEDIA_FRUS];
487 } QEMU_PACKED CXLMemECSReadAttrs;
488
489 typedef struct CXLMemECSFRUWriteAttrs {
490 uint16_t ecs_config;
491 } QEMU_PACKED CXLMemECSFRUWriteAttrs;
492
493 typedef struct CXLMemECSWriteAttrs {
494 uint8_t ecs_log_cap;
495 CXLMemECSFRUWriteAttrs fru_attrs[CXL_ECS_NUM_MEDIA_FRUS];
496 } QEMU_PACKED CXLMemECSWriteAttrs;
497
498 #define DCD_MAX_NUM_REGION 8
499
500 typedef struct CXLDCExtentRaw {
501 uint64_t start_dpa;
502 uint64_t len;
503 uint8_t tag[0x10];
504 uint16_t shared_seq;
505 uint8_t rsvd[0x6];
506 } QEMU_PACKED CXLDCExtentRaw;
507
508 typedef struct CXLDCExtent {
509 uint64_t start_dpa;
510 uint64_t len;
511 uint8_t tag[0x10];
512 uint16_t shared_seq;
513 uint8_t rsvd[0x6];
514
515 QTAILQ_ENTRY(CXLDCExtent) node;
516 } CXLDCExtent;
517 typedef QTAILQ_HEAD(, CXLDCExtent) CXLDCExtentList;
518
519 typedef struct CXLDCExtentGroup {
520 CXLDCExtentList list;
521 QTAILQ_ENTRY(CXLDCExtentGroup) node;
522 } CXLDCExtentGroup;
523 typedef QTAILQ_HEAD(, CXLDCExtentGroup) CXLDCExtentGroupList;
524
525 typedef struct CXLDCRegion {
526 uint64_t base; /* aligned to 256*MiB */
527 uint64_t decode_len; /* aligned to 256*MiB */
528 uint64_t len;
529 uint64_t block_size;
530 uint32_t dsmadhandle;
531 uint8_t flags;
532 unsigned long *blk_bitmap;
533 } CXLDCRegion;
534
535 typedef struct CXLSetFeatureInfo {
536 QemuUUID uuid;
537 uint8_t data_transfer_flag;
538 bool data_saved_across_reset;
539 uint16_t data_offset;
540 size_t data_size;
541 } CXLSetFeatureInfo;
542
543 struct CXLSanitizeInfo;
544
545 typedef struct CXLAlertConfig {
546 uint8_t valid_alerts;
547 uint8_t enable_alerts;
548 uint8_t life_used_crit_alert_thresh;
549 uint8_t life_used_warn_thresh;
550 uint16_t over_temp_crit_alert_thresh;
551 uint16_t under_temp_crit_alert_thresh;
552 uint16_t over_temp_warn_thresh;
553 uint16_t under_temp_warn_thresh;
554 uint16_t cor_vmem_err_warn_thresh;
555 uint16_t cor_pmem_err_warn_thresh;
556 } QEMU_PACKED CXLAlertConfig;
557
558 struct CXLType3Dev {
559 /* Private */
560 PCIDevice parent_obj;
561
562 /* Properties */
563 HostMemoryBackend *hostmem; /* deprecated */
564 HostMemoryBackend *hostvmem;
565 HostMemoryBackend *hostpmem;
566 HostMemoryBackend *lsa;
567 uint64_t sn;
568
569 /* State */
570 AddressSpace hostvmem_as;
571 AddressSpace hostpmem_as;
572 CXLComponentState cxl_cstate;
573 CXLDeviceState cxl_dstate;
574 CXLCCI cci; /* Primary PCI mailbox CCI */
575 /* Always initialized as no way to know if a VDM might show up */
576 CXLCCI vdm_fm_owned_ld_mctp_cci;
577 CXLCCI ld0_cci;
578
579 CXLAlertConfig alert_config;
580
581 /* PCIe link characteristics */
582 PCIExpLinkSpeed speed;
583 PCIExpLinkWidth width;
584
585 /* DOE */
586 DOECap doe_cdat;
587
588 /* Error injection */
589 CXLErrorList error_list;
590
591 /* Poison Injection - cache */
592 CXLPoisonList poison_list;
593 unsigned int poison_list_cnt;
594 bool poison_list_overflowed;
595 uint64_t poison_list_overflow_ts;
596 /* Poison Injection - backup */
597 CXLPoisonList poison_list_bkp;
598 CXLPoisonList scan_media_results;
599 bool scan_media_hasrun;
600
601 CXLSetFeatureInfo set_feat_info;
602
603 /* Patrol scrub control attributes */
604 CXLMemPatrolScrubReadAttrs patrol_scrub_attrs;
605 CXLMemPatrolScrubWriteAttrs patrol_scrub_wr_attrs;
606 /* ECS control attributes */
607 CXLMemECSReadAttrs ecs_attrs;
608 CXLMemECSWriteAttrs ecs_wr_attrs;
609
610 struct dynamic_capacity {
611 HostMemoryBackend *host_dc;
612 AddressSpace host_dc_as;
613 /*
614 * total_capacity is equivalent to the dynamic capability
615 * memory region size.
616 */
617 uint64_t total_capacity; /* 256M aligned */
618 CXLDCExtentList extents;
619 CXLDCExtentGroupList extents_pending;
620 uint32_t total_extent_count;
621 uint32_t ext_list_gen_seq;
622
623 uint8_t num_regions; /* 0-8 regions */
624 CXLDCRegion regions[DCD_MAX_NUM_REGION];
625 } dc;
626
627 struct CXLSanitizeInfo *media_op_sanitize;
628 };
629
630 #define TYPE_CXL_TYPE3 "cxl-type3"
631 OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3)
632
633 struct CXLType3Class {
634 /* Private */
635 PCIDeviceClass parent_class;
636
637 /* public */
638 uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
639
640 uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size,
641 uint64_t offset);
642 void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,
643 uint64_t offset);
644 bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset,
645 uint8_t *data);
646 };
647
648 struct CSWMBCCIDev {
649 PCIDevice parent_obj;
650 PCIDevice *target;
651 CXLComponentState cxl_cstate;
652 CXLDeviceState cxl_dstate;
653 CXLCCI *cci;
654 };
655
656 #define TYPE_CXL_SWITCH_MAILBOX_CCI "cxl-switch-mailbox-cci"
657 OBJECT_DECLARE_TYPE(CSWMBCCIDev, CSWMBCCIClass, CXL_SWITCH_MAILBOX_CCI)
658
659 MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
660 unsigned size, MemTxAttrs attrs);
661 MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
662 unsigned size, MemTxAttrs attrs);
663
664 uint64_t cxl_device_get_timestamp(CXLDeviceState *cxlds);
665
666 void cxl_event_init(CXLDeviceState *cxlds, int start_msg_num);
667 bool cxl_event_insert(CXLDeviceState *cxlds, CXLEventLogType log_type,
668 CXLEventRecordRaw *event);
669 CXLRetCode cxl_event_get_records(CXLDeviceState *cxlds, CXLGetEventPayload *pl,
670 uint8_t log_type, int max_recs,
671 size_t *len);
672 CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds,
673 CXLClearEventPayload *pl);
674 void cxl_discard_all_event_records(CXLDeviceState *cxlds);
675
676 void cxl_event_irq_assert(CXLType3Dev *ct3d);
677
678 void cxl_set_poison_list_overflowed(CXLType3Dev *ct3d);
679 void cxl_clear_poison_list_overflowed(CXLType3Dev *ct3d);
680
681 CXLDCRegion *cxl_find_dc_region(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len);
682
683 void cxl_remove_extent_from_extent_list(CXLDCExtentList *list,
684 CXLDCExtent *extent);
685 void cxl_insert_extent_to_extent_list(CXLDCExtentList *list, uint64_t dpa,
686 uint64_t len, uint8_t *tag,
687 uint16_t shared_seq);
688 bool test_any_bits_set(const unsigned long *addr, unsigned long nr,
689 unsigned long size);
690 bool cxl_extents_contains_dpa_range(CXLDCExtentList *list,
691 uint64_t dpa, uint64_t len);
692 CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,
693 uint64_t dpa,
694 uint64_t len,
695 uint8_t *tag,
696 uint16_t shared_seq);
697 void cxl_extent_group_list_insert_tail(CXLDCExtentGroupList *list,
698 CXLDCExtentGroup *group);
699 void cxl_extent_group_list_delete_front(CXLDCExtentGroupList *list);
700 void ct3_set_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
701 uint64_t len);
702 void ct3_clear_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
703 uint64_t len);
704 bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
705 uint64_t len);
706 #endif
707