1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * QEMU LoongArch CPU
4 *
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
6 */
7
8 #ifndef LOONGARCH_CPU_H
9 #define LOONGARCH_CPU_H
10
11 #include "qemu/int128.h"
12 #include "exec/cpu-common.h"
13 #include "exec/cpu-defs.h"
14 #include "exec/cpu-interrupt.h"
15 #include "fpu/softfloat-types.h"
16 #include "hw/registerfields.h"
17 #include "qemu/timer.h"
18 #ifndef CONFIG_USER_ONLY
19 #include "system/memory.h"
20 #endif
21 #include "cpu-csr.h"
22 #include "cpu-qom.h"
23
24 #define IOCSRF_TEMP 0
25 #define IOCSRF_NODECNT 1
26 #define IOCSRF_MSI 2
27 #define IOCSRF_EXTIOI 3
28 #define IOCSRF_CSRIPI 4
29 #define IOCSRF_FREQCSR 5
30 #define IOCSRF_FREQSCALE 6
31 #define IOCSRF_DVFSV1 7
32 #define IOCSRF_GMOD 9
33 #define IOCSRF_VM 11
34
35 #define VERSION_REG 0x0
36 #define FEATURE_REG 0x8
37 #define VENDOR_REG 0x10
38 #define CPUNAME_REG 0x20
39 #define MISC_FUNC_REG 0x420
40 #define IOCSRM_EXTIOI_EN 48
41 #define IOCSRM_EXTIOI_INT_ENCODE 49
42
43 #define IOCSR_MEM_SIZE 0x428
44
45 #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */
46 #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */
47 #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */
48 #define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */
49
50 FIELD(FCSR0, ENABLES, 0, 5)
51 FIELD(FCSR0, RM, 8, 2)
52 FIELD(FCSR0, FLAGS, 16, 5)
53 FIELD(FCSR0, CAUSE, 24, 5)
54
55 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE)
56 #define SET_FP_CAUSE(REG, V) \
57 do { \
58 (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
59 } while (0)
60 #define UPDATE_FP_CAUSE(REG, V) \
61 do { \
62 (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \
63 } while (0)
64
65 #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES)
66 #define SET_FP_ENABLES(REG, V) \
67 do { \
68 (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
69 } while (0)
70
71 #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS)
72 #define SET_FP_FLAGS(REG, V) \
73 do { \
74 (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
75 } while (0)
76
77 #define UPDATE_FP_FLAGS(REG, V) \
78 do { \
79 (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
80 } while (0)
81
82 #define FP_INEXACT 1
83 #define FP_UNDERFLOW 2
84 #define FP_OVERFLOW 4
85 #define FP_DIV0 8
86 #define FP_INVALID 16
87
88 #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
89 #define EXCODE_MCODE(code) ( (code) & 0x3f )
90 #define EXCODE_SUBCODE(code) ( (code) >> 6 )
91
92 #define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
93 #define EXCCODE_INT EXCODE(0, 0)
94 #define EXCCODE_PIL EXCODE(1, 0)
95 #define EXCCODE_PIS EXCODE(2, 0)
96 #define EXCCODE_PIF EXCODE(3, 0)
97 #define EXCCODE_PME EXCODE(4, 0)
98 #define EXCCODE_PNR EXCODE(5, 0)
99 #define EXCCODE_PNX EXCODE(6, 0)
100 #define EXCCODE_PPI EXCODE(7, 0)
101 #define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */
102 #define EXCCODE_ADEM EXCODE(8, 1)
103 #define EXCCODE_ALE EXCODE(9, 0)
104 #define EXCCODE_BCE EXCODE(10, 0)
105 #define EXCCODE_SYS EXCODE(11, 0)
106 #define EXCCODE_BRK EXCODE(12, 0)
107 #define EXCCODE_INE EXCODE(13, 0)
108 #define EXCCODE_IPE EXCODE(14, 0)
109 #define EXCCODE_FPD EXCODE(15, 0)
110 #define EXCCODE_SXD EXCODE(16, 0)
111 #define EXCCODE_ASXD EXCODE(17, 0)
112 #define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */
113 #define EXCCODE_VFPE EXCODE(18, 1)
114 #define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */
115 #define EXCCODE_WPEM EXCODE(19, 1)
116 #define EXCCODE_BTD EXCODE(20, 0)
117 #define EXCCODE_BTE EXCODE(21, 0)
118 #define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */
119
120 /* cpucfg[0] bits */
121 FIELD(CPUCFG0, PRID, 0, 32)
122
123 /* cpucfg[1] bits */
124 FIELD(CPUCFG1, ARCH, 0, 2)
125 FIELD(CPUCFG1, PGMMU, 2, 1)
126 FIELD(CPUCFG1, IOCSR, 3, 1)
127 FIELD(CPUCFG1, PALEN, 4, 8)
128 FIELD(CPUCFG1, VALEN, 12, 8)
129 FIELD(CPUCFG1, UAL, 20, 1)
130 FIELD(CPUCFG1, RI, 21, 1)
131 FIELD(CPUCFG1, EP, 22, 1)
132 FIELD(CPUCFG1, RPLV, 23, 1)
133 FIELD(CPUCFG1, HP, 24, 1)
134 FIELD(CPUCFG1, CRC, 25, 1)
135 FIELD(CPUCFG1, MSG_INT, 26, 1)
136
137 /* cpucfg[1].arch */
138 #define CPUCFG1_ARCH_LA32R 0
139 #define CPUCFG1_ARCH_LA32 1
140 #define CPUCFG1_ARCH_LA64 2
141
142 /* cpucfg[2] bits */
143 FIELD(CPUCFG2, FP, 0, 1)
144 FIELD(CPUCFG2, FP_SP, 1, 1)
145 FIELD(CPUCFG2, FP_DP, 2, 1)
146 FIELD(CPUCFG2, FP_VER, 3, 3)
147 FIELD(CPUCFG2, LSX, 6, 1)
148 FIELD(CPUCFG2, LASX, 7, 1)
149 FIELD(CPUCFG2, COMPLEX, 8, 1)
150 FIELD(CPUCFG2, CRYPTO, 9, 1)
151 FIELD(CPUCFG2, LVZ, 10, 1)
152 FIELD(CPUCFG2, LVZ_VER, 11, 3)
153 FIELD(CPUCFG2, LLFTP, 14, 1)
154 FIELD(CPUCFG2, LLFTP_VER, 15, 3)
155 FIELD(CPUCFG2, LBT_X86, 18, 1)
156 FIELD(CPUCFG2, LBT_ARM, 19, 1)
157 FIELD(CPUCFG2, LBT_MIPS, 20, 1)
158 FIELD(CPUCFG2, LBT_ALL, 18, 3)
159 FIELD(CPUCFG2, LSPW, 21, 1)
160 FIELD(CPUCFG2, LAM, 22, 1)
161
162 /* cpucfg[3] bits */
163 FIELD(CPUCFG3, CCDMA, 0, 1)
164 FIELD(CPUCFG3, SFB, 1, 1)
165 FIELD(CPUCFG3, UCACC, 2, 1)
166 FIELD(CPUCFG3, LLEXC, 3, 1)
167 FIELD(CPUCFG3, SCDLY, 4, 1)
168 FIELD(CPUCFG3, LLDBAR, 5, 1)
169 FIELD(CPUCFG3, ITLBHMC, 6, 1)
170 FIELD(CPUCFG3, ICHMC, 7, 1)
171 FIELD(CPUCFG3, SPW_LVL, 8, 3)
172 FIELD(CPUCFG3, SPW_HP_HF, 11, 1)
173 FIELD(CPUCFG3, RVA, 12, 1)
174 FIELD(CPUCFG3, RVAMAX, 13, 4)
175
176 /* cpucfg[4] bits */
177 FIELD(CPUCFG4, CC_FREQ, 0, 32)
178
179 /* cpucfg[5] bits */
180 FIELD(CPUCFG5, CC_MUL, 0, 16)
181 FIELD(CPUCFG5, CC_DIV, 16, 16)
182
183 /* cpucfg[6] bits */
184 FIELD(CPUCFG6, PMP, 0, 1)
185 FIELD(CPUCFG6, PMVER, 1, 3)
186 FIELD(CPUCFG6, PMNUM, 4, 4)
187 FIELD(CPUCFG6, PMBITS, 8, 6)
188 FIELD(CPUCFG6, UPM, 14, 1)
189
190 /* cpucfg[16] bits */
191 FIELD(CPUCFG16, L1_IUPRE, 0, 1)
192 FIELD(CPUCFG16, L1_IUUNIFY, 1, 1)
193 FIELD(CPUCFG16, L1_DPRE, 2, 1)
194 FIELD(CPUCFG16, L2_IUPRE, 3, 1)
195 FIELD(CPUCFG16, L2_IUUNIFY, 4, 1)
196 FIELD(CPUCFG16, L2_IUPRIV, 5, 1)
197 FIELD(CPUCFG16, L2_IUINCL, 6, 1)
198 FIELD(CPUCFG16, L2_DPRE, 7, 1)
199 FIELD(CPUCFG16, L2_DPRIV, 8, 1)
200 FIELD(CPUCFG16, L2_DINCL, 9, 1)
201 FIELD(CPUCFG16, L3_IUPRE, 10, 1)
202 FIELD(CPUCFG16, L3_IUUNIFY, 11, 1)
203 FIELD(CPUCFG16, L3_IUPRIV, 12, 1)
204 FIELD(CPUCFG16, L3_IUINCL, 13, 1)
205 FIELD(CPUCFG16, L3_DPRE, 14, 1)
206 FIELD(CPUCFG16, L3_DPRIV, 15, 1)
207 FIELD(CPUCFG16, L3_DINCL, 16, 1)
208
209 /* cpucfg[17] bits */
210 FIELD(CPUCFG17, L1IU_WAYS, 0, 16)
211 FIELD(CPUCFG17, L1IU_SETS, 16, 8)
212 FIELD(CPUCFG17, L1IU_SIZE, 24, 7)
213
214 /* cpucfg[18] bits */
215 FIELD(CPUCFG18, L1D_WAYS, 0, 16)
216 FIELD(CPUCFG18, L1D_SETS, 16, 8)
217 FIELD(CPUCFG18, L1D_SIZE, 24, 7)
218
219 /* cpucfg[19] bits */
220 FIELD(CPUCFG19, L2IU_WAYS, 0, 16)
221 FIELD(CPUCFG19, L2IU_SETS, 16, 8)
222 FIELD(CPUCFG19, L2IU_SIZE, 24, 7)
223
224 /* cpucfg[20] bits */
225 FIELD(CPUCFG20, L3IU_WAYS, 0, 16)
226 FIELD(CPUCFG20, L3IU_SETS, 16, 8)
227 FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
228
229 /*CSR_CRMD */
230 FIELD(CSR_CRMD, PLV, 0, 2)
231 FIELD(CSR_CRMD, IE, 2, 1)
232 FIELD(CSR_CRMD, DA, 3, 1)
233 FIELD(CSR_CRMD, PG, 4, 1)
234 FIELD(CSR_CRMD, DATF, 5, 2)
235 FIELD(CSR_CRMD, DATM, 7, 2)
236 FIELD(CSR_CRMD, WE, 9, 1)
237
238 extern const char * const regnames[32];
239 extern const char * const fregnames[32];
240
241 #define N_IRQS 13
242 #define IRQ_TIMER 11
243 #define IRQ_IPI 12
244
245 #define LOONGARCH_STLB 2048 /* 2048 STLB */
246 #define LOONGARCH_MTLB 64 /* 64 MTLB */
247 #define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB)
248
249 /*
250 * define the ASID PS E VPPN field of TLB
251 */
252 FIELD(TLB_MISC, E, 0, 1)
253 FIELD(TLB_MISC, ASID, 1, 10)
254 FIELD(TLB_MISC, VPPN, 13, 35)
255 FIELD(TLB_MISC, PS, 48, 6)
256
257 #define LSX_LEN (128)
258 #define LASX_LEN (256)
259
260 typedef union VReg {
261 int8_t B[LASX_LEN / 8];
262 int16_t H[LASX_LEN / 16];
263 int32_t W[LASX_LEN / 32];
264 int64_t D[LASX_LEN / 64];
265 uint8_t UB[LASX_LEN / 8];
266 uint16_t UH[LASX_LEN / 16];
267 uint32_t UW[LASX_LEN / 32];
268 uint64_t UD[LASX_LEN / 64];
269 Int128 Q[LASX_LEN / 128];
270 } VReg;
271
272 typedef union fpr_t fpr_t;
273 union fpr_t {
274 VReg vreg;
275 };
276
277 #ifdef CONFIG_TCG
278 struct LoongArchTLB {
279 uint64_t tlb_misc;
280 /* Fields corresponding to CSR_TLBELO0/1 */
281 uint64_t tlb_entry0;
282 uint64_t tlb_entry1;
283 };
284 typedef struct LoongArchTLB LoongArchTLB;
285 #endif
286
287 enum loongarch_features {
288 LOONGARCH_FEATURE_LSX,
289 LOONGARCH_FEATURE_LASX,
290 LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
291 LOONGARCH_FEATURE_PMU,
292 LOONGARCH_FEATURE_PV_IPI,
293 LOONGARCH_FEATURE_STEALTIME,
294 };
295
296 typedef struct LoongArchBT {
297 /* scratch registers */
298 uint64_t scr0;
299 uint64_t scr1;
300 uint64_t scr2;
301 uint64_t scr3;
302 /* loongarch eflags */
303 uint32_t eflags;
304 uint32_t ftop;
305 } lbt_t;
306
307 typedef struct CPUArchState {
308 uint64_t gpr[32];
309 uint64_t pc;
310
311 fpr_t fpr[32];
312 bool cf[8];
313 uint32_t fcsr0;
314 lbt_t lbt;
315
316 uint32_t cpucfg[21];
317 uint32_t pv_features;
318
319 /* LoongArch CSRs */
320 uint64_t CSR_CRMD;
321 uint64_t CSR_PRMD;
322 uint64_t CSR_EUEN;
323 uint64_t CSR_MISC;
324 uint64_t CSR_ECFG;
325 uint64_t CSR_ESTAT;
326 uint64_t CSR_ERA;
327 uint64_t CSR_BADV;
328 uint64_t CSR_BADI;
329 uint64_t CSR_EENTRY;
330 uint64_t CSR_TLBIDX;
331 uint64_t CSR_TLBEHI;
332 uint64_t CSR_TLBELO0;
333 uint64_t CSR_TLBELO1;
334 uint64_t CSR_ASID;
335 uint64_t CSR_PGDL;
336 uint64_t CSR_PGDH;
337 uint64_t CSR_PGD;
338 uint64_t CSR_PWCL;
339 uint64_t CSR_PWCH;
340 uint64_t CSR_STLBPS;
341 uint64_t CSR_RVACFG;
342 uint64_t CSR_CPUID;
343 uint64_t CSR_PRCFG1;
344 uint64_t CSR_PRCFG2;
345 uint64_t CSR_PRCFG3;
346 uint64_t CSR_SAVE[16];
347 uint64_t CSR_TID;
348 uint64_t CSR_TCFG;
349 uint64_t CSR_TVAL;
350 uint64_t CSR_CNTC;
351 uint64_t CSR_TICLR;
352 uint64_t CSR_LLBCTL;
353 uint64_t CSR_IMPCTL1;
354 uint64_t CSR_IMPCTL2;
355 uint64_t CSR_TLBRENTRY;
356 uint64_t CSR_TLBRBADV;
357 uint64_t CSR_TLBRERA;
358 uint64_t CSR_TLBRSAVE;
359 uint64_t CSR_TLBRELO0;
360 uint64_t CSR_TLBRELO1;
361 uint64_t CSR_TLBREHI;
362 uint64_t CSR_TLBRPRMD;
363 uint64_t CSR_MERRCTL;
364 uint64_t CSR_MERRINFO1;
365 uint64_t CSR_MERRINFO2;
366 uint64_t CSR_MERRENTRY;
367 uint64_t CSR_MERRERA;
368 uint64_t CSR_MERRSAVE;
369 uint64_t CSR_CTAG;
370 uint64_t CSR_DMW[4];
371 uint64_t CSR_DBG;
372 uint64_t CSR_DERA;
373 uint64_t CSR_DSAVE;
374 struct {
375 uint64_t guest_addr;
376 } stealtime;
377
378 #ifdef CONFIG_TCG
379 float_status fp_status;
380 uint32_t fcsr0_mask;
381 uint64_t lladdr; /* LL virtual address compared against SC */
382 uint64_t llval;
383 #endif
384 #ifndef CONFIG_USER_ONLY
385 #ifdef CONFIG_TCG
386 LoongArchTLB tlb[LOONGARCH_TLB_MAX];
387 #endif
388
389 AddressSpace *address_space_iocsr;
390 bool load_elf;
391 uint64_t elf_address;
392 uint32_t mp_state;
393
394 struct loongarch_boot_info *boot_info;
395 #endif
396 } CPULoongArchState;
397
398 typedef struct LoongArchCPUTopo {
399 int32_t socket_id; /* socket-id of this VCPU */
400 int32_t core_id; /* core-id of this VCPU */
401 int32_t thread_id; /* thread-id of this VCPU */
402 } LoongArchCPUTopo;
403
404 /**
405 * LoongArchCPU:
406 * @env: #CPULoongArchState
407 *
408 * A LoongArch CPU.
409 */
410 struct ArchCPU {
411 CPUState parent_obj;
412
413 CPULoongArchState env;
414 QEMUTimer timer;
415 uint32_t phy_id;
416 OnOffAuto lbt;
417 OnOffAuto pmu;
418 OnOffAuto lsx;
419 OnOffAuto lasx;
420 OnOffAuto kvm_pv_ipi;
421 OnOffAuto kvm_steal_time;
422 int32_t socket_id; /* socket-id of this CPU */
423 int32_t core_id; /* core-id of this CPU */
424 int32_t thread_id; /* thread-id of this CPU */
425 int32_t node_id; /* NUMA node of this CPU */
426
427 /* 'compatible' string for this CPU for Linux device trees */
428 const char *dtb_compatible;
429 /* used by KVM_REG_LOONGARCH_COUNTER ioctl to access guest time counters */
430 uint64_t kvm_state_counter;
431 VMChangeStateEntry *vmsentry;
432 };
433
434 /**
435 * LoongArchCPUClass:
436 * @parent_realize: The parent class' realize handler.
437 * @parent_phases: The parent class' reset phase handlers.
438 *
439 * A LoongArch CPU model.
440 */
441 struct LoongArchCPUClass {
442 CPUClass parent_class;
443
444 DeviceRealize parent_realize;
445 DeviceUnrealize parent_unrealize;
446 ResettablePhases parent_phases;
447 };
448
449 /*
450 * LoongArch CPUs has 4 privilege levels.
451 * 0 for kernel mode, 3 for user mode.
452 * Define an extra index for DA(direct addressing) mode.
453 */
454 #define MMU_PLV_KERNEL 0
455 #define MMU_PLV_USER 3
456 #define MMU_KERNEL_IDX MMU_PLV_KERNEL
457 #define MMU_USER_IDX MMU_PLV_USER
458 #define MMU_DA_IDX 4
459
is_la64(CPULoongArchState * env)460 static inline bool is_la64(CPULoongArchState *env)
461 {
462 return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
463 }
464
is_va32(CPULoongArchState * env)465 static inline bool is_va32(CPULoongArchState *env)
466 {
467 /* VA32 if !LA64 or VA32L[1-3] */
468 bool va32 = !is_la64(env);
469 uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
470 if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) {
471 va32 = true;
472 }
473 return va32;
474 }
475
set_pc(CPULoongArchState * env,uint64_t value)476 static inline void set_pc(CPULoongArchState *env, uint64_t value)
477 {
478 if (is_va32(env)) {
479 env->pc = (uint32_t)value;
480 } else {
481 env->pc = value;
482 }
483 }
484
485 /*
486 * LoongArch CPUs hardware flags.
487 */
488 #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */
489 #define HW_FLAGS_EUEN_FPE 0x04
490 #define HW_FLAGS_EUEN_SXE 0x08
491 #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
492 #define HW_FLAGS_VA32 0x20
493 #define HW_FLAGS_EUEN_ASXE 0x40
494
495 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
496
497 void loongarch_cpu_post_init(Object *obj);
498
499 #ifdef CONFIG_KVM
500 void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu);
501 #else
kvm_loongarch_cpu_post_init(LoongArchCPU * cpu)502 static inline void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu)
503 {
504 }
505 #endif
506
507 #endif /* LOONGARCH_CPU_H */
508