xref: /linux/drivers/net/ethernet/renesas/ravb.h (revision 8f7aa3d3c7323f4ca2768a9e74ebbe359c4f8f88) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Renesas Ethernet AVB device driver
3  *
4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
5  * Copyright (C) 2015 Renesas Solutions Corp.
6  * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7  *
8  * Based on the SuperH Ethernet driver
9  */
10 
11 #ifndef __RAVB_H__
12 #define __RAVB_H__
13 
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <linux/mdio-bitbang.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/ptp_clock_kernel.h>
22 #include <net/page_pool/types.h>
23 
24 #define BE_TX_RING_SIZE	64	/* TX ring size for Best Effort */
25 #define BE_RX_RING_SIZE	1024	/* RX ring size for Best Effort */
26 #define NC_TX_RING_SIZE	64	/* TX ring size for Network Control */
27 #define NC_RX_RING_SIZE	64	/* RX ring size for Network Control */
28 #define BE_TX_RING_MIN	64
29 #define BE_RX_RING_MIN	64
30 #define BE_TX_RING_MAX	1024
31 #define BE_RX_RING_MAX	2048
32 
33 #define PKT_BUF_SZ	1538
34 
35 /* Driver's parameters */
36 #define RAVB_ALIGN	128
37 
38 enum ravb_reg {
39 	/* AVB-DMAC registers */
40 	CCC	= 0x0000,
41 	DBAT	= 0x0004,
42 	DLR	= 0x0008,
43 	CSR	= 0x000C,
44 	CDAR0	= 0x0010,
45 	CDAR1	= 0x0014,
46 	CDAR2	= 0x0018,
47 	CDAR3	= 0x001C,
48 	CDAR4	= 0x0020,
49 	CDAR5	= 0x0024,
50 	CDAR6	= 0x0028,
51 	CDAR7	= 0x002C,
52 	CDAR8	= 0x0030,
53 	CDAR9	= 0x0034,
54 	CDAR10	= 0x0038,
55 	CDAR11	= 0x003C,
56 	CDAR12	= 0x0040,
57 	CDAR13	= 0x0044,
58 	CDAR14	= 0x0048,
59 	CDAR15	= 0x004C,
60 	CDAR16	= 0x0050,
61 	CDAR17	= 0x0054,
62 	CDAR18	= 0x0058,
63 	CDAR19	= 0x005C,
64 	CDAR20	= 0x0060,
65 	CDAR21	= 0x0064,
66 	ESR	= 0x0088,
67 	APSR	= 0x008C,	/* R-Car Gen3 only */
68 	RCR	= 0x0090,
69 	RQC0	= 0x0094,
70 	RQC1	= 0x0098,
71 	RQC2	= 0x009C,
72 	RQC3	= 0x00A0,
73 	RQC4	= 0x00A4,
74 	RPC	= 0x00B0,
75 	RTC	= 0x00B4,	/* R-Car Gen3 and RZ/G2L only */
76 	UFCW	= 0x00BC,
77 	UFCS	= 0x00C0,
78 	UFCV0	= 0x00C4,
79 	UFCV1	= 0x00C8,
80 	UFCV2	= 0x00CC,
81 	UFCV3	= 0x00D0,
82 	UFCV4	= 0x00D4,
83 	UFCD0	= 0x00E0,
84 	UFCD1	= 0x00E4,
85 	UFCD2	= 0x00E8,
86 	UFCD3	= 0x00EC,
87 	UFCD4	= 0x00F0,
88 	SFO	= 0x00FC,
89 	SFP0	= 0x0100,
90 	SFP1	= 0x0104,
91 	SFP2	= 0x0108,
92 	SFP3	= 0x010C,
93 	SFP4	= 0x0110,
94 	SFP5	= 0x0114,
95 	SFP6	= 0x0118,
96 	SFP7	= 0x011C,
97 	SFP8	= 0x0120,
98 	SFP9	= 0x0124,
99 	SFP10	= 0x0128,
100 	SFP11	= 0x012C,
101 	SFP12	= 0x0130,
102 	SFP13	= 0x0134,
103 	SFP14	= 0x0138,
104 	SFP15	= 0x013C,
105 	SFP16	= 0x0140,
106 	SFP17	= 0x0144,
107 	SFP18	= 0x0148,
108 	SFP19	= 0x014C,
109 	SFP20	= 0x0150,
110 	SFP21	= 0x0154,
111 	SFP22	= 0x0158,
112 	SFP23	= 0x015C,
113 	SFP24	= 0x0160,
114 	SFP25	= 0x0164,
115 	SFP26	= 0x0168,
116 	SFP27	= 0x016C,
117 	SFP28	= 0x0170,
118 	SFP29	= 0x0174,
119 	SFP30	= 0x0178,
120 	SFP31	= 0x017C,
121 	SFM0	= 0x01C0,
122 	SFM1	= 0x01C4,
123 	TGC	= 0x0300,
124 	TCCR	= 0x0304,
125 	TSR	= 0x0308,
126 	TFA0	= 0x0310,
127 	TFA1	= 0x0314,
128 	TFA2	= 0x0318,
129 	CIVR0	= 0x0320,
130 	CIVR1	= 0x0324,
131 	CDVR0	= 0x0328,
132 	CDVR1	= 0x032C,
133 	CUL0	= 0x0330,
134 	CUL1	= 0x0334,
135 	CLL0	= 0x0338,
136 	CLL1	= 0x033C,
137 	DIC	= 0x0350,
138 	DIS	= 0x0354,
139 	EIC	= 0x0358,
140 	EIS	= 0x035C,
141 	RIC0	= 0x0360,
142 	RIS0	= 0x0364,
143 	RIC1	= 0x0368,
144 	RIS1	= 0x036C,
145 	RIC2	= 0x0370,
146 	RIS2	= 0x0374,
147 	TIC	= 0x0378,
148 	TIS	= 0x037C,
149 	ISS	= 0x0380,
150 	CIE	= 0x0384,	/* R-Car Gen3 only */
151 	GCCR	= 0x0390,
152 	GMTT	= 0x0394,
153 	GPTC	= 0x0398,
154 	GTI	= 0x039C,
155 	GTO0	= 0x03A0,
156 	GTO1	= 0x03A4,
157 	GTO2	= 0x03A8,
158 	GIC	= 0x03AC,
159 	GIS	= 0x03B0,
160 	GCPT	= 0x03B4,	/* Documented for R-Car Gen3 only */
161 	GCT0	= 0x03B8,
162 	GCT1	= 0x03BC,
163 	GCT2	= 0x03C0,
164 	GIE	= 0x03CC,	/* R-Car Gen3 only */
165 	GID	= 0x03D0,	/* R-Car Gen3 only */
166 	DIL	= 0x0440,	/* R-Car Gen3 only */
167 	RIE0	= 0x0460,	/* R-Car Gen3 only */
168 	RID0	= 0x0464,	/* R-Car Gen3 only */
169 	RIE2	= 0x0470,	/* R-Car Gen3 only */
170 	RID2	= 0x0474,	/* R-Car Gen3 only */
171 	TIE	= 0x0478,	/* R-Car Gen3 only */
172 	TID	= 0x047c,	/* R-Car Gen3 only */
173 
174 	/* E-MAC registers */
175 	ECMR	= 0x0500,
176 	RFLR	= 0x0508,
177 	ECSR	= 0x0510,
178 	ECSIPR	= 0x0518,
179 	PIR	= 0x0520,
180 	PSR	= 0x0528,
181 	PIPR	= 0x052c,
182 	CXR31	= 0x0530,	/* RZ/G2L only */
183 	CXR35	= 0x0540,	/* RZ/G2L only */
184 	MPR	= 0x0558,
185 	PFTCR	= 0x055c,
186 	PFRCR	= 0x0560,
187 	GECMR	= 0x05b0,
188 	MAHR	= 0x05c0,
189 	MALR	= 0x05c8,
190 	TROCR	= 0x0700,	/* R-Car Gen3 and RZ/G2L only */
191 	CXR41	= 0x0708,	/* RZ/G2L only */
192 	CXR42	= 0x0710,	/* RZ/G2L only */
193 	CEFCR	= 0x0740,
194 	FRECR	= 0x0748,
195 	TSFRCR	= 0x0750,
196 	TLFRCR	= 0x0758,
197 	RFCR	= 0x0760,
198 	MAFCR	= 0x0778,
199 
200 	/* TOE registers (RZ/G2L only) */
201 	CSR0    = 0x0800,
202 	CSR1    = 0x0804,
203 	CSR2    = 0x0808,
204 };
205 
206 
207 /* Register bits of the Ethernet AVB */
208 /* CCC */
209 enum CCC_BIT {
210 	CCC_OPC		= 0x00000003,
211 	CCC_OPC_RESET	= 0x00000000,
212 	CCC_OPC_CONFIG	= 0x00000001,
213 	CCC_OPC_OPERATION = 0x00000002,
214 	CCC_GAC		= 0x00000080,
215 	CCC_DTSR	= 0x00000100,
216 	CCC_CSEL	= 0x00030000,
217 	CCC_CSEL_HPB	= 0x00010000,
218 	CCC_CSEL_ETH_TX	= 0x00020000,
219 	CCC_CSEL_GMII_REF = 0x00030000,
220 	CCC_LBME	= 0x01000000,
221 };
222 
223 /* CSR */
224 enum CSR_BIT {
225 	CSR_OPS		= 0x0000000F,
226 	CSR_OPS_RESET	= 0x00000001,
227 	CSR_OPS_CONFIG	= 0x00000002,
228 	CSR_OPS_OPERATION = 0x00000004,
229 	CSR_OPS_STANDBY	= 0x00000008,	/* Documented for R-Car Gen3 only */
230 	CSR_DTS		= 0x00000100,
231 	CSR_TPO0	= 0x00010000,
232 	CSR_TPO1	= 0x00020000,
233 	CSR_TPO2	= 0x00040000,
234 	CSR_TPO3	= 0x00080000,
235 	CSR_RPO		= 0x00100000,
236 };
237 
238 /* ESR */
239 enum ESR_BIT {
240 	ESR_EQN		= 0x0000001F,
241 	ESR_ET		= 0x00000F00,
242 	ESR_EIL		= 0x00001000,
243 };
244 
245 /* APSR (R-Car Gen3 only) */
246 enum APSR_BIT {
247 	APSR_MEMS	= 0x00000002,	/* Undocumented */
248 	APSR_CMSW	= 0x00000010,
249 	APSR_RDM	= 0x00002000,
250 	APSR_TDM	= 0x00004000,
251 	APSR_MIISELECT	= 0x01000000,	/* R-Car V4M only */
252 };
253 
254 /* RCR */
255 enum RCR_BIT {
256 	RCR_EFFS	= 0x00000001,
257 	RCR_ENCF	= 0x00000002,
258 	RCR_ESF		= 0x0000000C,
259 	RCR_ETS0	= 0x00000010,
260 	RCR_ETS2	= 0x00000020,
261 	RCR_RFCL	= 0x1FFF0000,
262 };
263 
264 /* RQC0/1/2/3/4 */
265 enum RQC_BIT {
266 	RQC_RSM0	= 0x00000003,
267 	RQC_UFCC0	= 0x00000030,
268 	RQC_RSM1	= 0x00000300,
269 	RQC_UFCC1	= 0x00003000,
270 	RQC_RSM2	= 0x00030000,
271 	RQC_UFCC2	= 0x00300000,
272 	RQC_RSM3	= 0x03000000,
273 	RQC_UFCC3	= 0x30000000,
274 };
275 
276 /* RPC */
277 enum RPC_BIT {
278 	RPC_PCNT	= 0x00000700,
279 	RPC_DCNT	= 0x00FF0000,
280 };
281 
282 /* UFCW */
283 enum UFCW_BIT {
284 	UFCW_WL0	= 0x0000003F,
285 	UFCW_WL1	= 0x00003F00,
286 	UFCW_WL2	= 0x003F0000,
287 	UFCW_WL3	= 0x3F000000,
288 };
289 
290 /* UFCS */
291 enum UFCS_BIT {
292 	UFCS_SL0	= 0x0000003F,
293 	UFCS_SL1	= 0x00003F00,
294 	UFCS_SL2	= 0x003F0000,
295 	UFCS_SL3	= 0x3F000000,
296 };
297 
298 /* UFCV0/1/2/3/4 */
299 enum UFCV_BIT {
300 	UFCV_CV0	= 0x0000003F,
301 	UFCV_CV1	= 0x00003F00,
302 	UFCV_CV2	= 0x003F0000,
303 	UFCV_CV3	= 0x3F000000,
304 };
305 
306 /* UFCD0/1/2/3/4 */
307 enum UFCD_BIT {
308 	UFCD_DV0	= 0x0000003F,
309 	UFCD_DV1	= 0x00003F00,
310 	UFCD_DV2	= 0x003F0000,
311 	UFCD_DV3	= 0x3F000000,
312 };
313 
314 /* SFO */
315 enum SFO_BIT {
316 	SFO_FBP		= 0x0000003F,
317 };
318 
319 /* RTC */
320 enum RTC_BIT {
321 	RTC_MFL0	= 0x00000FFF,
322 	RTC_MFL1	= 0x0FFF0000,
323 };
324 
325 /* TGC */
326 enum TGC_BIT {
327 	TGC_TSM0	= 0x00000001,
328 	TGC_TSM1	= 0x00000002,
329 	TGC_TSM2	= 0x00000004,
330 	TGC_TSM3	= 0x00000008,
331 	TGC_TQP		= 0x00000030,
332 	TGC_TQP_NONAVB	= 0x00000000,
333 	TGC_TQP_AVBMODE1 = 0x00000010,
334 	TGC_TQP_AVBMODE2 = 0x00000030,
335 	TGC_TBD0	= 0x00000300,
336 	TGC_TBD1	= 0x00003000,
337 	TGC_TBD2	= 0x00030000,
338 	TGC_TBD3	= 0x00300000,
339 };
340 
341 /* TCCR */
342 enum TCCR_BIT {
343 	TCCR_TSRQ0	= 0x00000001,
344 	TCCR_TSRQ1	= 0x00000002,
345 	TCCR_TSRQ2	= 0x00000004,
346 	TCCR_TSRQ3	= 0x00000008,
347 	TCCR_TFEN	= 0x00000100,
348 	TCCR_TFR	= 0x00000200,
349 };
350 
351 /* TSR */
352 enum TSR_BIT {
353 	TSR_CCS0	= 0x00000003,
354 	TSR_CCS1	= 0x0000000C,
355 	TSR_TFFL	= 0x00000700,
356 };
357 
358 /* TFA2 */
359 enum TFA2_BIT {
360 	TFA2_TSV	= 0x0000FFFF,
361 	TFA2_TST	= 0x03FF0000,
362 };
363 
364 /* DIC */
365 enum DIC_BIT {
366 	DIC_DPE1	= 0x00000002,
367 	DIC_DPE2	= 0x00000004,
368 	DIC_DPE3	= 0x00000008,
369 	DIC_DPE4	= 0x00000010,
370 	DIC_DPE5	= 0x00000020,
371 	DIC_DPE6	= 0x00000040,
372 	DIC_DPE7	= 0x00000080,
373 	DIC_DPE8	= 0x00000100,
374 	DIC_DPE9	= 0x00000200,
375 	DIC_DPE10	= 0x00000400,
376 	DIC_DPE11	= 0x00000800,
377 	DIC_DPE12	= 0x00001000,
378 	DIC_DPE13	= 0x00002000,
379 	DIC_DPE14	= 0x00004000,
380 	DIC_DPE15	= 0x00008000,
381 };
382 
383 /* DIS */
384 enum DIS_BIT {
385 	DIS_DPF1	= 0x00000002,
386 	DIS_DPF2	= 0x00000004,
387 	DIS_DPF3	= 0x00000008,
388 	DIS_DPF4	= 0x00000010,
389 	DIS_DPF5	= 0x00000020,
390 	DIS_DPF6	= 0x00000040,
391 	DIS_DPF7	= 0x00000080,
392 	DIS_DPF8	= 0x00000100,
393 	DIS_DPF9	= 0x00000200,
394 	DIS_DPF10	= 0x00000400,
395 	DIS_DPF11	= 0x00000800,
396 	DIS_DPF12	= 0x00001000,
397 	DIS_DPF13	= 0x00002000,
398 	DIS_DPF14	= 0x00004000,
399 	DIS_DPF15	= 0x00008000,
400 };
401 
402 /* EIC */
403 enum EIC_BIT {
404 	EIC_MREE	= 0x00000001,
405 	EIC_MTEE	= 0x00000002,
406 	EIC_QEE		= 0x00000004,
407 	EIC_SEE		= 0x00000008,
408 	EIC_CLLE0	= 0x00000010,
409 	EIC_CLLE1	= 0x00000020,
410 	EIC_CULE0	= 0x00000040,
411 	EIC_CULE1	= 0x00000080,
412 	EIC_TFFE	= 0x00000100,
413 };
414 
415 /* EIS */
416 enum EIS_BIT {
417 	EIS_MREF	= 0x00000001,
418 	EIS_MTEF	= 0x00000002,
419 	EIS_QEF		= 0x00000004,
420 	EIS_SEF		= 0x00000008,
421 	EIS_CLLF0	= 0x00000010,
422 	EIS_CLLF1	= 0x00000020,
423 	EIS_CULF0	= 0x00000040,
424 	EIS_CULF1	= 0x00000080,
425 	EIS_TFFF	= 0x00000100,
426 	EIS_QFS		= 0x00010000,
427 	EIS_RESERVED	= (GENMASK(31, 17) | GENMASK(15, 11)),
428 };
429 
430 /* RIC0 */
431 enum RIC0_BIT {
432 	RIC0_FRE0	= 0x00000001,
433 	RIC0_FRE1	= 0x00000002,
434 	RIC0_FRE2	= 0x00000004,
435 	RIC0_FRE3	= 0x00000008,
436 	RIC0_FRE4	= 0x00000010,
437 	RIC0_FRE5	= 0x00000020,
438 	RIC0_FRE6	= 0x00000040,
439 	RIC0_FRE7	= 0x00000080,
440 	RIC0_FRE8	= 0x00000100,
441 	RIC0_FRE9	= 0x00000200,
442 	RIC0_FRE10	= 0x00000400,
443 	RIC0_FRE11	= 0x00000800,
444 	RIC0_FRE12	= 0x00001000,
445 	RIC0_FRE13	= 0x00002000,
446 	RIC0_FRE14	= 0x00004000,
447 	RIC0_FRE15	= 0x00008000,
448 	RIC0_FRE16	= 0x00010000,
449 	RIC0_FRE17	= 0x00020000,
450 };
451 
452 /* RIC0 */
453 enum RIS0_BIT {
454 	RIS0_FRF0	= 0x00000001,
455 	RIS0_FRF1	= 0x00000002,
456 	RIS0_FRF2	= 0x00000004,
457 	RIS0_FRF3	= 0x00000008,
458 	RIS0_FRF4	= 0x00000010,
459 	RIS0_FRF5	= 0x00000020,
460 	RIS0_FRF6	= 0x00000040,
461 	RIS0_FRF7	= 0x00000080,
462 	RIS0_FRF8	= 0x00000100,
463 	RIS0_FRF9	= 0x00000200,
464 	RIS0_FRF10	= 0x00000400,
465 	RIS0_FRF11	= 0x00000800,
466 	RIS0_FRF12	= 0x00001000,
467 	RIS0_FRF13	= 0x00002000,
468 	RIS0_FRF14	= 0x00004000,
469 	RIS0_FRF15	= 0x00008000,
470 	RIS0_FRF16	= 0x00010000,
471 	RIS0_FRF17	= 0x00020000,
472 	RIS0_RESERVED	= GENMASK(31, 18),
473 };
474 
475 /* RIC1 */
476 enum RIC1_BIT {
477 	RIC1_RFWE	= 0x80000000,
478 };
479 
480 /* RIS1 */
481 enum RIS1_BIT {
482 	RIS1_RFWF	= 0x80000000,
483 };
484 
485 /* RIC2 */
486 enum RIC2_BIT {
487 	RIC2_QFE0	= 0x00000001,
488 	RIC2_QFE1	= 0x00000002,
489 	RIC2_QFE2	= 0x00000004,
490 	RIC2_QFE3	= 0x00000008,
491 	RIC2_QFE4	= 0x00000010,
492 	RIC2_QFE5	= 0x00000020,
493 	RIC2_QFE6	= 0x00000040,
494 	RIC2_QFE7	= 0x00000080,
495 	RIC2_QFE8	= 0x00000100,
496 	RIC2_QFE9	= 0x00000200,
497 	RIC2_QFE10	= 0x00000400,
498 	RIC2_QFE11	= 0x00000800,
499 	RIC2_QFE12	= 0x00001000,
500 	RIC2_QFE13	= 0x00002000,
501 	RIC2_QFE14	= 0x00004000,
502 	RIC2_QFE15	= 0x00008000,
503 	RIC2_QFE16	= 0x00010000,
504 	RIC2_QFE17	= 0x00020000,
505 	RIC2_RFFE	= 0x80000000,
506 };
507 
508 /* RIS2 */
509 enum RIS2_BIT {
510 	RIS2_QFF0	= 0x00000001,
511 	RIS2_QFF1	= 0x00000002,
512 	RIS2_QFF2	= 0x00000004,
513 	RIS2_QFF3	= 0x00000008,
514 	RIS2_QFF4	= 0x00000010,
515 	RIS2_QFF5	= 0x00000020,
516 	RIS2_QFF6	= 0x00000040,
517 	RIS2_QFF7	= 0x00000080,
518 	RIS2_QFF8	= 0x00000100,
519 	RIS2_QFF9	= 0x00000200,
520 	RIS2_QFF10	= 0x00000400,
521 	RIS2_QFF11	= 0x00000800,
522 	RIS2_QFF12	= 0x00001000,
523 	RIS2_QFF13	= 0x00002000,
524 	RIS2_QFF14	= 0x00004000,
525 	RIS2_QFF15	= 0x00008000,
526 	RIS2_QFF16	= 0x00010000,
527 	RIS2_QFF17	= 0x00020000,
528 	RIS2_RFFF	= 0x80000000,
529 	RIS2_RESERVED	= GENMASK(30, 18),
530 };
531 
532 /* TIC */
533 enum TIC_BIT {
534 	TIC_FTE0	= 0x00000001,	/* Documented for R-Car Gen3 only */
535 	TIC_FTE1	= 0x00000002,	/* Documented for R-Car Gen3 only */
536 	TIC_TFUE	= 0x00000100,
537 	TIC_TFWE	= 0x00000200,
538 };
539 
540 /* TIS */
541 enum TIS_BIT {
542 	TIS_FTF0	= 0x00000001,	/* Documented for R-Car Gen3 only */
543 	TIS_FTF1	= 0x00000002,	/* Documented for R-Car Gen3 only */
544 	TIS_TFUF	= 0x00000100,
545 	TIS_TFWF	= 0x00000200,
546 	TIS_RESERVED	= (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
547 };
548 
549 /* ISS */
550 enum ISS_BIT {
551 	ISS_FRS		= 0x00000001,	/* Documented for R-Car Gen3 only */
552 	ISS_FTS		= 0x00000004,	/* Documented for R-Car Gen3 only */
553 	ISS_ES		= 0x00000040,
554 	ISS_MS		= 0x00000080,
555 	ISS_TFUS	= 0x00000100,
556 	ISS_TFWS	= 0x00000200,
557 	ISS_RFWS	= 0x00001000,
558 	ISS_CGIS	= 0x00002000,
559 	ISS_DPS1	= 0x00020000,
560 	ISS_DPS2	= 0x00040000,
561 	ISS_DPS3	= 0x00080000,
562 	ISS_DPS4	= 0x00100000,
563 	ISS_DPS5	= 0x00200000,
564 	ISS_DPS6	= 0x00400000,
565 	ISS_DPS7	= 0x00800000,
566 	ISS_DPS8	= 0x01000000,
567 	ISS_DPS9	= 0x02000000,
568 	ISS_DPS10	= 0x04000000,
569 	ISS_DPS11	= 0x08000000,
570 	ISS_DPS12	= 0x10000000,
571 	ISS_DPS13	= 0x20000000,
572 	ISS_DPS14	= 0x40000000,
573 	ISS_DPS15	= 0x80000000,
574 };
575 
576 /* CIE (R-Car Gen3 only) */
577 enum CIE_BIT {
578 	CIE_CRIE	= 0x00000001,
579 	CIE_CTIE	= 0x00000100,
580 	CIE_RQFM	= 0x00010000,
581 	CIE_CL0M	= 0x00020000,
582 	CIE_RFWL	= 0x00040000,
583 	CIE_RFFL	= 0x00080000,
584 };
585 
586 /* GCCR */
587 enum GCCR_BIT {
588 	GCCR_TCR	= 0x00000003,
589 	GCCR_TCR_NOREQ	= 0x00000000, /* No request */
590 	GCCR_TCR_RESET	= 0x00000001, /* gPTP/AVTP presentation timer reset */
591 	GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */
592 	GCCR_LTO	= 0x00000004,
593 	GCCR_LTI	= 0x00000008,
594 	GCCR_LPTC	= 0x00000010,
595 	GCCR_LMTT	= 0x00000020,
596 	GCCR_TCSS	= 0x00000300,
597 	GCCR_TCSS_GPTP	= 0x00000000,	/* gPTP timer value */
598 	GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */
599 	GCCR_TCSS_AVTP	= 0x00000200,	/* AVTP presentation time value */
600 };
601 
602 /* GTI */
603 enum GTI_BIT {
604 	GTI_TIV		= 0x0FFFFFFF,
605 };
606 
607 #define GTI_TIV_MAX	GTI_TIV
608 #define GTI_TIV_MIN	0x20
609 
610 /* GIC */
611 enum GIC_BIT {
612 	GIC_PTCE	= 0x00000001,	/* Documented for R-Car Gen3 only */
613 	GIC_PTME	= 0x00000004,
614 };
615 
616 /* GIS */
617 enum GIS_BIT {
618 	GIS_PTCF	= 0x00000001,	/* Documented for R-Car Gen3 only */
619 	GIS_PTMF	= 0x00000004,
620 	GIS_RESERVED	= GENMASK(15, 10),
621 };
622 
623 /* GIE (R-Car Gen3 only) */
624 enum GIE_BIT {
625 	GIE_PTCS	= 0x00000001,
626 	GIE_PTOS	= 0x00000002,
627 	GIE_PTMS0	= 0x00000004,
628 	GIE_PTMS1	= 0x00000008,
629 	GIE_PTMS2	= 0x00000010,
630 	GIE_PTMS3	= 0x00000020,
631 	GIE_PTMS4	= 0x00000040,
632 	GIE_PTMS5	= 0x00000080,
633 	GIE_PTMS6	= 0x00000100,
634 	GIE_PTMS7	= 0x00000200,
635 	GIE_ATCS0	= 0x00010000,
636 	GIE_ATCS1	= 0x00020000,
637 	GIE_ATCS2	= 0x00040000,
638 	GIE_ATCS3	= 0x00080000,
639 	GIE_ATCS4	= 0x00100000,
640 	GIE_ATCS5	= 0x00200000,
641 	GIE_ATCS6	= 0x00400000,
642 	GIE_ATCS7	= 0x00800000,
643 	GIE_ATCS8	= 0x01000000,
644 	GIE_ATCS9	= 0x02000000,
645 	GIE_ATCS10	= 0x04000000,
646 	GIE_ATCS11	= 0x08000000,
647 	GIE_ATCS12	= 0x10000000,
648 	GIE_ATCS13	= 0x20000000,
649 	GIE_ATCS14	= 0x40000000,
650 	GIE_ATCS15	= 0x80000000,
651 };
652 
653 /* GID (R-Car Gen3 only) */
654 enum GID_BIT {
655 	GID_PTCD	= 0x00000001,
656 	GID_PTOD	= 0x00000002,
657 	GID_PTMD0	= 0x00000004,
658 	GID_PTMD1	= 0x00000008,
659 	GID_PTMD2	= 0x00000010,
660 	GID_PTMD3	= 0x00000020,
661 	GID_PTMD4	= 0x00000040,
662 	GID_PTMD5	= 0x00000080,
663 	GID_PTMD6	= 0x00000100,
664 	GID_PTMD7	= 0x00000200,
665 	GID_ATCD0	= 0x00010000,
666 	GID_ATCD1	= 0x00020000,
667 	GID_ATCD2	= 0x00040000,
668 	GID_ATCD3	= 0x00080000,
669 	GID_ATCD4	= 0x00100000,
670 	GID_ATCD5	= 0x00200000,
671 	GID_ATCD6	= 0x00400000,
672 	GID_ATCD7	= 0x00800000,
673 	GID_ATCD8	= 0x01000000,
674 	GID_ATCD9	= 0x02000000,
675 	GID_ATCD10	= 0x04000000,
676 	GID_ATCD11	= 0x08000000,
677 	GID_ATCD12	= 0x10000000,
678 	GID_ATCD13	= 0x20000000,
679 	GID_ATCD14	= 0x40000000,
680 	GID_ATCD15	= 0x80000000,
681 };
682 
683 /* RIE0 (R-Car Gen3 only) */
684 enum RIE0_BIT {
685 	RIE0_FRS0	= 0x00000001,
686 	RIE0_FRS1	= 0x00000002,
687 	RIE0_FRS2	= 0x00000004,
688 	RIE0_FRS3	= 0x00000008,
689 	RIE0_FRS4	= 0x00000010,
690 	RIE0_FRS5	= 0x00000020,
691 	RIE0_FRS6	= 0x00000040,
692 	RIE0_FRS7	= 0x00000080,
693 	RIE0_FRS8	= 0x00000100,
694 	RIE0_FRS9	= 0x00000200,
695 	RIE0_FRS10	= 0x00000400,
696 	RIE0_FRS11	= 0x00000800,
697 	RIE0_FRS12	= 0x00001000,
698 	RIE0_FRS13	= 0x00002000,
699 	RIE0_FRS14	= 0x00004000,
700 	RIE0_FRS15	= 0x00008000,
701 	RIE0_FRS16	= 0x00010000,
702 	RIE0_FRS17	= 0x00020000,
703 };
704 
705 /* RID0 (R-Car Gen3 only) */
706 enum RID0_BIT {
707 	RID0_FRD0	= 0x00000001,
708 	RID0_FRD1	= 0x00000002,
709 	RID0_FRD2	= 0x00000004,
710 	RID0_FRD3	= 0x00000008,
711 	RID0_FRD4	= 0x00000010,
712 	RID0_FRD5	= 0x00000020,
713 	RID0_FRD6	= 0x00000040,
714 	RID0_FRD7	= 0x00000080,
715 	RID0_FRD8	= 0x00000100,
716 	RID0_FRD9	= 0x00000200,
717 	RID0_FRD10	= 0x00000400,
718 	RID0_FRD11	= 0x00000800,
719 	RID0_FRD12	= 0x00001000,
720 	RID0_FRD13	= 0x00002000,
721 	RID0_FRD14	= 0x00004000,
722 	RID0_FRD15	= 0x00008000,
723 	RID0_FRD16	= 0x00010000,
724 	RID0_FRD17	= 0x00020000,
725 };
726 
727 /* RIE2 (R-Car Gen3 only) */
728 enum RIE2_BIT {
729 	RIE2_QFS0	= 0x00000001,
730 	RIE2_QFS1	= 0x00000002,
731 	RIE2_QFS2	= 0x00000004,
732 	RIE2_QFS3	= 0x00000008,
733 	RIE2_QFS4	= 0x00000010,
734 	RIE2_QFS5	= 0x00000020,
735 	RIE2_QFS6	= 0x00000040,
736 	RIE2_QFS7	= 0x00000080,
737 	RIE2_QFS8	= 0x00000100,
738 	RIE2_QFS9	= 0x00000200,
739 	RIE2_QFS10	= 0x00000400,
740 	RIE2_QFS11	= 0x00000800,
741 	RIE2_QFS12	= 0x00001000,
742 	RIE2_QFS13	= 0x00002000,
743 	RIE2_QFS14	= 0x00004000,
744 	RIE2_QFS15	= 0x00008000,
745 	RIE2_QFS16	= 0x00010000,
746 	RIE2_QFS17	= 0x00020000,
747 	RIE2_RFFS	= 0x80000000,
748 };
749 
750 /* RID2 (R-Car Gen3 only) */
751 enum RID2_BIT {
752 	RID2_QFD0	= 0x00000001,
753 	RID2_QFD1	= 0x00000002,
754 	RID2_QFD2	= 0x00000004,
755 	RID2_QFD3	= 0x00000008,
756 	RID2_QFD4	= 0x00000010,
757 	RID2_QFD5	= 0x00000020,
758 	RID2_QFD6	= 0x00000040,
759 	RID2_QFD7	= 0x00000080,
760 	RID2_QFD8	= 0x00000100,
761 	RID2_QFD9	= 0x00000200,
762 	RID2_QFD10	= 0x00000400,
763 	RID2_QFD11	= 0x00000800,
764 	RID2_QFD12	= 0x00001000,
765 	RID2_QFD13	= 0x00002000,
766 	RID2_QFD14	= 0x00004000,
767 	RID2_QFD15	= 0x00008000,
768 	RID2_QFD16	= 0x00010000,
769 	RID2_QFD17	= 0x00020000,
770 	RID2_RFFD	= 0x80000000,
771 };
772 
773 /* TIE (R-Car Gen3 only) */
774 enum TIE_BIT {
775 	TIE_FTS0	= 0x00000001,
776 	TIE_FTS1	= 0x00000002,
777 	TIE_FTS2	= 0x00000004,
778 	TIE_FTS3	= 0x00000008,
779 	TIE_TFUS	= 0x00000100,
780 	TIE_TFWS	= 0x00000200,
781 	TIE_MFUS	= 0x00000400,
782 	TIE_MFWS	= 0x00000800,
783 	TIE_TDPS0	= 0x00010000,
784 	TIE_TDPS1	= 0x00020000,
785 	TIE_TDPS2	= 0x00040000,
786 	TIE_TDPS3	= 0x00080000,
787 };
788 
789 /* TID (R-Car Gen3 only) */
790 enum TID_BIT {
791 	TID_FTD0	= 0x00000001,
792 	TID_FTD1	= 0x00000002,
793 	TID_FTD2	= 0x00000004,
794 	TID_FTD3	= 0x00000008,
795 	TID_TFUD	= 0x00000100,
796 	TID_TFWD	= 0x00000200,
797 	TID_MFUD	= 0x00000400,
798 	TID_MFWD	= 0x00000800,
799 	TID_TDPD0	= 0x00010000,
800 	TID_TDPD1	= 0x00020000,
801 	TID_TDPD2	= 0x00040000,
802 	TID_TDPD3	= 0x00080000,
803 };
804 
805 /* ECMR */
806 enum ECMR_BIT {
807 	ECMR_PRM	= 0x00000001,
808 	ECMR_DM		= 0x00000002,
809 	ECMR_TE		= 0x00000020,
810 	ECMR_RE		= 0x00000040,
811 	ECMR_MPDE	= 0x00000200,
812 	ECMR_TXF	= 0x00010000,	/* Documented for R-Car Gen3 only */
813 	ECMR_RXF	= 0x00020000,
814 	ECMR_PFR	= 0x00040000,
815 	ECMR_ZPF	= 0x00080000,	/* Documented for R-Car Gen3 and RZ/G2L */
816 	ECMR_RZPF	= 0x00100000,
817 	ECMR_DPAD	= 0x00200000,
818 	ECMR_RCSC	= 0x00800000,
819 	ECMR_RCPT	= 0x02000000,	/* Documented for RZ/G2L only */
820 	ECMR_TRCCM	= 0x04000000,
821 };
822 
823 /* ECSR */
824 enum ECSR_BIT {
825 	ECSR_ICD	= 0x00000001,
826 	ECSR_MPD	= 0x00000002,
827 	ECSR_LCHNG	= 0x00000004,
828 	ECSR_PHYI	= 0x00000008,
829 	ECSR_PFRI	= 0x00000010,	/* Documented for R-Car Gen3 and RZ/G2L */
830 };
831 
832 /* ECSIPR */
833 enum ECSIPR_BIT {
834 	ECSIPR_ICDIP	= 0x00000001,
835 	ECSIPR_MPDIP	= 0x00000002,
836 	ECSIPR_LCHNGIP	= 0x00000004,
837 };
838 
839 /* PIR */
840 enum PIR_BIT {
841 	PIR_MDC		= 0x00000001,
842 	PIR_MMD		= 0x00000002,
843 	PIR_MDO		= 0x00000004,
844 	PIR_MDI		= 0x00000008,
845 };
846 
847 /* PSR */
848 enum PSR_BIT {
849 	PSR_LMON	= 0x00000001,
850 };
851 
852 /* PIPR */
853 enum PIPR_BIT {
854 	PIPR_PHYIP	= 0x00000001,
855 };
856 
857 /* MPR */
858 enum MPR_BIT {
859 	MPR_MP		= 0x0000ffff,
860 };
861 
862 /* GECMR */
863 enum GECMR_BIT {
864 	GECMR_SPEED		= 0x00000001,
865 	GECMR_SPEED_100		= 0x00000000,
866 	GECMR_SPEED_1000	= 0x00000001,
867 	GBETH_GECMR_SPEED	= 0x00000030,
868 	GBETH_GECMR_SPEED_10	= 0x00000000,
869 	GBETH_GECMR_SPEED_100	= 0x00000010,
870 	GBETH_GECMR_SPEED_1000	= 0x00000020,
871 };
872 
873 /* The Ethernet AVB descriptor definitions. */
874 struct ravb_desc {
875 	__le16 ds;	/* Descriptor size */
876 	u8 cc;		/* Content control MSBs (reserved) */
877 	u8 die_dt;	/* Descriptor interrupt enable and type */
878 	__le32 dptr;	/* Descriptor pointer */
879 };
880 
881 #define DPTR_ALIGN	4	/* Required descriptor pointer alignment */
882 
883 enum DIE_DT {
884 	/* Frame data */
885 	DT_FMID		= 0x40,
886 	DT_FSTART	= 0x50,
887 	DT_FEND		= 0x60,
888 	DT_FSINGLE	= 0x70,
889 	/* Chain control */
890 	DT_LINK		= 0x80,
891 	DT_LINKFIX	= 0x90,
892 	DT_EOS		= 0xa0,
893 	/* HW/SW arbitration */
894 	DT_FEMPTY	= 0xc0,
895 	DT_FEMPTY_IS	= 0xd0,
896 	DT_FEMPTY_IC	= 0xe0,
897 	DT_FEMPTY_ND	= 0xf0,
898 	DT_LEMPTY	= 0x20,
899 	DT_EEMPTY	= 0x30,
900 };
901 
902 struct ravb_rx_desc {
903 	__le16 ds_cc;	/* Descriptor size and content control LSBs */
904 	u8 msc;		/* MAC status code */
905 	u8 die_dt;	/* Descriptor interrupt enable and type */
906 	__le32 dptr;	/* Descpriptor pointer */
907 };
908 
909 struct ravb_ex_rx_desc {
910 	__le16 ds_cc;	/* Descriptor size and content control lower bits */
911 	u8 msc;		/* MAC status code */
912 	u8 die_dt;	/* Descriptor interrupt enable and type */
913 	__le32 dptr;	/* Descpriptor pointer */
914 	__le32 ts_n;	/* Timestampe nsec */
915 	__le32 ts_sl;	/* Timestamp low */
916 	__le16 ts_sh;	/* Timestamp high */
917 	__le16 res;	/* Reserved bits */
918 };
919 
920 enum RX_DS_CC_BIT {
921 	RX_DS		= 0x0fff, /* Data size */
922 	RX_TR		= 0x1000, /* Truncation indication */
923 	RX_EI		= 0x2000, /* Error indication */
924 	RX_PS		= 0xc000, /* Padding selection */
925 };
926 
927 /* E-MAC status code */
928 enum MSC_BIT {
929 	MSC_CRC		= 0x01, /* Frame CRC error */
930 	MSC_RFE		= 0x02, /* Frame reception error (flagged by PHY) */
931 	MSC_RTSF	= 0x04, /* Frame length error (frame too short) */
932 	MSC_RTLF	= 0x08, /* Frame length error (frame too long) */
933 	MSC_FRE		= 0x10, /* Fraction error (not a multiple of 8 bits) */
934 	MSC_CRL		= 0x20, /* Carrier lost */
935 	MSC_CEEF	= 0x40, /* Carrier extension error */
936 	MSC_MC		= 0x80, /* Multicast frame reception */
937 };
938 
939 struct ravb_tx_desc {
940 	__le16 ds_tagl;	/* Descriptor size and frame tag LSBs */
941 	u8 tagh_tsr;	/* Frame tag MSBs and timestamp storage request bit */
942 	u8 die_dt;	/* Descriptor interrupt enable and type */
943 	__le32 dptr;	/* Descpriptor pointer */
944 };
945 
946 enum TX_DS_TAGL_BIT {
947 	TX_DS		= 0x0fff, /* Data size */
948 	TX_TAGL		= 0xf000, /* Frame tag LSBs */
949 };
950 
951 enum TX_TAGH_TSR_BIT {
952 	TX_TAGH		= 0x3f, /* Frame tag MSBs */
953 	TX_TSR		= 0x40, /* Timestamp storage request */
954 };
955 enum RAVB_QUEUE {
956 	RAVB_BE = 0,	/* Best Effort Queue */
957 	RAVB_NC,	/* Network Control Queue */
958 };
959 
960 enum CXR31_BIT {
961 	CXR31_SEL_LINK0	= 0x00000001,
962 	CXR31_SEL_LINK1	= 0x00000008,
963 };
964 
965 enum CXR35_BIT {
966 	CXR35_SEL_XMII		= 0x00000003,
967 	CXR35_SEL_XMII_RGMII	= 0x00000000,
968 	CXR35_SEL_XMII_MII	= 0x00000002,
969 	CXR35_HALFCYC_CLKSW	= 0xffff0000,
970 };
971 
972 enum CSR0_BIT {
973 	CSR0_TPE	= 0x00000010,
974 	CSR0_RPE	= 0x00000020,
975 };
976 
977 enum CSR1_BIT {
978 	CSR1_TIP4	= 0x00000001,
979 	CSR1_TTCP4	= 0x00000010,
980 	CSR1_TUDP4	= 0x00000020,
981 	CSR1_TICMP4	= 0x00000040,
982 	CSR1_TTCP6	= 0x00100000,
983 	CSR1_TUDP6	= 0x00200000,
984 	CSR1_TICMP6	= 0x00400000,
985 	CSR1_THOP	= 0x01000000,
986 	CSR1_TROUT	= 0x02000000,
987 	CSR1_TAHD	= 0x04000000,
988 	CSR1_TDHD	= 0x08000000,
989 };
990 
991 #define CSR1_CSUM_ENABLE (CSR1_TTCP4 | CSR1_TUDP4 | CSR1_TTCP6 | CSR1_TUDP6)
992 
993 enum CSR2_BIT {
994 	CSR2_RIP4	= 0x00000001,
995 	CSR2_RTCP4	= 0x00000010,
996 	CSR2_RUDP4	= 0x00000020,
997 	CSR2_RICMP4	= 0x00000040,
998 	CSR2_RTCP6	= 0x00100000,
999 	CSR2_RUDP6	= 0x00200000,
1000 	CSR2_RICMP6	= 0x00400000,
1001 	CSR2_RHOP	= 0x01000000,
1002 	CSR2_RROUT	= 0x02000000,
1003 	CSR2_RAHD	= 0x04000000,
1004 	CSR2_RDHD	= 0x08000000,
1005 };
1006 
1007 #define CSR2_CSUM_ENABLE (CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4 | \
1008 			  CSR2_RTCP6 | CSR2_RUDP6 | CSR2_RICMP6)
1009 
1010 #define RX_QUEUE_OFFSET	4
1011 #define NUM_RX_QUEUE	2
1012 #define NUM_TX_QUEUE	2
1013 
1014 struct ravb_tstamp_skb {
1015 	struct list_head list;
1016 	struct sk_buff *skb;
1017 	u16 tag;
1018 };
1019 
1020 struct ravb_ptp_perout {
1021 	u32 target;
1022 	u32 period;
1023 };
1024 
1025 #define N_EXT_TS	1
1026 #define N_PER_OUT	1
1027 
1028 struct ravb_ptp {
1029 	struct ptp_clock *clock;
1030 	struct ptp_clock_info info;
1031 	u32 default_addend;
1032 	u32 current_addend;
1033 	int extts[N_EXT_TS];
1034 	struct ravb_ptp_perout perout[N_PER_OUT];
1035 };
1036 
1037 struct ravb_hw_info {
1038 	int (*receive)(struct net_device *ndev, int budget, int q);
1039 	void (*set_rate)(struct net_device *ndev);
1040 	int (*set_feature)(struct net_device *ndev, netdev_features_t features);
1041 	int (*dmac_init)(struct net_device *ndev);
1042 	void (*emac_init)(struct net_device *ndev);
1043 	const char (*gstrings_stats)[ETH_GSTRING_LEN];
1044 	size_t gstrings_size;
1045 	netdev_features_t net_hw_features;
1046 	netdev_features_t net_features;
1047 	netdev_features_t vlan_features;
1048 	int stats_len;
1049 	u32 tccr_mask;
1050 	u32 tx_max_frame_size;
1051 	u32 rx_max_frame_size;
1052 	u32 rx_buffer_size;
1053 	u32 rx_desc_size;
1054 	u32 dbat_entry_num;
1055 	unsigned aligned_tx: 1;
1056 	unsigned coalesce_irqs:1;	/* Needs software IRQ coalescing */
1057 
1058 	/* hardware features */
1059 	unsigned internal_delay:1;	/* AVB-DMAC has internal delays */
1060 	unsigned tx_counters:1;		/* E-MAC has TX counters */
1061 	unsigned carrier_counters:1;	/* E-MAC has carrier counters */
1062 	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
1063 	unsigned irq_en_dis:1;		/* Has separate irq enable and disable regs */
1064 	unsigned err_mgmt_irqs:1;	/* Line1 (Err) and Line2 (Mgmt) irqs are separate */
1065 	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
1066 	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
1067 	unsigned gptp_ref_clk:1;	/* gPTP has separate reference clock */
1068 	unsigned nc_queues:1;		/* AVB-DMAC has RX and TX NC queues */
1069 	unsigned magic_pkt:1;		/* E-MAC supports magic packet detection */
1070 	unsigned half_duplex:1;		/* E-MAC supports half duplex mode */
1071 };
1072 
1073 struct ravb_rx_buffer {
1074 	struct page *page;
1075 	unsigned int offset;
1076 };
1077 
1078 struct ravb_private {
1079 	struct net_device *ndev;
1080 	struct platform_device *pdev;
1081 	void __iomem *addr;
1082 	struct clk *clk;
1083 	struct clk *refclk;
1084 	struct clk *gptp_clk;
1085 	struct mdiobb_ctrl mdiobb;
1086 	u32 num_rx_ring[NUM_RX_QUEUE];
1087 	u32 num_tx_ring[NUM_TX_QUEUE];
1088 	u32 desc_bat_size;
1089 	dma_addr_t desc_bat_dma;
1090 	struct ravb_desc *desc_bat;
1091 	dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
1092 	dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
1093 	union {
1094 		struct ravb_rx_desc *desc;
1095 		struct ravb_ex_rx_desc *ex_desc;
1096 		void *raw;
1097 	} rx_ring[NUM_RX_QUEUE];
1098 	struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
1099 	void *tx_align[NUM_TX_QUEUE];
1100 	struct sk_buff *rx_1st_skb;
1101 	struct page_pool *rx_pool[NUM_RX_QUEUE];
1102 	struct ravb_rx_buffer *rx_buffers[NUM_RX_QUEUE];
1103 	struct sk_buff **tx_skb[NUM_TX_QUEUE];
1104 	u32 rx_over_errors;
1105 	u32 rx_fifo_errors;
1106 	struct net_device_stats stats[NUM_RX_QUEUE];
1107 	enum hwtstamp_tx_types tstamp_tx_ctrl;
1108 	enum hwtstamp_rx_filters tstamp_rx_ctrl;
1109 	struct list_head ts_skb_list;
1110 	u32 ts_skb_tag;
1111 	struct ravb_ptp ptp;
1112 	spinlock_t lock;		/* Register access lock */
1113 	u32 cur_rx[NUM_RX_QUEUE];	/* Consumer ring indices */
1114 	u32 dirty_rx[NUM_RX_QUEUE];	/* Producer ring indices */
1115 	u32 cur_tx[NUM_TX_QUEUE];
1116 	u32 dirty_tx[NUM_TX_QUEUE];
1117 	struct napi_struct napi[NUM_RX_QUEUE];
1118 	struct work_struct work;
1119 	/* MII transceiver section. */
1120 	struct mii_bus *mii_bus;	/* MDIO bus control */
1121 	int link;
1122 	phy_interface_t phy_interface;
1123 	int msg_enable;
1124 	int speed;
1125 	int emac_irq;
1126 
1127 	unsigned no_avb_link:1;
1128 	unsigned avb_link_active_low:1;
1129 	unsigned wol_enabled:1;
1130 	unsigned rxcidm:1;		/* RX Clock Internal Delay Mode */
1131 	unsigned txcidm:1;		/* TX Clock Internal Delay Mode */
1132 	unsigned rgmii_override:1;	/* Deprecated rgmii-*id behavior */
1133 	unsigned int num_tx_desc;	/* TX descriptors per packet */
1134 
1135 	int duplex;
1136 
1137 	const struct ravb_hw_info *info;
1138 	struct reset_control *rstc;
1139 
1140 	u32 gti_tiv;
1141 };
1142 
ravb_read(struct net_device * ndev,enum ravb_reg reg)1143 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
1144 {
1145 	struct ravb_private *priv = netdev_priv(ndev);
1146 
1147 	return ioread32(priv->addr + reg);
1148 }
1149 
ravb_write(struct net_device * ndev,u32 data,enum ravb_reg reg)1150 static inline void ravb_write(struct net_device *ndev, u32 data,
1151 			      enum ravb_reg reg)
1152 {
1153 	struct ravb_private *priv = netdev_priv(ndev);
1154 
1155 	iowrite32(data, priv->addr + reg);
1156 }
1157 
1158 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
1159 		 u32 set);
1160 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
1161 
1162 void ravb_ptp_interrupt(struct net_device *ndev);
1163 void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev);
1164 void ravb_ptp_stop(struct net_device *ndev);
1165 
1166 #endif	/* #ifndef __RAVB_H__ */
1167