1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // CS42L43 CODEC driver 4 // 5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/bitops.h> 9 #include <linux/bits.h> 10 #include <linux/build_bug.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/bitmap.h> 16 #include <linux/gcd.h> 17 #include <linux/irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/jiffies.h> 20 #include <linux/mfd/cs42l43.h> 21 #include <linux/mfd/cs42l43-regs.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/string.h> 28 #include <linux/workqueue.h> 29 #include <sound/control.h> 30 #include <sound/cs42l43.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/soc-component.h> 34 #include <sound/soc-dapm.h> 35 #include <sound/soc-dai.h> 36 #include <sound/soc.h> 37 #include <sound/tlv.h> 38 39 #include "cs42l43.h" 40 41 #define CS42L43_DECL_MUX(name, reg) \ 42 static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \ 43 0, CS42L43_MIXER_SRC_MASK, \ 44 cs42l43_mixer_texts, cs42l43_mixer_values); \ 45 static const struct snd_kcontrol_new cs42l43_##name##_mux = \ 46 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum) 47 48 #define CS42L43B_DECL_MUX(name, reg) \ 49 static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \ 50 0, CS42L43_MIXER_SRC_MASK, \ 51 cs42l43b_mixer_texts, cs42l43b_mixer_values); \ 52 static const struct snd_kcontrol_new cs42l43_##name##_mux = \ 53 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum) 54 55 #define CS42L43_DECL_MIXER(name, reg) \ 56 CS42L43_DECL_MUX(name##_in1, reg); \ 57 CS42L43_DECL_MUX(name##_in2, reg + 0x4); \ 58 CS42L43_DECL_MUX(name##_in3, reg + 0x8); \ 59 CS42L43_DECL_MUX(name##_in4, reg + 0xC) 60 61 #define CS42L43B_DECL_MIXER(name, reg) \ 62 CS42L43B_DECL_MUX(name##_in1, reg); \ 63 CS42L43B_DECL_MUX(name##_in2, reg + 0x4); \ 64 CS42L43B_DECL_MUX(name##_in3, reg + 0x8); \ 65 CS42L43B_DECL_MUX(name##_in4, reg + 0xC) 66 67 #define CS42L43_DAPM_MUX(name_str, name) \ 68 SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux) 69 70 #define CS42L43_DAPM_MIXER(name_str, name) \ 71 SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \ 72 SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \ 73 SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \ 74 SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \ 75 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0) 76 77 #define CS42L43_BASE_ROUTES(name_str) \ 78 { name_str, "Tone Generator 1", "Tone 1" }, \ 79 { name_str, "Tone Generator 2", "Tone 2" }, \ 80 { name_str, "Decimator 1", "Decimator 1" }, \ 81 { name_str, "Decimator 2", "Decimator 2" }, \ 82 { name_str, "Decimator 3", "Decimator 3" }, \ 83 { name_str, "Decimator 4", "Decimator 4" }, \ 84 { name_str, "ASPRX1", "ASPRX1" }, \ 85 { name_str, "ASPRX2", "ASPRX2" }, \ 86 { name_str, "ASPRX3", "ASPRX3" }, \ 87 { name_str, "ASPRX4", "ASPRX4" }, \ 88 { name_str, "ASPRX5", "ASPRX5" }, \ 89 { name_str, "ASPRX6", "ASPRX6" }, \ 90 { name_str, "DP5RX1", "DP5RX1" }, \ 91 { name_str, "DP5RX2", "DP5RX2" }, \ 92 { name_str, "DP6RX1", "DP6RX1" }, \ 93 { name_str, "DP6RX2", "DP6RX2" }, \ 94 { name_str, "DP7RX1", "DP7RX1" }, \ 95 { name_str, "DP7RX2", "DP7RX2" }, \ 96 { name_str, "ASRC INT1", "ASRC_INT1" }, \ 97 { name_str, "ASRC INT2", "ASRC_INT2" }, \ 98 { name_str, "ASRC INT3", "ASRC_INT3" }, \ 99 { name_str, "ASRC INT4", "ASRC_INT4" }, \ 100 { name_str, "ASRC DEC1", "ASRC_DEC1" }, \ 101 { name_str, "ASRC DEC2", "ASRC_DEC2" }, \ 102 { name_str, "ASRC DEC3", "ASRC_DEC3" }, \ 103 { name_str, "ASRC DEC4", "ASRC_DEC4" }, \ 104 { name_str, "ISRC1 INT1", "ISRC1INT1" }, \ 105 { name_str, "ISRC1 INT2", "ISRC1INT2" }, \ 106 { name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \ 107 { name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \ 108 { name_str, "ISRC2 INT1", "ISRC2INT1" }, \ 109 { name_str, "ISRC2 INT2", "ISRC2INT2" }, \ 110 { name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \ 111 { name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \ 112 { name_str, "EQ1", "EQ" }, \ 113 { name_str, "EQ2", "EQ" } 114 115 #define CS42L43B_BASE_ROUTES(name_str) \ 116 { name_str, "Decimator 5", "Decimator 5" }, \ 117 { name_str, "Decimator 6", "Decimator 6" }, \ 118 { name_str, "ISRC1 DEC3", "ISRC1DEC3" }, \ 119 { name_str, "ISRC1 DEC4", "ISRC1DEC4" }, \ 120 { name_str, "ISRC2 DEC3", "ISRC2DEC3" }, \ 121 { name_str, "ISRC2 DEC4", "ISRC2DEC4" } 122 123 #define CS42L43_MUX_ROUTES(name_str, widget) \ 124 { widget, NULL, name_str " Input" }, \ 125 { name_str " Input", NULL, "Mixer Core" }, \ 126 CS42L43_BASE_ROUTES(name_str " Input") 127 128 #define CS42L43B_MUX_ROUTES(name_str, widget) \ 129 CS42L43_MUX_ROUTES(name_str, widget), \ 130 CS42L43B_BASE_ROUTES(name_str " Input") 131 132 #define CS42L43_MIXER_ROUTES(name_str, widget) \ 133 { name_str " Mixer", NULL, name_str " Input 1" }, \ 134 { name_str " Mixer", NULL, name_str " Input 2" }, \ 135 { name_str " Mixer", NULL, name_str " Input 3" }, \ 136 { name_str " Mixer", NULL, name_str " Input 4" }, \ 137 { widget, NULL, name_str " Mixer" }, \ 138 { name_str " Mixer", NULL, "Mixer Core" }, \ 139 CS42L43_BASE_ROUTES(name_str " Input 1"), \ 140 CS42L43_BASE_ROUTES(name_str " Input 2"), \ 141 CS42L43_BASE_ROUTES(name_str " Input 3"), \ 142 CS42L43_BASE_ROUTES(name_str " Input 4") 143 144 #define CS42L43B_MIXER_ROUTES(name_str, widget) \ 145 CS42L43_MIXER_ROUTES(name_str, widget), \ 146 CS42L43B_BASE_ROUTES(name_str " Input 1"), \ 147 CS42L43B_BASE_ROUTES(name_str " Input 2"), \ 148 CS42L43B_BASE_ROUTES(name_str " Input 3"), \ 149 CS42L43B_BASE_ROUTES(name_str " Input 4") 150 151 #define CS42L43_MIXER_VOLUMES(name_str, base) \ 152 SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \ 153 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 154 cs42l43_mixer_tlv), \ 155 SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \ 156 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 157 cs42l43_mixer_tlv), \ 158 SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \ 159 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 160 cs42l43_mixer_tlv), \ 161 SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \ 162 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 163 cs42l43_mixer_tlv) 164 165 #define CS42L43_IRQ_ERROR(name) \ 166 static irqreturn_t cs42l43_##name(int irq, void *data) \ 167 { \ 168 struct cs42l43_codec *priv = data; \ 169 dev_err(priv->dev, "Error " #name " IRQ\n"); \ 170 return IRQ_HANDLED; \ 171 } 172 173 CS42L43_IRQ_ERROR(pll_lost_lock) 174 CS42L43_IRQ_ERROR(spkr_clock_stop) 175 CS42L43_IRQ_ERROR(spkl_clock_stop) 176 CS42L43_IRQ_ERROR(spkr_brown_out) 177 CS42L43_IRQ_ERROR(spkl_brown_out) 178 CS42L43_IRQ_ERROR(spkr_therm_shutdown) 179 CS42L43_IRQ_ERROR(spkl_therm_shutdown) 180 CS42L43_IRQ_ERROR(spkr_therm_warm) 181 CS42L43_IRQ_ERROR(spkl_therm_warm) 182 CS42L43_IRQ_ERROR(spkr_sc_detect) 183 CS42L43_IRQ_ERROR(spkl_sc_detect) 184 185 static void cs42l43_hp_ilimit_clear_work(struct work_struct *work) 186 { 187 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec, 188 hp_ilimit_clear_work.work); 189 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(priv->component); 190 191 snd_soc_dapm_mutex_lock(dapm); 192 193 priv->hp_ilimit_count--; 194 195 if (priv->hp_ilimit_count) 196 queue_delayed_work(system_dfl_wq, &priv->hp_ilimit_clear_work, 197 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS)); 198 199 snd_soc_dapm_mutex_unlock(dapm); 200 } 201 202 static irqreturn_t cs42l43_hp_ilimit(int irq, void *data) 203 { 204 struct cs42l43_codec *priv = data; 205 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(priv->component); 206 struct cs42l43 *cs42l43 = priv->core; 207 208 dev_dbg(priv->dev, "headphone ilimit IRQ\n"); 209 210 snd_soc_dapm_mutex_lock(dapm); 211 212 if (priv->hp_ilimit_count < CS42L43_HP_ILIMIT_MAX_COUNT) { 213 if (!priv->hp_ilimit_count) 214 queue_delayed_work(system_dfl_wq, &priv->hp_ilimit_clear_work, 215 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS)); 216 217 priv->hp_ilimit_count++; 218 snd_soc_dapm_mutex_unlock(dapm); 219 return IRQ_HANDLED; 220 } 221 222 dev_err(priv->dev, "Disabling headphone for %dmS, due to frequent current limit\n", 223 CS42L43_HP_ILIMIT_BACKOFF_MS); 224 225 priv->hp_ilimited = true; 226 227 // No need to wait for disable, as just disabling for a period of time 228 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, 229 CS42L43_HP_EN_MASK, 0); 230 231 snd_soc_dapm_mutex_unlock(dapm); 232 233 msleep(CS42L43_HP_ILIMIT_BACKOFF_MS); 234 235 snd_soc_dapm_mutex_lock(dapm); 236 237 if (priv->hp_ena && !priv->load_detect_running) { 238 unsigned long time_left; 239 240 reinit_completion(&priv->hp_startup); 241 242 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, 243 CS42L43_HP_EN_MASK, priv->hp_ena); 244 245 time_left = wait_for_completion_timeout(&priv->hp_startup, 246 msecs_to_jiffies(CS42L43_HP_TIMEOUT_MS)); 247 if (!time_left) 248 dev_err(priv->dev, "ilimit HP restore timed out\n"); 249 } 250 251 priv->hp_ilimited = false; 252 253 snd_soc_dapm_mutex_unlock(dapm); 254 255 return IRQ_HANDLED; 256 } 257 258 #define CS42L43_IRQ_COMPLETE(name) \ 259 static irqreturn_t cs42l43_##name(int irq, void *data) \ 260 { \ 261 struct cs42l43_codec *priv = data; \ 262 dev_dbg(priv->dev, #name " completed\n"); \ 263 complete(&priv->name); \ 264 return IRQ_HANDLED; \ 265 } 266 267 CS42L43_IRQ_COMPLETE(pll_ready) 268 CS42L43_IRQ_COMPLETE(hp_startup) 269 CS42L43_IRQ_COMPLETE(hp_shutdown) 270 CS42L43_IRQ_COMPLETE(type_detect) 271 CS42L43_IRQ_COMPLETE(spkr_shutdown) 272 CS42L43_IRQ_COMPLETE(spkl_shutdown) 273 CS42L43_IRQ_COMPLETE(spkr_startup) 274 CS42L43_IRQ_COMPLETE(spkl_startup) 275 CS42L43_IRQ_COMPLETE(load_detect) 276 277 static irqreturn_t cs42l43_mic_shutter(int irq, void *data) 278 { 279 struct cs42l43_codec *priv = data; 280 struct snd_soc_component *component = priv->component; 281 int i; 282 283 dev_dbg(priv->dev, "Microphone shutter changed\n"); 284 285 if (!component) 286 return IRQ_NONE; 287 288 for (i = 1; i < ARRAY_SIZE(priv->kctl); i++) { 289 if (!priv->kctl[i]) 290 return IRQ_NONE; 291 292 snd_ctl_notify(component->card->snd_card, 293 SNDRV_CTL_EVENT_MASK_VALUE, &priv->kctl[i]->id); 294 } 295 296 return IRQ_HANDLED; 297 } 298 299 static irqreturn_t cs42l43_spk_shutter(int irq, void *data) 300 { 301 struct cs42l43_codec *priv = data; 302 struct snd_soc_component *component = priv->component; 303 304 dev_dbg(priv->dev, "Speaker shutter changed\n"); 305 306 if (!component) 307 return IRQ_NONE; 308 309 if (!priv->kctl[0]) 310 return IRQ_NONE; 311 312 snd_ctl_notify(component->card->snd_card, 313 SNDRV_CTL_EVENT_MASK_VALUE, &priv->kctl[0]->id); 314 315 return IRQ_HANDLED; 316 } 317 318 static const unsigned int cs42l43_sample_rates[] = { 319 8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000, 320 }; 321 322 #define CS42L43_CONSUMER_RATE_MASK 0xFF 323 #define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer 324 325 static const struct snd_pcm_hw_constraint_list cs42l43_constraint = { 326 .count = ARRAY_SIZE(cs42l43_sample_rates), 327 .list = cs42l43_sample_rates, 328 }; 329 330 static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 331 { 332 struct snd_soc_component *component = dai->component; 333 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 334 struct cs42l43 *cs42l43 = priv->core; 335 int ret; 336 int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap, 337 CS42L43_ASP_CLK_CONFIG2, 338 CS42L43_ASP_MASTER_MODE_MASK); 339 340 if (provider) 341 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK; 342 else 343 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK; 344 345 if (cs42l43->variant_id == CS42L43_DEVID_VAL && (dai->id == 3 || dai->id == 4)) { 346 ret = snd_pcm_hw_constraint_minmax(substream->runtime, 347 SNDRV_PCM_HW_PARAM_CHANNELS, 348 1, 2); 349 if (ret < 0) 350 return ret; 351 } 352 353 return snd_pcm_hw_constraint_list(substream->runtime, 0, 354 SNDRV_PCM_HW_PARAM_RATE, 355 &priv->constraint); 356 } 357 358 static int cs42l43_convert_sample_rate(unsigned int rate) 359 { 360 switch (rate) { 361 case 8000: 362 return 0x11; 363 case 16000: 364 return 0x12; 365 case 24000: 366 return 0x02; 367 case 32000: 368 return 0x13; 369 case 44100: 370 return 0x0B; 371 case 48000: 372 return 0x03; 373 case 96000: 374 return 0x04; 375 case 192000: 376 return 0x05; 377 default: 378 return -EINVAL; 379 } 380 } 381 382 static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream, 383 struct snd_pcm_hw_params *params, 384 struct snd_soc_dai *dai) 385 { 386 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component); 387 struct cs42l43 *cs42l43 = priv->core; 388 int ret; 389 390 ret = cs42l43_convert_sample_rate(params_rate(params)); 391 if (ret < 0) { 392 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret); 393 return ret; 394 } 395 396 //FIXME: For now lets just set sample rate 1, this needs expanded in the future 397 regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1, 398 CS42L43_SAMPLE_RATE_MASK, ret); 399 400 return 0; 401 } 402 403 static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream, 404 struct snd_pcm_hw_params *params, 405 struct snd_soc_dai *dai) 406 { 407 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component); 408 struct cs42l43 *cs42l43 = priv->core; 409 int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL, 410 CS42L43_ASP_FSYNC_MODE_MASK); 411 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 412 CS42L43_ASP_MASTER_MODE_MASK); 413 int n_chans = params_channels(params); 414 int data_width = params_width(params); 415 int n_slots = n_chans; 416 int slot_width = data_width; 417 int frame, bclk_target, i; 418 unsigned int reg; 419 int *slots; 420 421 if (priv->n_slots) { 422 n_slots = priv->n_slots; 423 slot_width = priv->slot_width; 424 } 425 426 if (!dsp_mode && (n_slots & 0x1)) { 427 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n"); 428 n_slots++; 429 } 430 431 frame = n_slots * slot_width; 432 bclk_target = params_rate(params) * frame; 433 434 if (provider) { 435 unsigned int gcd_nm = gcd(bclk_target, CS42L43_INTERNAL_SYSCLK); 436 int n = bclk_target / gcd_nm; 437 int m = CS42L43_INTERNAL_SYSCLK / gcd_nm; 438 439 if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) || 440 m > CS42L43_ASP_BCLK_M_MASK) { 441 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target); 442 return -EINVAL; 443 } 444 445 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n", 446 n, m, bclk_target, n_slots, slot_width); 447 448 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1, 449 CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK, 450 n << CS42L43_ASP_BCLK_N_SHIFT | 451 m << CS42L43_ASP_BCLK_M_SHIFT); 452 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1, 453 CS42L43_ASP_FSYNC_M_MASK, frame); 454 } 455 456 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4, 457 CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK, 458 frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT); 459 460 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 461 reg = CS42L43_ASP_TX_CH1_CTRL; 462 slots = priv->tx_slots; 463 } else { 464 reg = CS42L43_ASP_RX_CH1_CTRL; 465 slots = priv->rx_slots; 466 } 467 468 for (i = 0; i < n_chans; i++, reg += 4) { 469 int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK); 470 int slot_pos; 471 472 if (dsp_mode) 473 slot_pos = slots[i] * slot_width; 474 else 475 slot_pos = (slots[i] / 2) * slot_width; 476 477 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n", 478 i, slots[i], slot_pos, slot_phase); 479 480 regmap_update_bits(cs42l43->regmap, reg, 481 CS42L43_ASP_CH_WIDTH_MASK | 482 CS42L43_ASP_CH_SLOT_MASK | 483 CS42L43_ASP_CH_SLOT_PHASE_MASK, 484 ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) | 485 (slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) | 486 slot_phase); 487 } 488 489 return cs42l43_set_sample_rate(substream, params, dai); 490 } 491 492 static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 493 { 494 struct snd_soc_component *component = dai->component; 495 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 496 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 497 struct cs42l43 *cs42l43 = priv->core; 498 int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 499 CS42L43_ASP_MASTER_MODE_MASK); 500 struct snd_soc_dapm_route routes[] = { 501 { "BCLK", NULL, "FSYNC" }, 502 }; 503 unsigned int asp_ctrl = 0; 504 unsigned int data_ctrl = 0; 505 unsigned int fsync_ctrl = 0; 506 unsigned int clk_config = 0; 507 508 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 509 case SND_SOC_DAIFMT_DSP_A: 510 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT; 511 fallthrough; 512 case SND_SOC_DAIFMT_DSP_B: 513 asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK; 514 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK; 515 break; 516 case SND_SOC_DAIFMT_I2S: 517 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT; 518 break; 519 case SND_SOC_DAIFMT_LEFT_J: 520 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK; 521 break; 522 default: 523 dev_err(priv->dev, "Unsupported DAI format 0x%x\n", 524 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 525 return -EINVAL; 526 } 527 528 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 529 case SND_SOC_DAIFMT_CBC_CFC: 530 if (provider) 531 snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes)); 532 break; 533 case SND_SOC_DAIFMT_CBP_CFP: 534 if (!provider) 535 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); 536 clk_config |= CS42L43_ASP_MASTER_MODE_MASK; 537 break; 538 default: 539 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n", 540 fmt & SND_SOC_DAIFMT_MASTER_MASK); 541 return -EINVAL; 542 } 543 544 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 545 case SND_SOC_DAIFMT_NB_NF: 546 clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */ 547 break; 548 case SND_SOC_DAIFMT_IB_NF: 549 break; 550 case SND_SOC_DAIFMT_NB_IF: 551 clk_config |= CS42L43_ASP_BCLK_INV_MASK; 552 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK | 553 CS42L43_ASP_FSYNC_OUT_INV_MASK; 554 break; 555 case SND_SOC_DAIFMT_IB_IF: 556 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK | 557 CS42L43_ASP_FSYNC_OUT_INV_MASK; 558 break; 559 default: 560 dev_err(priv->dev, "Unsupported invert mode 0x%x\n", 561 fmt & SND_SOC_DAIFMT_INV_MASK); 562 return -EINVAL; 563 } 564 565 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL, 566 CS42L43_ASP_FSYNC_MODE_MASK, 567 asp_ctrl); 568 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL, 569 CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK | 570 CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK, 571 data_ctrl); 572 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 573 CS42L43_ASP_MASTER_MODE_MASK | 574 CS42L43_ASP_BCLK_INV_MASK, 575 clk_config); 576 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3, 577 CS42L43_ASP_FSYNC_IN_INV_MASK | 578 CS42L43_ASP_FSYNC_OUT_INV_MASK, 579 fsync_ctrl); 580 581 return 0; 582 } 583 584 static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned long mask, 585 int *slots, unsigned int nslots) 586 { 587 int i = 0; 588 int slot; 589 590 for_each_set_bit(slot, &mask, BITS_PER_TYPE(mask)) { 591 if (i == nslots) { 592 dev_warn(priv->dev, "Too many channels in TDM mask: %lx\n", 593 mask); 594 return; 595 } 596 597 slots[i++] = slot; 598 } 599 600 } 601 602 static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 603 unsigned int rx_mask, int slots, int slot_width) 604 { 605 struct snd_soc_component *component = dai->component; 606 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 607 608 priv->n_slots = slots; 609 priv->slot_width = slot_width; 610 611 if (!slots) { 612 tx_mask = CS42L43_DEFAULT_SLOTS; 613 rx_mask = CS42L43_DEFAULT_SLOTS; 614 } 615 616 cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots, 617 ARRAY_SIZE(priv->tx_slots)); 618 cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots, 619 ARRAY_SIZE(priv->rx_slots)); 620 621 return 0; 622 } 623 624 static int cs42l43_dai_probe(struct snd_soc_dai *dai) 625 { 626 struct snd_soc_component *component = dai->component; 627 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 628 static const char * const controls[] = { 629 "Speaker Digital Switch", 630 "Decimator 1 Switch", 631 "Decimator 2 Switch", 632 "Decimator 3 Switch", 633 "Decimator 4 Switch", 634 "Decimator 5 Switch", 635 "Decimator 6 Switch", 636 }; 637 int control_size, i; 638 639 static_assert(ARRAY_SIZE(controls) == ARRAY_SIZE(priv->kctl)); 640 641 switch (priv->core->variant_id) { 642 case CS42L43_DEVID_VAL: 643 control_size = ARRAY_SIZE(controls) - 2; // ignore Decimator 5 and 6 644 break; 645 case CS42L43B_DEVID_VAL: 646 control_size = ARRAY_SIZE(controls); 647 break; 648 default: 649 return -EINVAL; 650 } 651 652 for (i = 0; i < control_size; i++) { 653 if (priv->kctl[i]) 654 continue; 655 656 priv->kctl[i] = snd_soc_component_get_kcontrol(component, controls[i]); 657 } 658 659 return 0; 660 } 661 662 static int cs42l43_dai_remove(struct snd_soc_dai *dai) 663 { 664 struct snd_soc_component *component = dai->component; 665 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 666 int i; 667 668 for (i = 0; i < ARRAY_SIZE(priv->kctl); i++) 669 priv->kctl[i] = NULL; 670 671 return 0; 672 } 673 674 static const struct snd_soc_dai_ops cs42l43_asp_ops = { 675 .probe = cs42l43_dai_probe, 676 .remove = cs42l43_dai_remove, 677 .startup = cs42l43_startup, 678 .hw_params = cs42l43_asp_hw_params, 679 .set_fmt = cs42l43_asp_set_fmt, 680 .set_tdm_slot = cs42l43_asp_set_tdm_slot, 681 }; 682 683 static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream, 684 struct snd_pcm_hw_params *params, 685 struct snd_soc_dai *dai) 686 { 687 int ret; 688 689 ret = cs42l43_sdw_add_peripheral(substream, params, dai); 690 if (ret) 691 return ret; 692 693 return cs42l43_set_sample_rate(substream, params, dai); 694 } 695 696 static const struct snd_soc_dai_ops cs42l43_sdw_ops = { 697 .probe = cs42l43_dai_probe, 698 .remove = cs42l43_dai_remove, 699 .startup = cs42l43_startup, 700 .set_stream = cs42l43_sdw_set_stream, 701 .hw_params = cs42l43_sdw_hw_params, 702 .hw_free = cs42l43_sdw_remove_peripheral, 703 }; 704 705 #define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 706 SNDRV_PCM_FMTBIT_S32_LE) 707 #define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 708 709 static struct snd_soc_dai_driver cs42l43_dais[] = { 710 { 711 .name = "cs42l43-asp", 712 .ops = &cs42l43_asp_ops, 713 .symmetric_rate = 1, 714 .capture = { 715 .stream_name = "ASP Capture", 716 .channels_min = 1, 717 .channels_max = CS42L43_ASP_MAX_CHANNELS, 718 .rates = SNDRV_PCM_RATE_KNOT, 719 .formats = CS42L43_ASP_FORMATS, 720 }, 721 .playback = { 722 .stream_name = "ASP Playback", 723 .channels_min = 1, 724 .channels_max = CS42L43_ASP_MAX_CHANNELS, 725 .rates = SNDRV_PCM_RATE_KNOT, 726 .formats = CS42L43_ASP_FORMATS, 727 }, 728 }, 729 { 730 .name = "cs42l43-dp1", 731 .id = 1, 732 .ops = &cs42l43_sdw_ops, 733 .capture = { 734 .stream_name = "DP1 Capture", 735 .channels_min = 1, 736 .channels_max = 4, 737 .rates = SNDRV_PCM_RATE_KNOT, 738 .formats = CS42L43_SDW_FORMATS, 739 }, 740 }, 741 { 742 .name = "cs42l43-dp2", 743 .id = 2, 744 .ops = &cs42l43_sdw_ops, 745 .capture = { 746 .stream_name = "DP2 Capture", 747 .channels_min = 1, 748 .channels_max = 2, 749 .rates = SNDRV_PCM_RATE_KNOT, 750 .formats = CS42L43_SDW_FORMATS, 751 }, 752 }, 753 { 754 .name = "cs42l43-dp3", 755 .id = 3, 756 .ops = &cs42l43_sdw_ops, 757 .capture = { 758 .stream_name = "DP3 Capture", 759 .channels_min = 1, 760 .channels_max = 4, 761 .rates = SNDRV_PCM_RATE_KNOT, 762 .formats = CS42L43_SDW_FORMATS, 763 }, 764 }, 765 { 766 .name = "cs42l43-dp4", 767 .id = 4, 768 .ops = &cs42l43_sdw_ops, 769 .capture = { 770 .stream_name = "DP4 Capture", 771 .channels_min = 1, 772 .channels_max = 4, 773 .rates = SNDRV_PCM_RATE_KNOT, 774 .formats = CS42L43_SDW_FORMATS, 775 }, 776 }, 777 { 778 .name = "cs42l43-dp5", 779 .id = 5, 780 .ops = &cs42l43_sdw_ops, 781 .playback = { 782 .stream_name = "DP5 Playback", 783 .channels_min = 1, 784 .channels_max = 2, 785 .rates = SNDRV_PCM_RATE_KNOT, 786 .formats = CS42L43_SDW_FORMATS, 787 }, 788 }, 789 { 790 .name = "cs42l43-dp6", 791 .id = 6, 792 .ops = &cs42l43_sdw_ops, 793 .playback = { 794 .stream_name = "DP6 Playback", 795 .channels_min = 1, 796 .channels_max = 2, 797 .rates = SNDRV_PCM_RATE_KNOT, 798 .formats = CS42L43_SDW_FORMATS, 799 }, 800 }, 801 { 802 .name = "cs42l43-dp7", 803 .id = 7, 804 .ops = &cs42l43_sdw_ops, 805 .playback = { 806 .stream_name = "DP7 Playback", 807 .channels_min = 1, 808 .channels_max = 2, 809 .rates = SNDRV_PCM_RATE_KNOT, 810 .formats = CS42L43_SDW_FORMATS, 811 }, 812 }, 813 }; 814 815 static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0); 816 817 static const char * const cs42l43_ramp_text[] = { 818 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", 819 "15ms/6dB", "30ms/6dB", 820 }; 821 822 static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" }; 823 824 static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1, 825 CS42L43_ADC_AIN_SEL_SHIFT, 826 cs42l43_adc1_input_text); 827 828 static const struct snd_kcontrol_new cs42l43_adc1_input_ctl = 829 SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input); 830 831 static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" }; 832 833 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text); 834 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text); 835 836 static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = { 837 SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode), 838 SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode), 839 }; 840 841 static const char * const cs42l43_pdm_clk_text[] = { 842 "3.072MHz", "1.536MHz", "768kHz", 843 }; 844 845 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL, 846 CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text); 847 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL, 848 CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text); 849 850 static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0); 851 static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0); 852 853 static const char * const cs42l43_wnf_corner_text[] = { 854 "160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", 855 }; 856 857 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1, 858 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 859 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2, 860 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 861 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3, 862 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 863 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, 864 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 865 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_wnf_corner, CS42L43B_DECIM_HPF_WNF_CTRL5, 866 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 867 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_wnf_corner, CS42L43B_DECIM_HPF_WNF_CTRL6, 868 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 869 870 static const char * const cs42l43_hpf_corner_text[] = { 871 "3Hz", "12Hz", "48Hz", "96Hz", 872 }; 873 874 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1, 875 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 876 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2, 877 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 878 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3, 879 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 880 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, 881 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 882 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_hpf_corner, CS42L43B_DECIM_HPF_WNF_CTRL5, 883 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 884 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_hpf_corner, CS42L43B_DECIM_HPF_WNF_CTRL6, 885 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 886 887 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 888 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text); 889 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 890 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text); 891 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 892 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text); 893 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 894 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text); 895 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 896 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text); 897 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 898 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text); 899 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 900 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text); 901 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 902 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text); 903 904 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec1_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 905 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text); 906 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec1_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 907 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text); 908 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec2_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 909 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text); 910 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec2_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 911 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text); 912 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec3_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 913 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text); 914 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec3_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 915 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text); 916 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec4_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 917 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text); 918 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec4_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 919 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text); 920 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 921 CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_SHIFT, cs42l43_ramp_text); 922 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 923 CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_SHIFT, cs42l43_ramp_text); 924 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 925 CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_SHIFT, cs42l43_ramp_text); 926 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 927 CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_SHIFT, cs42l43_ramp_text); 928 929 static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0); 930 931 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP, 932 CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text); 933 934 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP, 935 CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text); 936 937 static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1); 938 939 static const char * const cs42l43_headphone_ramp_text[] = { 940 "1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44", 941 "48", "66", "72", 942 }; 943 944 static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL, 945 CS42L43_HP_PATH_VOL_RAMP_SHIFT, 946 cs42l43_headphone_ramp_text); 947 948 static const char * const cs42l43_tone_freq_text[] = { 949 "1kHz", "2kHz", "4kHz", "6kHz", "8kHz", 950 }; 951 952 static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL, 953 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text); 954 955 static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL, 956 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text); 957 958 static const char * const cs42l43_mixer_texts[] = { 959 "None", 960 "Tone Generator 1", "Tone Generator 2", 961 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4", 962 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6", 963 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2", 964 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4", 965 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4", 966 "ISRC1 INT1", "ISRC1 INT2", 967 "ISRC1 DEC1", "ISRC1 DEC2", 968 "ISRC2 INT1", "ISRC2 INT2", 969 "ISRC2 DEC1", "ISRC2 DEC2", 970 "EQ1", "EQ2", 971 }; 972 973 static const unsigned int cs42l43_mixer_values[] = { 974 0x00, // None 975 0x04, 0x05, // Tone Generator 1, 2 976 0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4 977 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6 978 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2 979 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4 980 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4 981 0x50, 0x51, // ISRC1 INT1, 2 982 0x52, 0x53, // ISRC1 DEC1, 2 983 0x54, 0x55, // ISRC2 INT1, 2 984 0x56, 0x57, // ISRC2 DEC1, 2 985 0x58, 0x59, // EQ1, 2 986 }; 987 988 static const char * const cs42l43b_mixer_texts[] = { 989 "None", 990 "Tone Generator 1", "Tone Generator 2", 991 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4", "Decimator 5", "Decimator 6", 992 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6", 993 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2", 994 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4", 995 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4", 996 "ISRC1 INT1", "ISRC1 INT2", 997 "ISRC1 DEC1", "ISRC1 DEC2", "ISRC1 DEC3", "ISRC1 DEC4", 998 "ISRC2 INT1", "ISRC2 INT2", 999 "ISRC2 DEC1", "ISRC2 DEC2", "ISRC2 DEC3", "ISRC2 DEC4", 1000 "EQ1", "EQ2", 1001 }; 1002 1003 static const unsigned int cs42l43b_mixer_values[] = { 1004 0x00, // None 1005 0x04, 0x05, // Tone Generator 1, 2 1006 0x10, 0x11, 0x80, 0x81, 0x12, 0x13, // Decimator 1, 2, 3, 4, 5, 6 1007 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6 1008 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2 1009 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4 1010 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4 1011 0x50, 0x51, // ISRC1 INT1, 2 1012 0x52, 0x53, 0x78, 0x79, // ISRC1 DEC1, 2, 3, 4 1013 0x54, 0x55, // ISRC2 INT1, 2 1014 0x56, 0x57, 0x7A, 0x7B, // ISRC2 DEC1, 2, 3, 4 1015 0x58, 0x59, // EQ1, 2 1016 }; 1017 1018 /* A variant */ 1019 CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT); 1020 CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT); 1021 CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT); 1022 CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT); 1023 CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT); 1024 CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT); 1025 1026 CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT); 1027 CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT); 1028 CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT); 1029 CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT); 1030 CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT); 1031 CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT); 1032 CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT); 1033 CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT); 1034 CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT); 1035 CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT); 1036 1037 CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1); 1038 CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1); 1039 CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1); 1040 CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1); 1041 CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1); 1042 CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1); 1043 CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1); 1044 CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1); 1045 1046 CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1); 1047 CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1); 1048 CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1); 1049 CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1); 1050 CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1); 1051 CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1); 1052 CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1); 1053 CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1); 1054 1055 CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1); 1056 CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1); 1057 1058 CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1); 1059 CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1); 1060 1061 CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1); 1062 CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1); 1063 1064 CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1); 1065 CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1); 1066 1067 /* B variant */ 1068 CS42L43B_DECL_MUX(b_asptx1, CS42L43_ASPTX1_INPUT); 1069 CS42L43B_DECL_MUX(b_asptx2, CS42L43_ASPTX2_INPUT); 1070 CS42L43B_DECL_MUX(b_asptx3, CS42L43_ASPTX3_INPUT); 1071 CS42L43B_DECL_MUX(b_asptx4, CS42L43_ASPTX4_INPUT); 1072 CS42L43B_DECL_MUX(b_asptx5, CS42L43_ASPTX5_INPUT); 1073 CS42L43B_DECL_MUX(b_asptx6, CS42L43_ASPTX6_INPUT); 1074 1075 CS42L43B_DECL_MUX(b_dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT); 1076 CS42L43B_DECL_MUX(b_dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT); 1077 CS42L43B_DECL_MUX(b_dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT); 1078 CS42L43B_DECL_MUX(b_dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT); 1079 CS42L43B_DECL_MUX(b_dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT); 1080 CS42L43B_DECL_MUX(b_dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT); 1081 CS42L43B_DECL_MUX(b_dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT); 1082 CS42L43B_DECL_MUX(b_dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT); 1083 CS42L43B_DECL_MUX(b_dp3tx3, CS42L43B_SWIRE_DP3_CH3_INPUT); 1084 CS42L43B_DECL_MUX(b_dp3tx4, CS42L43B_SWIRE_DP3_CH4_INPUT); 1085 CS42L43B_DECL_MUX(b_dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT); 1086 CS42L43B_DECL_MUX(b_dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT); 1087 CS42L43B_DECL_MUX(b_dp4tx3, CS42L43B_SWIRE_DP4_CH3_INPUT); 1088 CS42L43B_DECL_MUX(b_dp4tx4, CS42L43B_SWIRE_DP4_CH4_INPUT); 1089 1090 CS42L43B_DECL_MUX(b_asrcint1, CS42L43_ASRC_INT1_INPUT1); 1091 CS42L43B_DECL_MUX(b_asrcint2, CS42L43_ASRC_INT2_INPUT1); 1092 CS42L43B_DECL_MUX(b_asrcint3, CS42L43_ASRC_INT3_INPUT1); 1093 CS42L43B_DECL_MUX(b_asrcint4, CS42L43_ASRC_INT4_INPUT1); 1094 CS42L43B_DECL_MUX(b_asrcdec1, CS42L43_ASRC_DEC1_INPUT1); 1095 CS42L43B_DECL_MUX(b_asrcdec2, CS42L43_ASRC_DEC2_INPUT1); 1096 CS42L43B_DECL_MUX(b_asrcdec3, CS42L43_ASRC_DEC3_INPUT1); 1097 CS42L43B_DECL_MUX(b_asrcdec4, CS42L43_ASRC_DEC4_INPUT1); 1098 1099 CS42L43B_DECL_MUX(b_isrc1int1, CS42L43_ISRC1INT1_INPUT1); 1100 CS42L43B_DECL_MUX(b_isrc1int2, CS42L43_ISRC1INT2_INPUT1); 1101 CS42L43B_DECL_MUX(b_isrc1dec1, CS42L43_ISRC1DEC1_INPUT1); 1102 CS42L43B_DECL_MUX(b_isrc1dec2, CS42L43_ISRC1DEC2_INPUT1); 1103 CS42L43B_DECL_MUX(b_isrc1dec3, CS42L43B_ISRC1DEC3_INPUT1); 1104 CS42L43B_DECL_MUX(b_isrc1dec4, CS42L43B_ISRC1DEC4_INPUT1); 1105 CS42L43B_DECL_MUX(b_isrc2int1, CS42L43_ISRC2INT1_INPUT1); 1106 CS42L43B_DECL_MUX(b_isrc2int2, CS42L43_ISRC2INT2_INPUT1); 1107 CS42L43B_DECL_MUX(b_isrc2dec1, CS42L43_ISRC2DEC1_INPUT1); 1108 CS42L43B_DECL_MUX(b_isrc2dec2, CS42L43_ISRC2DEC2_INPUT1); 1109 CS42L43B_DECL_MUX(b_isrc2dec3, CS42L43B_ISRC2DEC3_INPUT1); 1110 CS42L43B_DECL_MUX(b_isrc2dec4, CS42L43B_ISRC2DEC4_INPUT1); 1111 1112 CS42L43B_DECL_MUX(b_spdif1, CS42L43_SPDIF1_INPUT1); 1113 CS42L43B_DECL_MUX(b_spdif2, CS42L43_SPDIF2_INPUT1); 1114 1115 CS42L43B_DECL_MIXER(b_eq1, CS42L43_EQ1MIX_INPUT1); 1116 CS42L43B_DECL_MIXER(b_eq2, CS42L43_EQ2MIX_INPUT1); 1117 1118 CS42L43B_DECL_MIXER(b_amp1, CS42L43_AMP1MIX_INPUT1); 1119 CS42L43B_DECL_MIXER(b_amp2, CS42L43_AMP2MIX_INPUT1); 1120 1121 CS42L43B_DECL_MIXER(b_amp3, CS42L43_AMP3MIX_INPUT1); 1122 CS42L43B_DECL_MIXER(b_amp4, CS42L43_AMP4MIX_INPUT1); 1123 1124 static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol, 1125 struct snd_ctl_elem_value *ucontrol) 1126 { 1127 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1128 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1129 int ret; 1130 1131 snd_soc_dapm_mutex_lock(dapm); 1132 ret = snd_soc_get_volsw(kcontrol, ucontrol); 1133 snd_soc_dapm_mutex_unlock(dapm); 1134 1135 return ret; 1136 } 1137 1138 static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol, 1139 struct snd_ctl_elem_value *ucontrol) 1140 { 1141 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1142 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1143 int ret; 1144 1145 snd_soc_dapm_mutex_lock(dapm); 1146 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1147 snd_soc_dapm_mutex_unlock(dapm); 1148 1149 return ret; 1150 } 1151 1152 static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol, 1153 struct snd_ctl_elem_value *ucontrol) 1154 { 1155 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1156 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1157 int ret; 1158 1159 snd_soc_dapm_mutex_lock(dapm); 1160 ret = snd_soc_get_enum_double(kcontrol, ucontrol); 1161 snd_soc_dapm_mutex_unlock(dapm); 1162 1163 return ret; 1164 } 1165 1166 static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol, 1167 struct snd_ctl_elem_value *ucontrol) 1168 { 1169 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1170 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1171 int ret; 1172 1173 snd_soc_dapm_mutex_lock(dapm); 1174 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1175 snd_soc_dapm_mutex_unlock(dapm); 1176 1177 return ret; 1178 } 1179 1180 static int cs42l43_eq_get(struct snd_kcontrol *kcontrol, 1181 struct snd_ctl_elem_value *ucontrol) 1182 { 1183 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1184 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1185 1186 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs)); 1187 1188 return 0; 1189 } 1190 1191 static int cs42l43_eq_put(struct snd_kcontrol *kcontrol, 1192 struct snd_ctl_elem_value *ucontrol) 1193 { 1194 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1195 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1196 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1197 1198 snd_soc_dapm_mutex_lock(dapm); 1199 1200 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs)); 1201 1202 snd_soc_dapm_mutex_unlock(dapm); 1203 1204 return 0; 1205 } 1206 1207 static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv) 1208 { 1209 struct cs42l43 *cs42l43 = priv->core; 1210 1211 mutex_lock(&priv->spk_vu_lock); 1212 1213 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1, 1214 CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK); 1215 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1, 1216 CS42L43_AMP1_2_VU_MASK, 0); 1217 1218 mutex_unlock(&priv->spk_vu_lock); 1219 } 1220 1221 static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift) 1222 { 1223 struct cs42l43 *cs42l43 = priv->core; 1224 unsigned int val; 1225 int ret; 1226 1227 ret = pm_runtime_resume_and_get(priv->dev); 1228 if (ret) { 1229 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret); 1230 return ret; 1231 } 1232 1233 /* 1234 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must 1235 * be cached for the non-volatiles, so drop it from the cache here so 1236 * we force a read. 1237 */ 1238 ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, 1239 CS42L43_SHUTTER_CONTROL); 1240 if (ret) { 1241 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret); 1242 goto error; 1243 } 1244 1245 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val); 1246 if (ret) { 1247 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret); 1248 goto error; 1249 } 1250 1251 ret = !(val & BIT(shift)); 1252 1253 dev_dbg(priv->dev, "%s shutter is %s\n", 1254 BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker", 1255 ret ? "open" : "closed"); 1256 1257 error: 1258 pm_runtime_put_autosuspend(priv->dev); 1259 1260 return ret; 1261 } 1262 1263 static int cs42l43_decim_get(struct snd_kcontrol *kcontrol, 1264 struct snd_ctl_elem_value *ucontrol) 1265 { 1266 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1267 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1268 int ret; 1269 1270 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT); 1271 if (ret > 0) 1272 ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol); 1273 else if (!ret) 1274 ucontrol->value.integer.value[0] = ret; 1275 1276 return ret; 1277 } 1278 1279 static int cs42l43_spk_get(struct snd_kcontrol *kcontrol, 1280 struct snd_ctl_elem_value *ucontrol) 1281 { 1282 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1283 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1284 int ret; 1285 1286 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT); 1287 if (ret > 0) 1288 ret = snd_soc_get_volsw(kcontrol, ucontrol); 1289 else if (!ret) 1290 ucontrol->value.integer.value[0] = ret; 1291 1292 return ret; 1293 } 1294 1295 static int cs42l43_spk_put(struct snd_kcontrol *kcontrol, 1296 struct snd_ctl_elem_value *ucontrol) 1297 { 1298 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1299 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1300 int ret; 1301 1302 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1303 if (ret > 0) 1304 cs42l43_spk_vu_sync(priv); 1305 1306 return ret; 1307 } 1308 1309 static const struct snd_kcontrol_new cs42l43_controls[] = { 1310 SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum, 1311 cs42l43_jack_get, cs42l43_jack_put), 1312 1313 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2, 1314 CS42L43_ADC_PGA_GAIN_SHIFT, 1315 0xF, 4, cs42l43_adc_tlv), 1316 1317 SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL, 1318 CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0), 1319 SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL, 1320 CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0), 1321 SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk), 1322 SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk), 1323 1324 SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1, 1325 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1326 SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2, 1327 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1328 SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3, 1329 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1330 SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4, 1331 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1332 1333 SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner), 1334 SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner), 1335 SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner), 1336 SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner), 1337 1338 SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1, 1339 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1340 SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2, 1341 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1342 SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3, 1343 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1344 SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4, 1345 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1346 1347 SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner), 1348 SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner), 1349 SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner), 1350 SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner), 1351 1352 SOC_DOUBLE_R_EXT("Speaker Digital Switch", 1353 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, 1354 CS42L43_AMP_MUTE_SHIFT, 1, 1, 1355 cs42l43_spk_get, cs42l43_spk_put), 1356 1357 SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume", 1358 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, 1359 CS42L43_AMP_VOL_SHIFT, 1360 0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put, 1361 cs42l43_speaker_tlv), 1362 1363 SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up), 1364 SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down), 1365 1366 CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1), 1367 CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1), 1368 1369 SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL, 1370 CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT, 1371 0x11B, 229, cs42l43_headphone_tlv), 1372 1373 SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1, 1374 CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0), 1375 1376 SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL, 1377 CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0), 1378 SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL, 1379 CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0), 1380 SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp), 1381 1382 CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1), 1383 CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1), 1384 1385 SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq), 1386 SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq), 1387 1388 SOC_DOUBLE_EXT("EQ Switch", 1389 CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT, 1390 CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1, 1391 cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw), 1392 1393 SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS, 1394 cs42l43_eq_get, cs42l43_eq_put), 1395 1396 CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1), 1397 CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1), 1398 }; 1399 1400 static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w, 1401 struct snd_kcontrol *kcontrol, int event) 1402 { 1403 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1404 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1405 struct cs42l43 *cs42l43 = priv->core; 1406 unsigned int val; 1407 int i, ret; 1408 1409 switch (event) { 1410 case SND_SOC_DAPM_PRE_PMU: 1411 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0, 1412 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 1413 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK); 1414 1415 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0, 1416 CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK); 1417 1418 for (i = 0; i < CS42L43_N_EQ_COEFFS; i++) 1419 regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0, 1420 priv->eq_coeffs[i]); 1421 1422 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0, 1423 CS42L43_WRITE_MODE_MASK, 0); 1424 1425 return 0; 1426 case SND_SOC_DAPM_POST_PMU: 1427 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0, 1428 val, (val & CS42L43_INITIALIZE_DONE_MASK), 1429 2000, 10000); 1430 if (ret) 1431 dev_err(priv->dev, "Failed to start EQs: %d\n", ret); 1432 1433 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0, 1434 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 0); 1435 return ret; 1436 default: 1437 return 0; 1438 } 1439 } 1440 1441 struct cs42l43_pll_config { 1442 unsigned int freq; 1443 1444 unsigned int div; 1445 unsigned int mode; 1446 unsigned int cal; 1447 }; 1448 1449 static const struct cs42l43_pll_config cs42l43_pll_configs[] = { 1450 { 2400000, 0x50000000, 0x1, 0xA4 }, 1451 { 3000000, 0x40000000, 0x1, 0x83 }, 1452 { 3072000, 0x40000000, 0x3, 0x80 }, 1453 }; 1454 1455 static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src, 1456 unsigned int freq) 1457 { 1458 struct cs42l43 *cs42l43 = priv->core; 1459 1460 lockdep_assert_held(&cs42l43->pll_lock); 1461 1462 if (priv->refclk_src == src && priv->refclk_freq == freq) 1463 return 0; 1464 1465 if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) { 1466 dev_err(priv->dev, "PLL active, can't change configuration\n"); 1467 return -EBUSY; 1468 } 1469 1470 switch (src) { 1471 case CS42L43_SYSCLK_MCLK: 1472 case CS42L43_SYSCLK_SDW: 1473 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n", 1474 src ? "SoundWire" : "MCLK", freq); 1475 1476 priv->refclk_src = src; 1477 priv->refclk_freq = freq; 1478 1479 return 0; 1480 default: 1481 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src); 1482 return -EINVAL; 1483 } 1484 } 1485 1486 static int cs42l43_enable_pll(struct cs42l43_codec *priv) 1487 { 1488 static const struct reg_sequence enable_seq[] = { 1489 { CS42L43_OSC_DIV_SEL, 0x0, }, 1490 { CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, }, 1491 }; 1492 struct cs42l43 *cs42l43 = priv->core; 1493 const struct cs42l43_pll_config *config = NULL; 1494 unsigned int div = 0; 1495 unsigned int freq = priv->refclk_freq; 1496 unsigned long time_left; 1497 1498 lockdep_assert_held(&cs42l43->pll_lock); 1499 1500 if (priv->refclk_src == CS42L43_SYSCLK_SDW) { 1501 if (!freq) 1502 freq = cs42l43->sdw_freq; 1503 else if (!cs42l43->sdw_freq) 1504 cs42l43->sdw_freq = freq; 1505 } 1506 1507 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq); 1508 1509 div = fls(freq) - 1510 fls(cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq); 1511 freq >>= div; 1512 1513 if (div <= CS42L43_PLL_REFCLK_DIV_MASK) { 1514 int i; 1515 1516 for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) { 1517 if (freq == cs42l43_pll_configs[i].freq) { 1518 config = &cs42l43_pll_configs[i]; 1519 break; 1520 } 1521 } 1522 } 1523 1524 if (!config) { 1525 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq); 1526 return -EINVAL; 1527 } 1528 1529 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1530 CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK, 1531 div << CS42L43_PLL_REFCLK_DIV_SHIFT | 1532 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT); 1533 regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div); 1534 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, 1535 CS42L43_PLL_MODE_BYPASS_500_MASK | 1536 CS42L43_PLL_MODE_BYPASS_1029_MASK, 1537 config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT); 1538 regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO, 1539 CS42L43_PLL_CAL_RATIO_MASK, config->cal); 1540 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1541 CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK); 1542 1543 reinit_completion(&priv->pll_ready); 1544 1545 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, 1546 CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK); 1547 1548 time_left = wait_for_completion_timeout(&priv->pll_ready, 1549 msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS)); 1550 if (!time_left) { 1551 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, 1552 CS42L43_PLL_EN_MASK, 0); 1553 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1554 CS42L43_PLL_REFCLK_EN_MASK, 0); 1555 1556 dev_err(priv->dev, "Timeout out waiting for PLL\n"); 1557 return -ETIMEDOUT; 1558 } 1559 1560 if (priv->refclk_src == CS42L43_SYSCLK_SDW) 1561 cs42l43->sdw_pll_active = true; 1562 1563 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left)); 1564 1565 /* 1566 * Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL, 1567 * but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole 1568 * change over happens under the regmap lock to prevent any reads. 1569 */ 1570 regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq)); 1571 1572 return 0; 1573 } 1574 1575 static int cs42l43_disable_pll(struct cs42l43_codec *priv) 1576 { 1577 static const struct reg_sequence disable_seq[] = { 1578 { CS42L43_MCLK_SRC_SEL, 0x0, 5, }, 1579 { CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, }, 1580 }; 1581 struct cs42l43 *cs42l43 = priv->core; 1582 1583 dev_dbg(priv->dev, "Disabling PLL\n"); 1584 1585 lockdep_assert_held(&cs42l43->pll_lock); 1586 1587 regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq)); 1588 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0); 1589 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1590 CS42L43_PLL_REFCLK_EN_MASK, 0); 1591 1592 cs42l43->sdw_pll_active = false; 1593 1594 return 0; 1595 } 1596 1597 static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w, 1598 struct snd_kcontrol *kcontrol, int event) 1599 { 1600 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1601 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1602 struct cs42l43 *cs42l43 = priv->core; 1603 int ret; 1604 1605 mutex_lock(&cs42l43->pll_lock); 1606 1607 switch (event) { 1608 case SND_SOC_DAPM_PRE_PMU: 1609 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) { 1610 ret = clk_prepare_enable(priv->mclk); 1611 if (ret) { 1612 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret); 1613 break; 1614 } 1615 } 1616 1617 ret = cs42l43_enable_pll(priv); 1618 break; 1619 case SND_SOC_DAPM_POST_PMD: 1620 ret = cs42l43_disable_pll(priv); 1621 1622 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) 1623 clk_disable_unprepare(priv->mclk); 1624 break; 1625 default: 1626 ret = 0; 1627 break; 1628 } 1629 1630 mutex_unlock(&cs42l43->pll_lock); 1631 1632 return ret; 1633 } 1634 1635 static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd, 1636 int event, int timeout_ms) 1637 { 1638 unsigned long time_left; 1639 1640 switch (event) { 1641 case SND_SOC_DAPM_PRE_PMU: 1642 reinit_completion(pmu); 1643 return 0; 1644 case SND_SOC_DAPM_PRE_PMD: 1645 reinit_completion(pmd); 1646 return 0; 1647 case SND_SOC_DAPM_POST_PMU: 1648 time_left = wait_for_completion_timeout(pmu, msecs_to_jiffies(timeout_ms)); 1649 break; 1650 case SND_SOC_DAPM_POST_PMD: 1651 time_left = wait_for_completion_timeout(pmd, msecs_to_jiffies(timeout_ms)); 1652 break; 1653 default: 1654 return 0; 1655 } 1656 1657 if (!time_left) 1658 return -ETIMEDOUT; 1659 else 1660 return 0; 1661 } 1662 1663 static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w, 1664 struct snd_kcontrol *kcontrol, int event) 1665 { 1666 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1667 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1668 1669 return cs42l43_dapm_wait_completion(&priv->spkr_startup, 1670 &priv->spkr_shutdown, event, 1671 CS42L43_SPK_TIMEOUT_MS); 1672 } 1673 1674 static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w, 1675 struct snd_kcontrol *kcontrol, int event) 1676 { 1677 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1678 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1679 1680 return cs42l43_dapm_wait_completion(&priv->spkl_startup, 1681 &priv->spkl_shutdown, event, 1682 CS42L43_SPK_TIMEOUT_MS); 1683 } 1684 1685 static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w, 1686 struct snd_kcontrol *kcontrol, int event) 1687 { 1688 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1689 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1690 struct cs42l43 *cs42l43 = priv->core; 1691 unsigned int mask = 1 << w->shift; 1692 unsigned int val = 0; 1693 int ret; 1694 1695 switch (event) { 1696 case SND_SOC_DAPM_PRE_PMU: 1697 val = mask; 1698 fallthrough; 1699 case SND_SOC_DAPM_PRE_PMD: 1700 priv->hp_ena &= ~mask; 1701 priv->hp_ena |= val; 1702 1703 ret = cs42l43_dapm_wait_completion(&priv->hp_startup, 1704 &priv->hp_shutdown, event, 1705 CS42L43_HP_TIMEOUT_MS); 1706 if (ret) 1707 return ret; 1708 1709 if (!priv->load_detect_running && !priv->hp_ilimited) 1710 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, 1711 mask, val); 1712 break; 1713 case SND_SOC_DAPM_POST_PMU: 1714 case SND_SOC_DAPM_POST_PMD: 1715 if (priv->load_detect_running || priv->hp_ilimited) 1716 break; 1717 1718 ret = cs42l43_dapm_wait_completion(&priv->hp_startup, 1719 &priv->hp_shutdown, event, 1720 CS42L43_HP_TIMEOUT_MS); 1721 if (ret) 1722 return ret; 1723 break; 1724 default: 1725 break; 1726 } 1727 1728 return 0; 1729 } 1730 1731 static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w, 1732 struct snd_kcontrol *kcontrol, int event) 1733 { 1734 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1735 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1736 struct cs42l43 *cs42l43 = priv->core; 1737 unsigned int reg, ramp, mute; 1738 unsigned int *val; 1739 int ret; 1740 1741 if (cs42l43->variant_id == CS42L43_DEVID_VAL) { 1742 switch (w->shift) { 1743 case CS42L43_ADC1_EN_SHIFT: 1744 case CS42L43_PDM1_DIN_L_EN_SHIFT: 1745 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1746 ramp = CS42L43_DECIM1_VD_RAMP_MASK; 1747 mute = CS42L43_DECIM1_MUTE_MASK; 1748 val = &priv->decim_cache[0]; 1749 break; 1750 case CS42L43_ADC2_EN_SHIFT: 1751 case CS42L43_PDM1_DIN_R_EN_SHIFT: 1752 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1753 ramp = CS42L43_DECIM2_VD_RAMP_MASK; 1754 mute = CS42L43_DECIM2_MUTE_MASK; 1755 val = &priv->decim_cache[1]; 1756 break; 1757 case CS42L43_PDM2_DIN_L_EN_SHIFT: 1758 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1759 ramp = CS42L43_DECIM3_VD_RAMP_MASK; 1760 mute = CS42L43_DECIM3_MUTE_MASK; 1761 val = &priv->decim_cache[2]; 1762 break; 1763 case CS42L43_PDM2_DIN_R_EN_SHIFT: 1764 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1765 ramp = CS42L43_DECIM4_VD_RAMP_MASK; 1766 mute = CS42L43_DECIM4_MUTE_MASK; 1767 val = &priv->decim_cache[3]; 1768 break; 1769 default: 1770 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); 1771 return -EINVAL; 1772 } 1773 } else if (cs42l43->variant_id == CS42L43B_DEVID_VAL) { 1774 switch (w->shift) { 1775 case CS42L43_ADC1_EN_SHIFT: 1776 reg = CS42L43B_DECIM_VOL_CTRL_CH1_CH2; 1777 ramp = CS42L43_DECIM1_VD_RAMP_MASK; 1778 mute = CS42L43_DECIM1_MUTE_MASK; 1779 val = &priv->decim_cache[0]; 1780 break; 1781 case CS42L43_ADC2_EN_SHIFT: 1782 reg = CS42L43B_DECIM_VOL_CTRL_CH1_CH2; 1783 ramp = CS42L43_DECIM2_VD_RAMP_MASK; 1784 mute = CS42L43_DECIM2_MUTE_MASK; 1785 val = &priv->decim_cache[1]; 1786 break; 1787 case CS42L43_PDM1_DIN_L_EN_SHIFT: 1788 reg = CS42L43B_DECIM_VOL_CTRL_CH3_CH4; 1789 ramp = CS42L43_DECIM3_VD_RAMP_MASK; 1790 mute = CS42L43_DECIM3_MUTE_MASK; 1791 val = &priv->decim_cache[2]; 1792 break; 1793 case CS42L43_PDM1_DIN_R_EN_SHIFT: 1794 reg = CS42L43B_DECIM_VOL_CTRL_CH3_CH4; 1795 ramp = CS42L43_DECIM4_VD_RAMP_MASK; 1796 mute = CS42L43_DECIM4_MUTE_MASK; 1797 val = &priv->decim_cache[3]; 1798 break; 1799 case CS42L43_PDM2_DIN_L_EN_SHIFT: 1800 reg = CS42L43B_DECIM_VOL_CTRL_CH5_CH6; 1801 ramp = CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_MASK; 1802 mute = CS42L43B_DECIM5_MUTE_MASK; 1803 val = &priv->decim_cache[4]; 1804 break; 1805 case CS42L43_PDM2_DIN_R_EN_SHIFT: 1806 reg = CS42L43B_DECIM_VOL_CTRL_CH5_CH6; 1807 ramp = CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_MASK; 1808 mute = CS42L43B_DECIM6_MUTE_MASK; 1809 val = &priv->decim_cache[5]; 1810 break; 1811 default: 1812 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); 1813 return -EINVAL; 1814 } 1815 } else { 1816 return -EINVAL; 1817 } 1818 1819 switch (event) { 1820 case SND_SOC_DAPM_PRE_PMU: 1821 ret = regmap_read(cs42l43->regmap, reg, val); 1822 if (ret) { 1823 dev_err(priv->dev, 1824 "Failed to cache decimator settings: %d\n", 1825 ret); 1826 return ret; 1827 } 1828 1829 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute); 1830 break; 1831 case SND_SOC_DAPM_POST_PMU: 1832 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val); 1833 break; 1834 default: 1835 break; 1836 } 1837 1838 return 0; 1839 } 1840 1841 static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w, 1842 struct snd_kcontrol *kcontrol, int event) 1843 { 1844 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1845 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1846 struct cs42l43 *cs42l43 = priv->core; 1847 unsigned int mask = 1 << w->shift; 1848 unsigned int val = 0; 1849 int ret; 1850 1851 ret = cs42l43_mic_ev(w, kcontrol, event); 1852 if (ret) 1853 return ret; 1854 1855 switch (event) { 1856 case SND_SOC_DAPM_PRE_PMU: 1857 val = mask; 1858 fallthrough; 1859 case SND_SOC_DAPM_PRE_PMD: 1860 priv->adc_ena &= ~mask; 1861 priv->adc_ena |= val; 1862 1863 if (!priv->load_detect_running) 1864 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3, 1865 mask, val); 1866 fallthrough; 1867 default: 1868 return 0; 1869 } 1870 } 1871 1872 static const struct snd_soc_dapm_widget cs42l43_widgets[] = { 1873 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev, 1874 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1875 1876 SND_SOC_DAPM_INPUT("ADC1_IN1_P"), 1877 SND_SOC_DAPM_INPUT("ADC1_IN1_N"), 1878 SND_SOC_DAPM_INPUT("ADC1_IN2_P"), 1879 SND_SOC_DAPM_INPUT("ADC1_IN2_N"), 1880 SND_SOC_DAPM_INPUT("ADC2_IN_P"), 1881 SND_SOC_DAPM_INPUT("ADC2_IN_N"), 1882 1883 SND_SOC_DAPM_INPUT("PDM1_DIN"), 1884 SND_SOC_DAPM_INPUT("PDM2_DIN"), 1885 1886 SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl), 1887 1888 SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0, 1889 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1890 SND_SOC_DAPM_PRE_PMD), 1891 SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0, 1892 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1893 SND_SOC_DAPM_PRE_PMD), 1894 1895 SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT, 1896 0, NULL, 0, cs42l43_mic_ev, 1897 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1898 SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT, 1899 0, NULL, 0, cs42l43_mic_ev, 1900 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1901 SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT, 1902 0, NULL, 0, cs42l43_mic_ev, 1903 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1904 SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT, 1905 0, NULL, 0, cs42l43_mic_ev, 1906 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1907 1908 SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0), 1909 SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0), 1910 SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0), 1911 SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0), 1912 1913 SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT, 1914 0, NULL, 0), 1915 SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT, 1916 0, NULL, 0), 1917 1918 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, 1919 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0), 1920 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, 1921 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0), 1922 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, 1923 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0), 1924 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, 1925 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0), 1926 SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, 1927 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0), 1928 SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, 1929 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0), 1930 1931 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, 1932 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0), 1933 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1, 1934 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0), 1935 SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2, 1936 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0), 1937 SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3, 1938 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0), 1939 SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4, 1940 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0), 1941 SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5, 1942 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0), 1943 1944 SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1945 SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1946 SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0), 1947 SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0), 1948 1949 SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1950 SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1951 1952 SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1953 SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1954 1955 SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1956 SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1957 1958 SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1959 SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1960 1961 SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1962 SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1963 1964 SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1965 SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1966 1967 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0), 1968 1969 SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0, 1970 cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1971 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1972 SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0, 1973 cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1974 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1975 1976 SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"), 1977 SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"), 1978 SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"), 1979 SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"), 1980 1981 SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT, 1982 0, NULL, 0), 1983 SND_SOC_DAPM_OUTPUT("SPDIF_TX"), 1984 1985 SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0, 1986 cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1987 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1988 SND_SOC_DAPM_OUTPUT("AMP3_OUT"), 1989 SND_SOC_DAPM_OUTPUT("AMP4_OUT"), 1990 1991 SND_SOC_DAPM_SIGGEN("Tone"), 1992 SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT, 1993 0, NULL, 0), 1994 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL, 1995 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0), 1996 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL, 1997 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0), 1998 1999 SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT, 2000 0, NULL, 0), 2001 SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT, 2002 0, NULL, 0), 2003 2004 SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL, 2005 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0), 2006 SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL, 2007 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0), 2008 SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL, 2009 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0), 2010 SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL, 2011 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0), 2012 2013 SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL, 2014 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0), 2015 SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL, 2016 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0), 2017 SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL, 2018 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0), 2019 SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL, 2020 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0), 2021 2022 SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4, 2023 CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0), 2024 SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4, 2025 CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0), 2026 2027 SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES, 2028 CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0), 2029 SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES, 2030 CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0), 2031 SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES, 2032 CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0), 2033 SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES, 2034 CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0), 2035 SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES, 2036 CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0), 2037 SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES, 2038 CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0), 2039 SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES, 2040 CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0), 2041 SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES, 2042 CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0), 2043 2044 SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT, 2045 0, NULL, 0), 2046 SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT, 2047 0, NULL, 0, cs42l43_eq_ev, 2048 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 2049 2050 SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT, 2051 0, NULL, 0), 2052 }; 2053 2054 static const struct snd_soc_dapm_route cs42l43_routes[] = { 2055 { "ADC1_IN1_P", NULL, "PLL" }, 2056 { "ADC1_IN1_N", NULL, "PLL" }, 2057 { "ADC1_IN2_P", NULL, "PLL" }, 2058 { "ADC1_IN2_N", NULL, "PLL" }, 2059 { "ADC2_IN_P", NULL, "PLL" }, 2060 { "ADC2_IN_N", NULL, "PLL" }, 2061 { "PDM1_DIN", NULL, "PLL" }, 2062 { "PDM2_DIN", NULL, "PLL" }, 2063 { "AMP1_OUT_P", NULL, "PLL" }, 2064 { "AMP1_OUT_N", NULL, "PLL" }, 2065 { "AMP2_OUT_P", NULL, "PLL" }, 2066 { "AMP2_OUT_N", NULL, "PLL" }, 2067 { "SPDIF_TX", NULL, "PLL" }, 2068 { "HP", NULL, "PLL" }, 2069 { "AMP3_OUT", NULL, "PLL" }, 2070 { "AMP4_OUT", NULL, "PLL" }, 2071 { "Tone 1", NULL, "PLL" }, 2072 { "Tone 2", NULL, "PLL" }, 2073 { "ASP Playback", NULL, "PLL" }, 2074 { "ASP Capture", NULL, "PLL" }, 2075 { "DP1 Capture", NULL, "PLL" }, 2076 { "DP2 Capture", NULL, "PLL" }, 2077 { "DP3 Capture", NULL, "PLL" }, 2078 { "DP4 Capture", NULL, "PLL" }, 2079 { "DP5 Playback", NULL, "PLL" }, 2080 { "DP6 Playback", NULL, "PLL" }, 2081 { "DP7 Playback", NULL, "PLL" }, 2082 2083 { "ADC1 Input", "IN1", "ADC1_IN1_P" }, 2084 { "ADC1 Input", "IN1", "ADC1_IN1_N" }, 2085 { "ADC1 Input", "IN2", "ADC1_IN2_P" }, 2086 { "ADC1 Input", "IN2", "ADC1_IN2_N" }, 2087 2088 { "ADC1", NULL, "ADC1 Input" }, 2089 { "ADC2", NULL, "ADC2_IN_P" }, 2090 { "ADC2", NULL, "ADC2_IN_N" }, 2091 2092 { "PDM1L", NULL, "PDM1_DIN" }, 2093 { "PDM1R", NULL, "PDM1_DIN" }, 2094 { "PDM2L", NULL, "PDM2_DIN" }, 2095 { "PDM2R", NULL, "PDM2_DIN" }, 2096 2097 { "ASP Capture", NULL, "ASPTX1" }, 2098 { "ASP Capture", NULL, "ASPTX2" }, 2099 { "ASP Capture", NULL, "ASPTX3" }, 2100 { "ASP Capture", NULL, "ASPTX4" }, 2101 { "ASP Capture", NULL, "ASPTX5" }, 2102 { "ASP Capture", NULL, "ASPTX6" }, 2103 { "ASPTX1", NULL, "BCLK" }, 2104 { "ASPTX2", NULL, "BCLK" }, 2105 { "ASPTX3", NULL, "BCLK" }, 2106 { "ASPTX4", NULL, "BCLK" }, 2107 { "ASPTX5", NULL, "BCLK" }, 2108 { "ASPTX6", NULL, "BCLK" }, 2109 2110 { "ASPRX1", NULL, "ASP Playback" }, 2111 { "ASPRX2", NULL, "ASP Playback" }, 2112 { "ASPRX3", NULL, "ASP Playback" }, 2113 { "ASPRX4", NULL, "ASP Playback" }, 2114 { "ASPRX5", NULL, "ASP Playback" }, 2115 { "ASPRX6", NULL, "ASP Playback" }, 2116 { "ASPRX1", NULL, "BCLK" }, 2117 { "ASPRX2", NULL, "BCLK" }, 2118 { "ASPRX3", NULL, "BCLK" }, 2119 { "ASPRX4", NULL, "BCLK" }, 2120 { "ASPRX5", NULL, "BCLK" }, 2121 { "ASPRX6", NULL, "BCLK" }, 2122 2123 { "DP1 Capture", NULL, "DP1TX1" }, 2124 { "DP1 Capture", NULL, "DP1TX2" }, 2125 { "DP1 Capture", NULL, "DP1TX3" }, 2126 { "DP1 Capture", NULL, "DP1TX4" }, 2127 2128 { "DP2 Capture", NULL, "DP2TX1" }, 2129 { "DP2 Capture", NULL, "DP2TX2" }, 2130 2131 { "DP3 Capture", NULL, "DP3TX1" }, 2132 { "DP3 Capture", NULL, "DP3TX2" }, 2133 2134 { "DP4 Capture", NULL, "DP4TX1" }, 2135 { "DP4 Capture", NULL, "DP4TX2" }, 2136 2137 { "DP5RX1", NULL, "DP5 Playback" }, 2138 { "DP5RX2", NULL, "DP5 Playback" }, 2139 2140 { "DP6RX1", NULL, "DP6 Playback" }, 2141 { "DP6RX2", NULL, "DP6 Playback" }, 2142 2143 { "DP7RX1", NULL, "DP7 Playback" }, 2144 { "DP7RX2", NULL, "DP7 Playback" }, 2145 2146 { "AMP1", NULL, "vdd-amp" }, 2147 { "AMP2", NULL, "vdd-amp" }, 2148 2149 { "AMP1_OUT_P", NULL, "AMP1" }, 2150 { "AMP1_OUT_N", NULL, "AMP1" }, 2151 { "AMP2_OUT_P", NULL, "AMP2" }, 2152 { "AMP2_OUT_N", NULL, "AMP2" }, 2153 2154 { "SPDIF_TX", NULL, "SPDIF" }, 2155 2156 { "AMP3_OUT", NULL, "HP" }, 2157 { "AMP4_OUT", NULL, "HP" }, 2158 2159 { "Tone 1", NULL, "Tone" }, 2160 { "Tone 1", NULL, "Tone Generator" }, 2161 { "Tone 2", NULL, "Tone" }, 2162 { "Tone 2", NULL, "Tone Generator" }, 2163 2164 { "ISRC1INT2", NULL, "ISRC1" }, 2165 { "ISRC1INT1", NULL, "ISRC1" }, 2166 { "ISRC1DEC2", NULL, "ISRC1" }, 2167 { "ISRC1DEC1", NULL, "ISRC1" }, 2168 2169 { "ISRC2INT2", NULL, "ISRC2" }, 2170 { "ISRC2INT1", NULL, "ISRC2" }, 2171 { "ISRC2DEC2", NULL, "ISRC2" }, 2172 { "ISRC2DEC1", NULL, "ISRC2" }, 2173 2174 { "ASRC_INT1", NULL, "ASRC_INT" }, 2175 { "ASRC_INT2", NULL, "ASRC_INT" }, 2176 { "ASRC_INT3", NULL, "ASRC_INT" }, 2177 { "ASRC_INT4", NULL, "ASRC_INT" }, 2178 { "ASRC_DEC1", NULL, "ASRC_DEC" }, 2179 { "ASRC_DEC2", NULL, "ASRC_DEC" }, 2180 { "ASRC_DEC3", NULL, "ASRC_DEC" }, 2181 { "ASRC_DEC4", NULL, "ASRC_DEC" }, 2182 2183 { "EQ", NULL, "EQ Clock" }, 2184 }; 2185 2186 static const struct snd_kcontrol_new cs42l43_a_controls[] = { 2187 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up, 2188 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2189 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down, 2190 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2191 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up, 2192 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2193 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down, 2194 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2195 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up, 2196 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2197 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down, 2198 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2199 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up, 2200 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2201 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down, 2202 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2203 2204 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 2205 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2206 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 2207 CS42L43_DECIM1_MUTE_SHIFT, 1, 1, 2208 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2209 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 2210 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2211 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 2212 CS42L43_DECIM2_MUTE_SHIFT, 1, 1, 2213 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2214 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 2215 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2216 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 2217 CS42L43_DECIM3_MUTE_SHIFT, 1, 1, 2218 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2219 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 2220 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2221 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 2222 CS42L43_DECIM4_MUTE_SHIFT, 1, 1, 2223 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2224 }; 2225 2226 static const struct snd_kcontrol_new cs42l43_b_controls[] = { 2227 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 2228 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2229 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 2230 CS42L43_DECIM1_MUTE_SHIFT, 1, 1, 2231 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2232 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 2233 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2234 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 2235 CS42L43_DECIM2_MUTE_SHIFT, 1, 1, 2236 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2237 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 2238 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2239 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 2240 CS42L43_DECIM3_MUTE_SHIFT, 1, 1, 2241 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2242 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 2243 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2244 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 2245 CS42L43_DECIM4_MUTE_SHIFT, 1, 1, 2246 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2247 SOC_SINGLE_TLV("Decimator 5 Volume", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 2248 CS42L43B_DECIM5_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2249 SOC_SINGLE_EXT("Decimator 5 Switch", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 2250 CS42L43B_DECIM5_MUTE_SHIFT, 1, 1, 2251 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2252 SOC_SINGLE_TLV("Decimator 6 Volume", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 2253 CS42L43B_DECIM6_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2254 SOC_SINGLE_EXT("Decimator 6 Switch", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 2255 CS42L43B_DECIM6_MUTE_SHIFT, 1, 1, 2256 cs42l43_decim_get, cs42l43_dapm_put_volsw), 2257 2258 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43b_dec1_ramp_up, 2259 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2260 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43b_dec1_ramp_down, 2261 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2262 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43b_dec2_ramp_up, 2263 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2264 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43b_dec2_ramp_down, 2265 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2266 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43b_dec3_ramp_up, 2267 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2268 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43b_dec3_ramp_down, 2269 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2270 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43b_dec4_ramp_up, 2271 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2272 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43b_dec4_ramp_down, 2273 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2274 SOC_ENUM_EXT("Decimator 5 Ramp Up", cs42l43b_dec5_ramp_up, 2275 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2276 SOC_ENUM_EXT("Decimator 5 Ramp Down", cs42l43b_dec5_ramp_down, 2277 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2278 SOC_ENUM_EXT("Decimator 6 Ramp Up", cs42l43b_dec6_ramp_up, 2279 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2280 SOC_ENUM_EXT("Decimator 6 Ramp Down", cs42l43b_dec6_ramp_down, 2281 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2282 2283 SOC_SINGLE("Decimator 5 WNF Switch", CS42L43B_DECIM_HPF_WNF_CTRL5, 2284 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 2285 SOC_SINGLE("Decimator 6 WNF Switch", CS42L43B_DECIM_HPF_WNF_CTRL6, 2286 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 2287 2288 SOC_ENUM("Decimator 5 WNF Corner Frequency", cs42l43b_dec5_wnf_corner), 2289 SOC_ENUM("Decimator 6 WNF Corner Frequency", cs42l43b_dec6_wnf_corner), 2290 2291 SOC_SINGLE("Decimator 5 HPF Switch", CS42L43B_DECIM_HPF_WNF_CTRL5, 2292 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 2293 SOC_SINGLE("Decimator 6 HPF Switch", CS42L43B_DECIM_HPF_WNF_CTRL6, 2294 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 2295 2296 SOC_ENUM("Decimator 5 HPF Corner Frequency", cs42l43b_dec5_hpf_corner), 2297 SOC_ENUM("Decimator 6 HPF Corner Frequency", cs42l43b_dec6_hpf_corner), 2298 }; 2299 2300 static const struct snd_soc_dapm_widget cs42l43_a_widgets[] = { 2301 SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0, 2302 &cs42l43_dec_mode_ctl[0]), 2303 SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0, 2304 &cs42l43_dec_mode_ctl[1]), 2305 CS42L43_DAPM_MUX("ASPTX1", asptx1), 2306 CS42L43_DAPM_MUX("ASPTX2", asptx2), 2307 CS42L43_DAPM_MUX("ASPTX3", asptx3), 2308 CS42L43_DAPM_MUX("ASPTX4", asptx4), 2309 CS42L43_DAPM_MUX("ASPTX5", asptx5), 2310 CS42L43_DAPM_MUX("ASPTX6", asptx6), 2311 2312 CS42L43_DAPM_MUX("DP1TX1", dp1tx1), 2313 CS42L43_DAPM_MUX("DP1TX2", dp1tx2), 2314 CS42L43_DAPM_MUX("DP1TX3", dp1tx3), 2315 CS42L43_DAPM_MUX("DP1TX4", dp1tx4), 2316 CS42L43_DAPM_MUX("DP2TX1", dp2tx1), 2317 CS42L43_DAPM_MUX("DP2TX2", dp2tx2), 2318 CS42L43_DAPM_MUX("DP3TX1", dp3tx1), 2319 CS42L43_DAPM_MUX("DP3TX2", dp3tx2), 2320 CS42L43_DAPM_MUX("DP4TX1", dp4tx1), 2321 CS42L43_DAPM_MUX("DP4TX2", dp4tx2), 2322 2323 CS42L43_DAPM_MUX("ASRC INT1", asrcint1), 2324 CS42L43_DAPM_MUX("ASRC INT2", asrcint2), 2325 CS42L43_DAPM_MUX("ASRC INT3", asrcint3), 2326 CS42L43_DAPM_MUX("ASRC INT4", asrcint4), 2327 CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1), 2328 CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2), 2329 CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3), 2330 CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4), 2331 2332 CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1), 2333 CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2), 2334 CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1), 2335 CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2), 2336 CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1), 2337 CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2), 2338 CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1), 2339 CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2), 2340 2341 CS42L43_DAPM_MUX("SPDIF1", spdif1), 2342 CS42L43_DAPM_MUX("SPDIF2", spdif2), 2343 2344 CS42L43_DAPM_MIXER("EQ1", eq1), 2345 CS42L43_DAPM_MIXER("EQ2", eq2), 2346 2347 CS42L43_DAPM_MIXER("Speaker L", amp1), 2348 CS42L43_DAPM_MIXER("Speaker R", amp2), 2349 2350 CS42L43_DAPM_MIXER("Headphone L", amp3), 2351 CS42L43_DAPM_MIXER("Headphone R", amp4), 2352 }; 2353 2354 static const struct snd_soc_dapm_widget cs42l43_b_widgets[] = { 2355 SND_SOC_DAPM_AIF_OUT("DP3TX3", NULL, 2, SND_SOC_NOPM, 0, 0), 2356 SND_SOC_DAPM_AIF_OUT("DP3TX4", NULL, 3, SND_SOC_NOPM, 0, 0), 2357 SND_SOC_DAPM_AIF_OUT("DP4TX3", NULL, 2, SND_SOC_NOPM, 0, 0), 2358 SND_SOC_DAPM_AIF_OUT("DP4TX4", NULL, 3, SND_SOC_NOPM, 0, 0), 2359 2360 SND_SOC_DAPM_PGA("Decimator 5", SND_SOC_NOPM, 0, 0, NULL, 0), 2361 SND_SOC_DAPM_PGA("Decimator 6", SND_SOC_NOPM, 0, 0, NULL, 0), 2362 2363 SND_SOC_DAPM_PGA("ISRC1DEC3", CS42L43_ISRC1_CTRL, 2364 CS42L43B_ISRC_DEC3_EN_SHIFT, 0, NULL, 0), 2365 SND_SOC_DAPM_PGA("ISRC1DEC4", CS42L43_ISRC1_CTRL, 2366 CS42L43B_ISRC_DEC4_EN_SHIFT, 0, NULL, 0), 2367 SND_SOC_DAPM_PGA("ISRC2DEC3", CS42L43_ISRC2_CTRL, 2368 CS42L43B_ISRC_DEC3_EN_SHIFT, 0, NULL, 0), 2369 SND_SOC_DAPM_PGA("ISRC2DEC4", CS42L43_ISRC2_CTRL, 2370 CS42L43B_ISRC_DEC4_EN_SHIFT, 0, NULL, 0), 2371 2372 CS42L43_DAPM_MUX("ASPTX1", b_asptx1), 2373 CS42L43_DAPM_MUX("ASPTX2", b_asptx2), 2374 CS42L43_DAPM_MUX("ASPTX3", b_asptx3), 2375 CS42L43_DAPM_MUX("ASPTX4", b_asptx4), 2376 CS42L43_DAPM_MUX("ASPTX5", b_asptx5), 2377 CS42L43_DAPM_MUX("ASPTX6", b_asptx6), 2378 2379 CS42L43_DAPM_MUX("DP1TX1", b_dp1tx1), 2380 CS42L43_DAPM_MUX("DP1TX2", b_dp1tx2), 2381 CS42L43_DAPM_MUX("DP1TX3", b_dp1tx3), 2382 CS42L43_DAPM_MUX("DP1TX4", b_dp1tx4), 2383 CS42L43_DAPM_MUX("DP2TX1", b_dp2tx1), 2384 CS42L43_DAPM_MUX("DP2TX2", b_dp2tx2), 2385 CS42L43_DAPM_MUX("DP3TX1", b_dp3tx1), 2386 CS42L43_DAPM_MUX("DP3TX2", b_dp3tx2), 2387 CS42L43_DAPM_MUX("DP3TX3", b_dp3tx3), 2388 CS42L43_DAPM_MUX("DP3TX4", b_dp3tx4), 2389 CS42L43_DAPM_MUX("DP4TX1", b_dp4tx1), 2390 CS42L43_DAPM_MUX("DP4TX2", b_dp4tx2), 2391 CS42L43_DAPM_MUX("DP4TX3", b_dp4tx3), 2392 CS42L43_DAPM_MUX("DP4TX4", b_dp4tx4), 2393 2394 CS42L43_DAPM_MUX("ASRC INT1", b_asrcint1), 2395 CS42L43_DAPM_MUX("ASRC INT2", b_asrcint2), 2396 CS42L43_DAPM_MUX("ASRC INT3", b_asrcint3), 2397 CS42L43_DAPM_MUX("ASRC INT4", b_asrcint4), 2398 CS42L43_DAPM_MUX("ASRC DEC1", b_asrcdec1), 2399 CS42L43_DAPM_MUX("ASRC DEC2", b_asrcdec2), 2400 CS42L43_DAPM_MUX("ASRC DEC3", b_asrcdec3), 2401 CS42L43_DAPM_MUX("ASRC DEC4", b_asrcdec4), 2402 2403 CS42L43_DAPM_MUX("ISRC1INT1", b_isrc1int1), 2404 CS42L43_DAPM_MUX("ISRC1INT2", b_isrc1int2), 2405 CS42L43_DAPM_MUX("ISRC1DEC1", b_isrc1dec1), 2406 CS42L43_DAPM_MUX("ISRC1DEC2", b_isrc1dec2), 2407 CS42L43_DAPM_MUX("ISRC1DEC3", b_isrc1dec3), 2408 CS42L43_DAPM_MUX("ISRC1DEC4", b_isrc1dec4), 2409 CS42L43_DAPM_MUX("ISRC2INT1", b_isrc2int1), 2410 CS42L43_DAPM_MUX("ISRC2INT2", b_isrc2int2), 2411 CS42L43_DAPM_MUX("ISRC2DEC1", b_isrc2dec1), 2412 CS42L43_DAPM_MUX("ISRC2DEC2", b_isrc2dec2), 2413 CS42L43_DAPM_MUX("ISRC2DEC3", b_isrc2dec3), 2414 CS42L43_DAPM_MUX("ISRC2DEC4", b_isrc2dec4), 2415 2416 CS42L43_DAPM_MUX("SPDIF1", b_spdif1), 2417 CS42L43_DAPM_MUX("SPDIF2", b_spdif2), 2418 2419 CS42L43_DAPM_MIXER("EQ1", b_eq1), 2420 CS42L43_DAPM_MIXER("EQ2", b_eq2), 2421 2422 CS42L43_DAPM_MIXER("Speaker L", b_amp1), 2423 CS42L43_DAPM_MIXER("Speaker R", b_amp2), 2424 2425 CS42L43_DAPM_MIXER("Headphone L", b_amp3), 2426 CS42L43_DAPM_MIXER("Headphone R", b_amp4), 2427 }; 2428 2429 static const struct snd_soc_dapm_route cs42l43_a_routes[] = { 2430 { "Decimator 1 Mode", "PDM", "PDM1L" }, 2431 { "Decimator 1 Mode", "ADC", "ADC1" }, 2432 { "Decimator 2 Mode", "PDM", "PDM1R" }, 2433 { "Decimator 2 Mode", "ADC", "ADC2" }, 2434 2435 { "Decimator 1", NULL, "Decimator 1 Mode" }, 2436 { "Decimator 2", NULL, "Decimator 2 Mode" }, 2437 { "Decimator 3", NULL, "PDM2L" }, 2438 { "Decimator 4", NULL, "PDM2R" }, 2439 2440 CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"), 2441 CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"), 2442 CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"), 2443 CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"), 2444 CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"), 2445 CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"), 2446 2447 CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"), 2448 CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"), 2449 CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"), 2450 CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"), 2451 CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"), 2452 CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"), 2453 CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"), 2454 CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"), 2455 CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"), 2456 CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"), 2457 2458 CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"), 2459 CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"), 2460 CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"), 2461 CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"), 2462 CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"), 2463 CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"), 2464 CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"), 2465 CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"), 2466 2467 CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), 2468 CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), 2469 CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), 2470 CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), 2471 CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), 2472 CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), 2473 CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), 2474 CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), 2475 2476 CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"), 2477 CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"), 2478 2479 CS42L43_MIXER_ROUTES("EQ1", "EQ"), 2480 CS42L43_MIXER_ROUTES("EQ2", "EQ"), 2481 2482 CS42L43_MIXER_ROUTES("Speaker L", "AMP1"), 2483 CS42L43_MIXER_ROUTES("Speaker R", "AMP2"), 2484 2485 CS42L43_MIXER_ROUTES("Headphone L", "HP"), 2486 CS42L43_MIXER_ROUTES("Headphone R", "HP"), 2487 }; 2488 2489 static const struct snd_soc_dapm_route cs42l43_b_routes[] = { 2490 { "Decimator 1", NULL, "ADC1" }, 2491 { "Decimator 2", NULL, "ADC2" }, 2492 { "Decimator 3", NULL, "PDM1L" }, 2493 { "Decimator 4", NULL, "PDM1R" }, 2494 { "Decimator 5", NULL, "PDM2L" }, 2495 { "Decimator 6", NULL, "PDM2R" }, 2496 2497 { "DP3 Capture", NULL, "DP3TX3" }, 2498 { "DP3 Capture", NULL, "DP3TX4" }, 2499 { "DP4 Capture", NULL, "DP4TX3" }, 2500 { "DP4 Capture", NULL, "DP4TX4" }, 2501 2502 { "ISRC1DEC3", NULL, "ISRC1" }, 2503 { "ISRC1DEC4", NULL, "ISRC1" }, 2504 { "ISRC2DEC3", NULL, "ISRC2" }, 2505 { "ISRC2DEC4", NULL, "ISRC2" }, 2506 2507 CS42L43B_MUX_ROUTES("ASPTX1", "ASPTX1"), 2508 CS42L43B_MUX_ROUTES("ASPTX2", "ASPTX2"), 2509 CS42L43B_MUX_ROUTES("ASPTX3", "ASPTX3"), 2510 CS42L43B_MUX_ROUTES("ASPTX4", "ASPTX4"), 2511 CS42L43B_MUX_ROUTES("ASPTX5", "ASPTX5"), 2512 CS42L43B_MUX_ROUTES("ASPTX6", "ASPTX6"), 2513 2514 CS42L43B_MUX_ROUTES("DP1TX1", "DP1TX1"), 2515 CS42L43B_MUX_ROUTES("DP1TX2", "DP1TX2"), 2516 CS42L43B_MUX_ROUTES("DP1TX3", "DP1TX3"), 2517 CS42L43B_MUX_ROUTES("DP1TX4", "DP1TX4"), 2518 CS42L43B_MUX_ROUTES("DP2TX1", "DP2TX1"), 2519 CS42L43B_MUX_ROUTES("DP2TX2", "DP2TX2"), 2520 CS42L43B_MUX_ROUTES("DP3TX1", "DP3TX1"), 2521 CS42L43B_MUX_ROUTES("DP3TX2", "DP3TX2"), 2522 CS42L43B_MUX_ROUTES("DP3TX3", "DP3TX3"), 2523 CS42L43B_MUX_ROUTES("DP3TX4", "DP3TX4"), 2524 CS42L43B_MUX_ROUTES("DP4TX1", "DP4TX1"), 2525 CS42L43B_MUX_ROUTES("DP4TX2", "DP4TX2"), 2526 CS42L43B_MUX_ROUTES("DP4TX3", "DP4TX3"), 2527 CS42L43B_MUX_ROUTES("DP4TX4", "DP4TX4"), 2528 2529 CS42L43B_MUX_ROUTES("ASRC INT1", "ASRC_INT1"), 2530 CS42L43B_MUX_ROUTES("ASRC INT2", "ASRC_INT2"), 2531 CS42L43B_MUX_ROUTES("ASRC INT3", "ASRC_INT3"), 2532 CS42L43B_MUX_ROUTES("ASRC INT4", "ASRC_INT4"), 2533 CS42L43B_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"), 2534 CS42L43B_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"), 2535 CS42L43B_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"), 2536 CS42L43B_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"), 2537 2538 CS42L43B_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), 2539 CS42L43B_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), 2540 CS42L43B_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), 2541 CS42L43B_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), 2542 CS42L43B_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), 2543 CS42L43B_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), 2544 CS42L43B_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), 2545 CS42L43B_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), 2546 CS42L43B_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), 2547 CS42L43B_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), 2548 CS42L43B_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"), 2549 CS42L43B_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"), 2550 2551 CS42L43B_MUX_ROUTES("SPDIF1", "SPDIF"), 2552 CS42L43B_MUX_ROUTES("SPDIF2", "SPDIF"), 2553 2554 CS42L43B_MIXER_ROUTES("EQ1", "EQ"), 2555 CS42L43B_MIXER_ROUTES("EQ2", "EQ"), 2556 2557 CS42L43B_MIXER_ROUTES("Speaker L", "AMP1"), 2558 CS42L43B_MIXER_ROUTES("Speaker R", "AMP2"), 2559 2560 CS42L43B_MIXER_ROUTES("Headphone L", "HP"), 2561 CS42L43B_MIXER_ROUTES("Headphone R", "HP"), 2562 }; 2563 2564 static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id, 2565 int src, unsigned int freq, int dir) 2566 { 2567 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 2568 struct cs42l43 *cs42l43 = priv->core; 2569 int ret; 2570 2571 mutex_lock(&cs42l43->pll_lock); 2572 ret = cs42l43_set_pll(priv, src, freq); 2573 mutex_unlock(&cs42l43->pll_lock); 2574 2575 return ret; 2576 } 2577 2578 static int cs42l43_component_probe(struct snd_soc_component *component) 2579 { 2580 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2581 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 2582 unsigned int num_controls, num_widgets, num_routes; 2583 const struct snd_soc_dapm_widget *widgets; 2584 const struct snd_kcontrol_new *controls; 2585 const struct snd_soc_dapm_route *routes; 2586 struct cs42l43 *cs42l43 = priv->core; 2587 int ret; 2588 2589 snd_soc_component_init_regmap(component, cs42l43->regmap); 2590 2591 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots, 2592 ARRAY_SIZE(priv->tx_slots)); 2593 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots, 2594 ARRAY_SIZE(priv->rx_slots)); 2595 2596 priv->component = component; 2597 priv->constraint = cs42l43_constraint; 2598 2599 switch (cs42l43->variant_id) { 2600 case CS42L43_DEVID_VAL: 2601 controls = cs42l43_a_controls; 2602 num_controls = ARRAY_SIZE(cs42l43_a_controls); 2603 widgets = cs42l43_a_widgets; 2604 num_widgets = ARRAY_SIZE(cs42l43_a_widgets); 2605 routes = cs42l43_a_routes; 2606 num_routes = ARRAY_SIZE(cs42l43_a_routes); 2607 break; 2608 case CS42L43B_DEVID_VAL: 2609 controls = cs42l43_b_controls; 2610 num_controls = ARRAY_SIZE(cs42l43_b_controls); 2611 widgets = cs42l43_b_widgets; 2612 num_widgets = ARRAY_SIZE(cs42l43_b_widgets); 2613 routes = cs42l43_b_routes; 2614 num_routes = ARRAY_SIZE(cs42l43_b_routes); 2615 break; 2616 default: 2617 return -EINVAL; 2618 } 2619 2620 ret = snd_soc_add_component_controls(component, controls, num_controls); 2621 if (ret) 2622 return ret; 2623 2624 ret = snd_soc_dapm_new_controls(dapm, widgets, num_widgets); 2625 if (ret) 2626 return ret; 2627 2628 ret = snd_soc_dapm_add_routes(dapm, routes, num_routes); 2629 if (ret) 2630 return ret; 2631 2632 return 0; 2633 } 2634 2635 static void cs42l43_component_remove(struct snd_soc_component *component) 2636 { 2637 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 2638 2639 cs42l43_set_jack(priv->component, NULL, NULL); 2640 2641 cancel_delayed_work_sync(&priv->bias_sense_timeout); 2642 cancel_delayed_work_sync(&priv->tip_sense_work); 2643 2644 cancel_delayed_work_sync(&priv->hp_ilimit_clear_work); 2645 2646 priv->component = NULL; 2647 } 2648 2649 static const struct snd_soc_component_driver cs42l43_component_drv = { 2650 .name = "cs42l43-codec", 2651 2652 .probe = cs42l43_component_probe, 2653 .remove = cs42l43_component_remove, 2654 .set_sysclk = cs42l43_set_sysclk, 2655 .set_jack = cs42l43_set_jack, 2656 2657 .endianness = 1, 2658 2659 .controls = cs42l43_controls, 2660 .num_controls = ARRAY_SIZE(cs42l43_controls), 2661 .dapm_widgets = cs42l43_widgets, 2662 .num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets), 2663 .dapm_routes = cs42l43_routes, 2664 .num_dapm_routes = ARRAY_SIZE(cs42l43_routes), 2665 }; 2666 2667 struct cs42l43_irq { 2668 unsigned int irq; 2669 const char *name; 2670 irq_handler_t handler; 2671 }; 2672 2673 static const struct cs42l43_irq cs42l43_irqs[] = { 2674 { CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock }, 2675 { CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready }, 2676 { CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup }, 2677 { CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown }, 2678 { CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect }, 2679 { CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense }, 2680 { CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense }, 2681 { CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press }, 2682 { CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release }, 2683 { CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp }, 2684 { CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop }, 2685 { CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop }, 2686 { CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out }, 2687 { CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out }, 2688 { CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown }, 2689 { CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown }, 2690 { CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup }, 2691 { CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup }, 2692 { CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown }, 2693 { CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown }, 2694 { CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm }, 2695 { CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm }, 2696 { CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect }, 2697 { CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect }, 2698 { CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit }, 2699 { CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect }, 2700 }; 2701 2702 static int cs42l43_request_irq(struct cs42l43_codec *priv, 2703 const char * const name, unsigned int irq, 2704 irq_handler_t handler, unsigned long flags) 2705 { 2706 int ret; 2707 2708 ret = irq_create_mapping(priv->dom, irq); 2709 if (ret < 0) 2710 return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name); 2711 2712 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name); 2713 2714 ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler, 2715 IRQF_ONESHOT | flags, name, priv); 2716 if (ret) 2717 return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name); 2718 2719 return 0; 2720 } 2721 2722 static void cs42l43_disable_irq(struct cs42l43_codec *priv, unsigned int irq) 2723 { 2724 int ret; 2725 2726 ret = irq_find_mapping(priv->dom, irq); 2727 if (ret > 0) 2728 disable_irq(ret); 2729 } 2730 2731 static void cs42l43_enable_irq(struct cs42l43_codec *priv, unsigned int irq) 2732 { 2733 int ret; 2734 2735 ret = irq_find_mapping(priv->dom, irq); 2736 if (ret > 0) 2737 enable_irq(ret); 2738 } 2739 2740 static int cs42l43_shutter_irq(struct cs42l43_codec *priv, unsigned int shutter, 2741 const char * const open_name, unsigned int *open_irq, 2742 const char * const close_name, unsigned int *close_irq, 2743 irq_handler_t handler) 2744 { 2745 int ret; 2746 2747 switch (shutter) { 2748 case 0x1: 2749 dev_warn(priv->dev, "Manual shutters, notifications not available\n"); 2750 return 0; 2751 case 0x2: 2752 *open_irq = CS42L43_GPIO1_RISE; 2753 *close_irq = CS42L43_GPIO1_FALL; 2754 break; 2755 case 0x4: 2756 *open_irq = CS42L43_GPIO2_RISE; 2757 *close_irq = CS42L43_GPIO2_FALL; 2758 break; 2759 case 0x8: 2760 *open_irq = CS42L43_GPIO3_RISE; 2761 *close_irq = CS42L43_GPIO3_FALL; 2762 break; 2763 default: 2764 return 0; 2765 } 2766 2767 ret = cs42l43_request_irq(priv, close_name, *close_irq, handler, IRQF_SHARED); 2768 if (ret) 2769 return ret; 2770 2771 return cs42l43_request_irq(priv, open_name, *open_irq, handler, IRQF_SHARED); 2772 } 2773 2774 static int cs42l43_codec_probe(struct platform_device *pdev) 2775 { 2776 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent); 2777 struct cs42l43_codec *priv; 2778 unsigned int val; 2779 int i, ret; 2780 2781 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2782 if (!priv) 2783 return -ENOMEM; 2784 2785 priv->dev = &pdev->dev; 2786 priv->core = cs42l43; 2787 2788 priv->dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY); 2789 if (!priv->dom) 2790 return -EPROBE_DEFER; 2791 2792 platform_set_drvdata(pdev, priv); 2793 2794 mutex_init(&priv->jack_lock); 2795 mutex_init(&priv->spk_vu_lock); 2796 2797 init_completion(&priv->hp_startup); 2798 init_completion(&priv->hp_shutdown); 2799 init_completion(&priv->spkr_shutdown); 2800 init_completion(&priv->spkl_shutdown); 2801 init_completion(&priv->spkr_startup); 2802 init_completion(&priv->spkl_startup); 2803 init_completion(&priv->pll_ready); 2804 init_completion(&priv->type_detect); 2805 init_completion(&priv->load_detect); 2806 2807 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work); 2808 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout); 2809 INIT_DELAYED_WORK(&priv->hp_ilimit_clear_work, cs42l43_hp_ilimit_clear_work); 2810 2811 pm_runtime_set_autosuspend_delay(priv->dev, 100); 2812 pm_runtime_use_autosuspend(priv->dev); 2813 pm_runtime_set_active(priv->dev); 2814 pm_runtime_get_noresume(priv->dev); 2815 2816 ret = devm_pm_runtime_enable(priv->dev); 2817 if (ret) 2818 goto err_pm; 2819 2820 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) { 2821 ret = cs42l43_request_irq(priv, cs42l43_irqs[i].name, 2822 cs42l43_irqs[i].irq, 2823 cs42l43_irqs[i].handler, 0); 2824 if (ret) 2825 goto err_pm; 2826 } 2827 2828 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val); 2829 if (ret) { 2830 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret); 2831 goto err_pm; 2832 } 2833 2834 ret = cs42l43_shutter_irq(priv, val & CS42L43_MIC_SHUTTER_CFG_MASK, 2835 "mic shutter open", &priv->shutter_irqs[0], 2836 "mic shutter close", &priv->shutter_irqs[1], 2837 cs42l43_mic_shutter); 2838 if (ret) 2839 goto err_pm; 2840 2841 ret = cs42l43_shutter_irq(priv, (val & CS42L43_SPK_SHUTTER_CFG_MASK) >> 2842 CS42L43_SPK_SHUTTER_CFG_SHIFT, 2843 "spk shutter open", &priv->shutter_irqs[2], 2844 "spk shutter close", &priv->shutter_irqs[3], 2845 cs42l43_spk_shutter); 2846 if (ret) 2847 goto err_pm; 2848 2849 // Don't use devm as we need to get against the MFD device 2850 priv->mclk = clk_get_optional(cs42l43->dev, "mclk"); 2851 if (IS_ERR(priv->mclk)) { 2852 ret = PTR_ERR(priv->mclk); 2853 dev_err_probe(priv->dev, ret, "Failed to get mclk\n"); 2854 goto err_pm; 2855 } 2856 2857 ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv, 2858 cs42l43_dais, ARRAY_SIZE(cs42l43_dais)); 2859 if (ret) { 2860 dev_err_probe(priv->dev, ret, "Failed to register component\n"); 2861 goto err_clk; 2862 } 2863 2864 pm_runtime_put_autosuspend(priv->dev); 2865 2866 return 0; 2867 2868 err_clk: 2869 clk_put(priv->mclk); 2870 err_pm: 2871 pm_runtime_put_sync(priv->dev); 2872 2873 return ret; 2874 } 2875 2876 static void cs42l43_codec_remove(struct platform_device *pdev) 2877 { 2878 struct cs42l43_codec *priv = platform_get_drvdata(pdev); 2879 2880 clk_put(priv->mclk); 2881 } 2882 2883 static int cs42l43_codec_runtime_resume(struct device *dev) 2884 { 2885 struct cs42l43_codec *priv = dev_get_drvdata(dev); 2886 2887 dev_dbg(priv->dev, "Runtime resume\n"); 2888 2889 // Toggle the speaker volume update incase the speaker volume was synced 2890 cs42l43_spk_vu_sync(priv); 2891 2892 return 0; 2893 } 2894 2895 static int cs42l43_codec_suspend(struct device *dev) 2896 { 2897 struct cs42l43_codec *priv = dev_get_drvdata(dev); 2898 int i; 2899 2900 dev_dbg(priv->dev, "System suspend\n"); 2901 2902 priv->suspend_jack_debounce = true; 2903 2904 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) 2905 cs42l43_disable_irq(priv, cs42l43_irqs[i].irq); 2906 2907 for (i = 0; i < ARRAY_SIZE(priv->shutter_irqs); i++) 2908 if (priv->shutter_irqs[i]) 2909 cs42l43_disable_irq(priv, priv->shutter_irqs[i]); 2910 2911 cancel_delayed_work_sync(&priv->bias_sense_timeout); 2912 cancel_delayed_work_sync(&priv->tip_sense_work); 2913 cancel_delayed_work_sync(&priv->hp_ilimit_clear_work); 2914 2915 cs42l43_clear_jack(priv); 2916 2917 return pm_runtime_force_suspend(dev); 2918 } 2919 2920 static int cs42l43_codec_resume(struct device *dev) 2921 { 2922 struct cs42l43_codec *priv = dev_get_drvdata(dev); 2923 int ret, i; 2924 2925 ret = pm_runtime_force_resume(dev); 2926 if (ret) 2927 return ret; 2928 2929 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) 2930 cs42l43_enable_irq(priv, cs42l43_irqs[i].irq); 2931 2932 for (i = 0; i < ARRAY_SIZE(priv->shutter_irqs); i++) 2933 if (priv->shutter_irqs[i]) 2934 cs42l43_enable_irq(priv, priv->shutter_irqs[i]); 2935 2936 return 0; 2937 } 2938 2939 static const struct dev_pm_ops cs42l43_codec_pm_ops = { 2940 RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL) 2941 SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend, cs42l43_codec_resume) 2942 }; 2943 2944 static const struct platform_device_id cs42l43_codec_id_table[] = { 2945 { "cs42l43-codec", }, 2946 {} 2947 }; 2948 MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table); 2949 2950 static struct platform_driver cs42l43_codec_driver = { 2951 .driver = { 2952 .name = "cs42l43-codec", 2953 .pm = pm_ptr(&cs42l43_codec_pm_ops), 2954 }, 2955 2956 .probe = cs42l43_codec_probe, 2957 .remove = cs42l43_codec_remove, 2958 .id_table = cs42l43_codec_id_table, 2959 }; 2960 module_platform_driver(cs42l43_codec_driver); 2961 2962 MODULE_IMPORT_NS("SND_SOC_CS42L43"); 2963 2964 MODULE_DESCRIPTION("CS42L43 CODEC Driver"); 2965 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>"); 2966 MODULE_LICENSE("GPL"); 2967