1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ/G2L Clock Pulse Generator 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 */ 8 9 #ifndef __RENESAS_RZG2L_CPG_H__ 10 #define __RENESAS_RZG2L_CPG_H__ 11 12 #include <linux/notifier.h> 13 14 #define CPG_SIPLL5_STBY (0x140) 15 #define CPG_SIPLL5_CLK1 (0x144) 16 #define CPG_SIPLL5_CLK3 (0x14C) 17 #define CPG_SIPLL5_CLK4 (0x150) 18 #define CPG_SIPLL5_CLK5 (0x154) 19 #define CPG_SIPLL5_MON (0x15C) 20 #define CPG_PL1_DDIV (0x200) 21 #define CPG_PL2_DDIV (0x204) 22 #define CPG_PL3A_DDIV (0x208) 23 #define CPG_PL6_DDIV (0x210) 24 #define CPG_PL3C_SDIV (0x214) 25 #define CPG_CLKSTATUS (0x280) 26 #define CPG_PL3_SSEL (0x408) 27 #define CPG_PL6_SSEL (0x414) 28 #define CPG_PL6_ETH_SSEL (0x418) 29 #define CPG_PL5_SDIV (0x420) 30 #define CPG_RST_MON (0x680) 31 #define CPG_BUS_ACPU_MSTOP (0xB60) 32 #define CPG_BUS_MCPU1_MSTOP (0xB64) 33 #define CPG_BUS_MCPU2_MSTOP (0xB68) 34 #define CPG_BUS_PERI_COM_MSTOP (0xB6C) 35 #define CPG_BUS_PERI_CPU_MSTOP (0xB70) 36 #define CPG_BUS_PERI_DDR_MSTOP (0xB74) 37 #define CPG_BUS_REG0_MSTOP (0xB7C) 38 #define CPG_BUS_REG1_MSTOP (0xB80) 39 #define CPG_BUS_TZCDDR_MSTOP (0xB84) 40 #define CPG_MHU_MSTOP (0xB88) 41 #define CPG_BUS_MCPU3_MSTOP (0xB90) 42 #define CPG_BUS_PERI_CPU2_MSTOP (0xB94) 43 #define CPG_OTHERFUNC1_REG (0xBE8) 44 45 #define CPG_SIPLL5_STBY_RESETB BIT(0) 46 #define CPG_SIPLL5_STBY_RESETB_WEN BIT(16) 47 #define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18) 48 #define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20) 49 #define CPG_SIPLL5_CLK4_RESV_LSB (0xFF) 50 #define CPG_SIPLL5_MON_PLL5_LOCK BIT(4) 51 52 #define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16) 53 54 #define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16) 55 #define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24) 56 57 #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) 58 #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) 59 60 /* n = 0/1/2 for PLL1/4/6 */ 61 #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) 62 #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) 63 64 #define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) 65 66 #define DDIV_PACK(offset, bitpos, size) \ 67 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 68 #define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) 69 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) 70 #define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2) 71 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) 72 #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) 73 #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) 74 #define DIVPL3E DDIV_PACK(CPG_PL3C_SDIV, 8, 5) 75 #define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) 76 77 #define SEL_PLL_PACK(offset, bitpos, size) \ 78 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 79 80 #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) 81 #define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1) 82 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) 83 #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) 84 85 #define MSTOP(name, bitmask) ((CPG_##name##_MSTOP) << 16 | (bitmask)) 86 87 #define EXTAL_FREQ_IN_MEGA_HZ (24) 88 89 /** 90 * Definitions of CPG Core Clocks 91 * 92 * These include: 93 * - Clock outputs exported to DT 94 * - External input clocks 95 * - Internal CPG clocks 96 */ 97 struct cpg_core_clk { 98 const char *name; 99 unsigned int id; 100 unsigned int parent; 101 unsigned int div; 102 unsigned int mult; 103 unsigned int type; 104 unsigned int conf; 105 unsigned int sconf; 106 const struct clk_div_table *dtable; 107 const u32 *mtable; 108 const unsigned long invalid_rate; 109 union { 110 const unsigned long max_rate; 111 const unsigned long default_rate; 112 }; 113 const char * const *parent_names; 114 notifier_fn_t notifier; 115 u32 flag; 116 u32 mux_flags; 117 int num_parents; 118 }; 119 120 enum clk_types { 121 /* Generic */ 122 CLK_TYPE_IN, /* External Clock Input */ 123 CLK_TYPE_FF, /* Fixed Factor Clock */ 124 CLK_TYPE_SAM_PLL, 125 CLK_TYPE_G3S_PLL, 126 127 /* Clock with divider */ 128 CLK_TYPE_DIV, 129 CLK_TYPE_G3S_DIV, 130 131 /* Clock with clock source selector */ 132 CLK_TYPE_MUX, 133 134 /* Clock with SD clock source selector */ 135 CLK_TYPE_SD_MUX, 136 137 /* Clock for SIPLL5 */ 138 CLK_TYPE_SIPLL5, 139 140 /* Clock for PLL5_4 clock source selector */ 141 CLK_TYPE_PLL5_4_MUX, 142 143 /* Clock for DSI divider */ 144 CLK_TYPE_DSI_DIV, 145 146 }; 147 148 #define DEF_TYPE(_name, _id, _type...) \ 149 { .name = _name, .id = _id, .type = _type } 150 #define DEF_BASE(_name, _id, _type, _parent...) \ 151 DEF_TYPE(_name, _id, _type, .parent = _parent) 152 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ 153 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) 154 #define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \ 155 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \ 156 .default_rate = _default_rate) 157 #define DEF_INPUT(_name, _id) \ 158 DEF_TYPE(_name, _id, CLK_TYPE_IN) 159 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 160 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 161 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ 162 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 163 .parent = _parent, .dtable = _dtable, \ 164 .flag = CLK_DIVIDER_HIWORD_MASK) 165 #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ 166 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 167 .parent = _parent, .dtable = _dtable, \ 168 .flag = CLK_DIVIDER_READ_ONLY) 169 #define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \ 170 _max_rate, _clk_flags, _notif) \ 171 DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \ 172 .parent = _parent, .dtable = _dtable, \ 173 .invalid_rate = _invalid_rate, \ 174 .max_rate = _max_rate, .flag = (_clk_flags), \ 175 .notifier = _notif) 176 #define DEF_MUX(_name, _id, _conf, _parent_names) \ 177 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 178 .parent_names = _parent_names, \ 179 .num_parents = ARRAY_SIZE(_parent_names), \ 180 .mux_flags = CLK_MUX_HIWORD_MASK) 181 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ 182 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 183 .parent_names = _parent_names, \ 184 .num_parents = ARRAY_SIZE(_parent_names), \ 185 .mux_flags = CLK_MUX_READ_ONLY) 186 #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \ 187 DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \ 188 .parent_names = _parent_names, \ 189 .num_parents = ARRAY_SIZE(_parent_names), \ 190 .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier) 191 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ 192 DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) 193 #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ 194 DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ 195 .parent_names = _parent_names, \ 196 .num_parents = ARRAY_SIZE(_parent_names)) 197 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ 198 DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) 199 200 /** 201 * struct rzg2l_mod_clk - Module Clocks definitions 202 * 203 * @name: handle between common and hardware-specific interfaces 204 * @id: clock index in array containing all Core and Module Clocks 205 * @parent: id of parent clock 206 * @mstop_conf: MSTOP configuration 207 * @off: register offset 208 * @bit: ON/MON bit 209 * @is_coupled: flag to indicate coupled clock 210 */ 211 struct rzg2l_mod_clk { 212 const char *name; 213 unsigned int id; 214 unsigned int parent; 215 u32 mstop_conf; 216 u16 off; 217 u8 bit; 218 bool is_coupled; 219 }; 220 221 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \ 222 { \ 223 .name = _name, \ 224 .id = MOD_CLK_BASE + (_id), \ 225 .parent = (_parent), \ 226 .mstop_conf = (_mstop_conf), \ 227 .off = (_off), \ 228 .bit = (_bit), \ 229 .is_coupled = (_is_coupled), \ 230 } 231 232 #define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \ 233 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false) 234 235 #define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \ 236 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true) 237 238 /** 239 * struct rzg2l_reset - Reset definitions 240 * 241 * @off: register offset 242 * @bit: reset bit 243 * @monbit: monitor bit in CPG_RST_MON register, -1 if none 244 */ 245 struct rzg2l_reset { 246 u16 off; 247 u8 bit; 248 s8 monbit; 249 }; 250 251 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ 252 [_id] = { \ 253 .off = (_off), \ 254 .bit = (_bit), \ 255 .monbit = (_monbit) \ 256 } 257 #define DEF_RST(_id, _off, _bit) \ 258 DEF_RST_MON(_id, _off, _bit, -1) 259 260 /** 261 * struct rzg2l_cpg_info - SoC-specific CPG Description 262 * 263 * @core_clks: Array of Core Clock definitions 264 * @num_core_clks: Number of entries in core_clks[] 265 * @last_dt_core_clk: ID of the last Core Clock exported to DT 266 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 267 * 268 * @mod_clks: Array of Module Clock definitions 269 * @num_mod_clks: Number of entries in mod_clks[] 270 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 271 * 272 * @resets: Array of Module Reset definitions 273 * @num_resets: Number of entries in resets[] 274 * 275 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that 276 * should not be disabled without a knowledgeable driver 277 * @num_crit_mod_clks: Number of entries in crit_mod_clks[] 278 * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers 279 */ 280 struct rzg2l_cpg_info { 281 /* Core Clocks */ 282 const struct cpg_core_clk *core_clks; 283 unsigned int num_core_clks; 284 unsigned int last_dt_core_clk; 285 unsigned int num_total_core_clks; 286 287 /* Module Clocks */ 288 const struct rzg2l_mod_clk *mod_clks; 289 unsigned int num_mod_clks; 290 unsigned int num_hw_mod_clks; 291 292 /* No PM Module Clocks */ 293 const unsigned int *no_pm_mod_clks; 294 unsigned int num_no_pm_mod_clks; 295 296 /* Resets */ 297 const struct rzg2l_reset *resets; 298 unsigned int num_resets; 299 300 /* Critical Module Clocks that should not be disabled */ 301 const unsigned int *crit_mod_clks; 302 unsigned int num_crit_mod_clks; 303 304 bool has_clk_mon_regs; 305 }; 306 307 extern const struct rzg2l_cpg_info r9a07g043_cpg_info; 308 extern const struct rzg2l_cpg_info r9a07g044_cpg_info; 309 extern const struct rzg2l_cpg_info r9a07g054_cpg_info; 310 extern const struct rzg2l_cpg_info r9a08g045_cpg_info; 311 extern const struct rzg2l_cpg_info r9a09g011_cpg_info; 312 313 int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data); 314 int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); 315 316 #endif 317