xref: /qemu/include/hw/intc/loongson_ipi_common.h (revision d01d42ccc9510c039b2e4ec49af164e374eab154)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Loongson ipi interrupt header files
4  *
5  * Copyright (C) 2021 Loongson Technology Corporation Limited
6  */
7 
8 #ifndef HW_LOONGSON_IPI_COMMON_H
9 #define HW_LOONGSON_IPI_COMMON_H
10 
11 #include "qom/object.h"
12 #include "hw/sysbus.h"
13 #include "exec/memattrs.h"
14 
15 #define IPI_MBX_NUM           4
16 
17 #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
18 OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
19                     LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
20 
21 typedef struct IPICore {
22     LoongsonIPICommonState *ipi;
23     uint32_t status;
24     uint32_t en;
25     uint32_t set;
26     uint32_t clear;
27     /* 64bit buf divide into 2 32-bit buf */
28     uint32_t buf[IPI_MBX_NUM * 2];
29     qemu_irq irq;
30     uint64_t arch_id;
31     CPUState *cpu;
32 } IPICore;
33 
34 struct LoongsonIPICommonState {
35     SysBusDevice parent_obj;
36 
37     MemoryRegion ipi_iocsr_mem;
38     MemoryRegion ipi64_iocsr_mem;
39     uint32_t num_cpu;
40     IPICore *cpu;
41 };
42 
43 struct LoongsonIPICommonClass {
44     SysBusDeviceClass parent_class;
45 
46     DeviceRealize parent_realize;
47     DeviceUnrealize parent_unrealize;
48     AddressSpace *(*get_iocsr_as)(CPUState *cpu);
49     int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id,
50                           int *index, CPUState **pcs);
51     int (*pre_save)(void *opaque);
52     int (*post_load)(void *opaque, int version_id);
53 };
54 
55 MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
56                                     unsigned size, MemTxAttrs attrs);
57 MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
58                                      unsigned size, MemTxAttrs attrs);
59 
60 /* Mainy used by iocsr read and write */
61 #define SMP_IPI_MAILBOX         0x1000ULL
62 
63 #define CORE_STATUS_OFF         0x0
64 #define CORE_EN_OFF             0x4
65 #define CORE_SET_OFF            0x8
66 #define CORE_CLEAR_OFF          0xc
67 #define CORE_BUF_20             0x20
68 #define CORE_BUF_28             0x28
69 #define CORE_BUF_30             0x30
70 #define CORE_BUF_38             0x38
71 #define IOCSR_IPI_SEND          0x40
72 #define IOCSR_MAIL_SEND         0x48
73 #define IOCSR_ANY_SEND          0x158
74 
75 #define MAIL_SEND_ADDR          (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
76 #define MAIL_SEND_OFFSET        0
77 #define ANY_SEND_OFFSET         (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
78 
79 #endif
80