1# SPDX-License-Identifier: GPL-2.0-only
2config ARCH_HAS_RESET_CONTROLLER
3	bool
4
5menuconfig RESET_CONTROLLER
6	bool "Reset Controller Support"
7	default y if ARCH_HAS_RESET_CONTROLLER
8	help
9	  Generic Reset Controller support.
10
11	  This framework is designed to abstract reset handling of devices
12	  via GPIOs or SoC-internal reset controller modules.
13
14	  If unsure, say no.
15
16if RESET_CONTROLLER
17
18config RESET_A10SR
19	tristate "Altera Arria10 System Resource Reset"
20	depends on MFD_ALTERA_A10SR || COMPILE_TEST
21	help
22	  This option enables support for the external reset functions for
23	  peripheral PHYs on the Altera Arria10 System Resource Chip.
24
25config RESET_ATH79
26	bool "AR71xx Reset Driver" if COMPILE_TEST
27	default ATH79
28	help
29	  This enables the ATH79 reset controller driver that supports the
30	  AR71xx SoC reset controller.
31
32config RESET_AXS10X
33	bool "AXS10x Reset Driver" if COMPILE_TEST
34	default ARC_PLAT_AXS10X
35	help
36	  This enables the reset controller driver for AXS10x.
37
38config RESET_BCM6345
39	bool "BCM6345 Reset Controller"
40	depends on BMIPS_GENERIC || COMPILE_TEST
41	default BMIPS_GENERIC
42	help
43	  This enables the reset controller driver for BCM6345 SoCs.
44
45config RESET_BERLIN
46	tristate "Berlin Reset Driver"
47	depends on ARCH_BERLIN || COMPILE_TEST
48	default m if ARCH_BERLIN
49	help
50	  This enables the reset controller driver for Marvell Berlin SoCs.
51
52config RESET_BRCMSTB
53	tristate "Broadcom STB reset controller"
54	depends on ARCH_BRCMSTB || COMPILE_TEST
55	default ARCH_BRCMSTB
56	help
57	  This enables the reset controller driver for Broadcom STB SoCs using
58	  a SUN_TOP_CTRL_SW_INIT style controller.
59
60config RESET_BRCMSTB_RESCAL
61	tristate "Broadcom STB RESCAL reset controller"
62	depends on HAS_IOMEM
63	depends on ARCH_BRCMSTB || COMPILE_TEST
64	default ARCH_BRCMSTB
65	help
66	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
67	  BCM7216.
68
69config RESET_EYEQ
70	bool "Mobileye EyeQ reset controller"
71	depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
72	select AUXILIARY_BUS
73	default MACH_EYEQ5 || MACH_EYEQ6H
74	help
75	  This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
76	  and EyeQ6H SoCs.
77
78	  It has one or more domains, with a varying number of resets in each.
79	  Registers are located in a shared register region called OLB. EyeQ6H
80	  has multiple reset instances.
81
82config RESET_GPIO
83	tristate "GPIO reset controller"
84	depends on GPIOLIB
85	help
86	  This enables a generic reset controller for resets attached via
87	  GPIOs.  Typically for OF platforms this driver expects "reset-gpios"
88	  property.
89
90	  If compiled as module, it will be called reset-gpio.
91
92config RESET_HSDK
93	bool "Synopsys HSDK Reset Driver"
94	depends on HAS_IOMEM
95	depends on ARC_SOC_HSDK || COMPILE_TEST
96	help
97	  This enables the reset controller driver for HSDK board.
98
99config RESET_IMX_SCU
100	tristate "i.MX8Q Reset Driver"
101	depends on IMX_SCU && HAVE_ARM_SMCCC
102	depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
103	help
104          This enables the reset controller driver for i.MX8QM/i.MX8QXP
105
106config RESET_IMX7
107	tristate "i.MX7/8 Reset Driver"
108	depends on HAS_IOMEM
109	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
110	default y if SOC_IMX7D
111	select MFD_SYSCON
112	help
113	  This enables the reset controller driver for i.MX7 SoCs.
114
115config RESET_IMX8MP_AUDIOMIX
116	tristate "i.MX8MP AudioMix Reset Driver"
117	depends on ARCH_MXC || COMPILE_TEST
118	select AUXILIARY_BUS
119	default CLK_IMX8MP
120	help
121	  This enables the reset controller driver for i.MX8MP AudioMix
122
123config RESET_INTEL_GW
124	bool "Intel Reset Controller Driver"
125	depends on X86 || COMPILE_TEST
126	depends on OF && HAS_IOMEM
127	select REGMAP_MMIO
128	help
129	  This enables the reset controller driver for Intel Gateway SoCs.
130	  Say Y to control the reset signals provided by reset controller.
131	  Otherwise, say N.
132
133config RESET_K210
134	bool "Reset controller driver for Canaan Kendryte K210 SoC"
135	depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
136	select MFD_SYSCON
137	default SOC_CANAAN_K210
138	help
139	  Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
140	  Say Y if you want to control reset signals provided by this
141	  controller.
142
143config RESET_LANTIQ
144	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
145	default SOC_TYPE_XWAY
146	help
147	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
148
149config RESET_LPC18XX
150	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
151	default ARCH_LPC18XX
152	help
153	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
154
155config RESET_MCHP_SPARX5
156	tristate "Microchip Sparx5 reset driver"
157	depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
158	default y if SPARX5_SWITCH
159	select MFD_SYSCON
160	help
161	  This driver supports switch core reset for the Microchip Sparx5 SoC.
162
163config RESET_NPCM
164	bool "NPCM BMC Reset Driver" if COMPILE_TEST
165	default ARCH_NPCM
166	select AUXILIARY_BUS
167	help
168	  This enables the reset controller driver for Nuvoton NPCM
169	  BMC SoCs.
170
171config RESET_NUVOTON_MA35D1
172	bool "Nuvoton MA35D1 Reset Driver"
173	depends on ARCH_MA35 || COMPILE_TEST
174	default ARCH_MA35
175	help
176	  This enables the reset controller driver for Nuvoton MA35D1 SoC.
177
178config RESET_PISTACHIO
179	bool "Pistachio Reset Driver"
180	depends on MIPS || COMPILE_TEST
181	help
182	  This enables the reset driver for ImgTec Pistachio SoCs.
183
184config RESET_POLARFIRE_SOC
185	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
186	depends on MCHP_CLK_MPFS
187	select AUXILIARY_BUS
188	default MCHP_CLK_MPFS
189	help
190	  This driver supports peripheral reset for the Microchip PolarFire SoC
191
192config RESET_QCOM_AOSS
193	tristate "Qcom AOSS Reset Driver"
194	depends on ARCH_QCOM || COMPILE_TEST
195	help
196	  This enables the AOSS (always on subsystem) reset driver
197	  for Qualcomm SDM845 SoCs. Say Y if you want to control
198	  reset signals provided by AOSS for Modem, Venus, ADSP,
199	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
200
201config RESET_QCOM_PDC
202	tristate "Qualcomm PDC Reset Driver"
203	depends on ARCH_QCOM || COMPILE_TEST
204	help
205	  This enables the PDC (Power Domain Controller) reset driver
206	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
207	  to control reset signals provided by PDC for Modem, Compute,
208	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
209
210config RESET_RASPBERRYPI
211	tristate "Raspberry Pi 4 Firmware Reset Driver"
212	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
213	default USB_XHCI_PCI
214	help
215	  Raspberry Pi 4's co-processor controls some of the board's HW
216	  initialization process, but it's up to Linux to trigger it when
217	  relevant. This driver provides a reset controller capable of
218	  interfacing with RPi4's co-processor and model these firmware
219	  initialization routines as reset lines.
220
221config RESET_RZG2L_USBPHY_CTRL
222	tristate "Renesas RZ/G2L USBPHY control driver"
223	depends on ARCH_RZG2L || COMPILE_TEST
224	help
225	  Support for USBPHY Control found on RZ/G2L family. It mainly
226	  controls reset and power down of the USB/PHY.
227
228config RESET_SCMI
229	tristate "Reset driver controlled via ARM SCMI interface"
230	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
231	default ARM_SCMI_PROTOCOL
232	help
233	  This driver provides support for reset signal/domains that are
234	  controlled by firmware that implements the SCMI interface.
235
236	  This driver uses SCMI Message Protocol to interact with the
237	  firmware controlling all the reset signals.
238
239config RESET_SIMPLE
240	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
241	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
242	depends on HAS_IOMEM
243	help
244	  This enables a simple reset controller driver for reset lines that
245	  that can be asserted and deasserted by toggling bits in a contiguous,
246	  exclusive register space.
247
248	  Currently this driver supports:
249	   - Altera SoCFPGAs
250	   - ASPEED BMC SoCs
251	   - Bitmain BM1880 SoC
252	   - Realtek SoCs
253	   - RCC reset controller in STM32 MCUs
254	   - Allwinner SoCs
255	   - SiFive FU740 SoCs
256	   - Sophgo SoCs
257
258config RESET_SOCFPGA
259	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
260	default ARM && ARCH_INTEL_SOCFPGA
261	select RESET_SIMPLE
262	help
263	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
264	  driver gets initialized early during platform init calls.
265
266config RESET_SUNPLUS
267	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
268	default ARCH_SUNPLUS
269	help
270	  This enables the reset driver support for Sunplus SoCs.
271	  The reset lines that can be asserted and deasserted by toggling bits
272	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
273	  which means each register holds 16 reset lines.
274
275config RESET_SUNXI
276	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
277	default ARCH_SUNXI
278	select RESET_SIMPLE
279	help
280	  This enables the reset driver for Allwinner SoCs.
281
282config RESET_TI_SCI
283	tristate "TI System Control Interface (TI-SCI) reset driver"
284	depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
285	help
286	  This enables the reset driver support over TI System Control Interface
287	  available on some new TI's SoCs. If you wish to use reset resources
288	  managed by the TI System Controller, say Y here. Otherwise, say N.
289
290config RESET_TI_SYSCON
291	tristate "TI SYSCON Reset Driver"
292	depends on HAS_IOMEM
293	select MFD_SYSCON
294	help
295	  This enables the reset driver support for TI devices with
296	  memory-mapped reset registers as part of a syscon device node. If
297	  you wish to use the reset framework for such memory-mapped devices,
298	  say Y here. Otherwise, say N.
299
300config RESET_TI_TPS380X
301	tristate "TI TPS380x Reset Driver"
302	select GPIOLIB
303	help
304	  This enables the reset driver support for TI TPS380x devices. If
305	  you wish to use the reset framework for such devices, say Y here.
306	  Otherwise, say N.
307
308config RESET_TN48M_CPLD
309	tristate "Delta Networks TN48M switch CPLD reset controller"
310	depends on MFD_TN48M_CPLD || COMPILE_TEST
311	default MFD_TN48M_CPLD
312	help
313	  This enables the reset controller driver for the Delta TN48M CPLD.
314	  It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
315	  switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
316	  Microchip PD69200 PoE PSE controller.
317
318	  This driver can also be built as a module. If so, the module will be
319	  called reset-tn48m.
320
321config RESET_UNIPHIER
322	tristate "Reset controller driver for UniPhier SoCs"
323	depends on ARCH_UNIPHIER || COMPILE_TEST
324	depends on OF && MFD_SYSCON
325	default ARCH_UNIPHIER
326	help
327	  Support for reset controllers on UniPhier SoCs.
328	  Say Y if you want to control reset signals provided by System Control
329	  block, Media I/O block, Peripheral Block.
330
331config RESET_UNIPHIER_GLUE
332	tristate "Reset driver in glue layer for UniPhier SoCs"
333	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
334	default ARCH_UNIPHIER
335	select RESET_SIMPLE
336	help
337	  Support for peripheral core reset included in its own glue layer
338	  on UniPhier SoCs. Say Y if you want to control reset signals
339	  provided by the glue layer.
340
341config RESET_ZYNQ
342	bool "ZYNQ Reset Driver" if COMPILE_TEST
343	default ARCH_ZYNQ
344	help
345	  This enables the reset controller driver for Xilinx Zynq SoCs.
346
347config RESET_ZYNQMP
348	bool "ZYNQMP Reset Driver" if COMPILE_TEST
349	default ARCH_ZYNQMP
350	help
351	  This enables the reset controller driver for Xilinx ZynqMP SoCs.
352
353source "drivers/reset/amlogic/Kconfig"
354source "drivers/reset/starfive/Kconfig"
355source "drivers/reset/sti/Kconfig"
356source "drivers/reset/hisilicon/Kconfig"
357source "drivers/reset/tegra/Kconfig"
358
359endif
360