1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 tristate "Berlin Reset Driver" 47 depends on ARCH_BERLIN || COMPILE_TEST 48 default m if ARCH_BERLIN 49 help 50 This enables the reset controller driver for Marvell Berlin SoCs. 51 52config RESET_BRCMSTB 53 tristate "Broadcom STB reset controller" 54 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 55 default ARCH_BRCMSTB || ARCH_BCM2835 56 help 57 This enables the reset controller driver for Broadcom STB SoCs using 58 a SUN_TOP_CTRL_SW_INIT style controller. 59 60config RESET_BRCMSTB_RESCAL 61 tristate "Broadcom STB RESCAL reset controller" 62 depends on HAS_IOMEM 63 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 64 default ARCH_BRCMSTB || ARCH_BCM2835 65 help 66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 67 BCM7216 or the BCM2712. 68 69config RESET_EYEQ 70 bool "Mobileye EyeQ reset controller" 71 depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST 72 select AUXILIARY_BUS 73 default MACH_EYEQ5 || MACH_EYEQ6H 74 help 75 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 76 and EyeQ6H SoCs. 77 78 It has one or more domains, with a varying number of resets in each. 79 Registers are located in a shared register region called OLB. EyeQ6H 80 has multiple reset instances. 81 82config RESET_GPIO 83 tristate "GPIO reset controller" 84 depends on GPIOLIB 85 help 86 This enables a generic reset controller for resets attached via 87 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 88 property. 89 90 If compiled as module, it will be called reset-gpio. 91 92config RESET_HSDK 93 bool "Synopsys HSDK Reset Driver" 94 depends on HAS_IOMEM 95 depends on ARC_SOC_HSDK || COMPILE_TEST 96 help 97 This enables the reset controller driver for HSDK board. 98 99config RESET_IMX_SCU 100 tristate "i.MX8Q Reset Driver" 101 depends on IMX_SCU && HAVE_ARM_SMCCC 102 depends on (ARM64 && ARCH_MXC) || COMPILE_TEST 103 help 104 This enables the reset controller driver for i.MX8QM/i.MX8QXP 105 106config RESET_IMX7 107 tristate "i.MX7/8 Reset Driver" 108 depends on HAS_IOMEM 109 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 110 default y if SOC_IMX7D 111 select MFD_SYSCON 112 help 113 This enables the reset controller driver for i.MX7 SoCs. 114 115config RESET_IMX8MP_AUDIOMIX 116 tristate "i.MX8MP AudioMix Reset Driver" 117 depends on ARCH_MXC || COMPILE_TEST 118 select AUXILIARY_BUS 119 default CLK_IMX8MP 120 help 121 This enables the reset controller driver for i.MX8MP AudioMix 122 123config RESET_INTEL_GW 124 bool "Intel Reset Controller Driver" 125 depends on X86 || COMPILE_TEST 126 depends on OF && HAS_IOMEM 127 select REGMAP_MMIO 128 help 129 This enables the reset controller driver for Intel Gateway SoCs. 130 Say Y to control the reset signals provided by reset controller. 131 Otherwise, say N. 132 133config RESET_K210 134 bool "Reset controller driver for Canaan Kendryte K210 SoC" 135 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 136 select MFD_SYSCON 137 default SOC_CANAAN_K210 138 help 139 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 140 Say Y if you want to control reset signals provided by this 141 controller. 142 143config RESET_K230 144 tristate "Reset controller driver for Canaan Kendryte K230 SoC" 145 depends on ARCH_CANAAN || COMPILE_TEST 146 depends on OF 147 help 148 Support for the Canaan Kendryte K230 RISC-V SoC reset controller. 149 Say Y if you want to control reset signals provided by this 150 controller. 151 152config RESET_LANTIQ 153 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 154 default SOC_TYPE_XWAY 155 help 156 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 157 158config RESET_LPC18XX 159 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 160 default ARCH_LPC18XX 161 help 162 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 163 164config RESET_MCHP_SPARX5 165 tristate "Microchip Sparx5 reset driver" 166 depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 167 default y if SPARX5_SWITCH 168 select MFD_SYSCON 169 help 170 This driver supports switch core reset for the Microchip Sparx5 SoC. 171 172config RESET_NPCM 173 bool "NPCM BMC Reset Driver" if COMPILE_TEST 174 default ARCH_NPCM 175 select AUXILIARY_BUS 176 help 177 This enables the reset controller driver for Nuvoton NPCM 178 BMC SoCs. 179 180config RESET_NUVOTON_MA35D1 181 bool "Nuvoton MA35D1 Reset Driver" 182 depends on ARCH_MA35 || COMPILE_TEST 183 default ARCH_MA35 184 help 185 This enables the reset controller driver for Nuvoton MA35D1 SoC. 186 187config RESET_PISTACHIO 188 bool "Pistachio Reset Driver" 189 depends on MIPS || COMPILE_TEST 190 help 191 This enables the reset driver for ImgTec Pistachio SoCs. 192 193config RESET_POLARFIRE_SOC 194 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 195 depends on MCHP_CLK_MPFS 196 select AUXILIARY_BUS 197 default MCHP_CLK_MPFS 198 help 199 This driver supports peripheral reset for the Microchip PolarFire SoC 200 201config RESET_QCOM_AOSS 202 tristate "Qcom AOSS Reset Driver" 203 depends on ARCH_QCOM || COMPILE_TEST 204 help 205 This enables the AOSS (always on subsystem) reset driver 206 for Qualcomm SDM845 SoCs. Say Y if you want to control 207 reset signals provided by AOSS for Modem, Venus, ADSP, 208 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 209 210config RESET_QCOM_PDC 211 tristate "Qualcomm PDC Reset Driver" 212 depends on ARCH_QCOM || COMPILE_TEST 213 help 214 This enables the PDC (Power Domain Controller) reset driver 215 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 216 to control reset signals provided by PDC for Modem, Compute, 217 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 218 219config RESET_RASPBERRYPI 220 tristate "Raspberry Pi 4 Firmware Reset Driver" 221 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 222 default USB_XHCI_PCI 223 help 224 Raspberry Pi 4's co-processor controls some of the board's HW 225 initialization process, but it's up to Linux to trigger it when 226 relevant. This driver provides a reset controller capable of 227 interfacing with RPi4's co-processor and model these firmware 228 initialization routines as reset lines. 229 230config RESET_RZG2L_USBPHY_CTRL 231 tristate "Renesas RZ/G2L USBPHY control driver" 232 depends on ARCH_RZG2L || COMPILE_TEST 233 help 234 Support for USBPHY Control found on RZ/G2L family. It mainly 235 controls reset and power down of the USB/PHY. 236 237config RESET_RZV2H_USB2PHY 238 tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" 239 depends on ARCH_RENESAS || COMPILE_TEST 240 help 241 Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC 242 (and similar SoCs). 243 244config RESET_SCMI 245 tristate "Reset driver controlled via ARM SCMI interface" 246 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 247 default ARM_SCMI_PROTOCOL 248 help 249 This driver provides support for reset signal/domains that are 250 controlled by firmware that implements the SCMI interface. 251 252 This driver uses SCMI Message Protocol to interact with the 253 firmware controlling all the reset signals. 254 255config RESET_SIMPLE 256 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 257 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 258 depends on HAS_IOMEM 259 help 260 This enables a simple reset controller driver for reset lines that 261 that can be asserted and deasserted by toggling bits in a contiguous, 262 exclusive register space. 263 264 Currently this driver supports: 265 - Altera SoCFPGAs 266 - ASPEED BMC SoCs 267 - Bitmain BM1880 SoC 268 - Realtek SoCs 269 - RCC reset controller in STM32 MCUs 270 - Allwinner SoCs 271 - SiFive FU740 SoCs 272 - Sophgo SoCs 273 274config RESET_SOCFPGA 275 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 276 default ARM && ARCH_INTEL_SOCFPGA 277 select RESET_SIMPLE 278 help 279 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 280 driver gets initialized early during platform init calls. 281 282config RESET_SPACEMIT 283 tristate "SpacemiT reset driver" 284 depends on ARCH_SPACEMIT || COMPILE_TEST 285 select AUXILIARY_BUS 286 default ARCH_SPACEMIT 287 help 288 This enables the reset controller driver for SpacemiT SoCs, 289 including the K1. 290 291config RESET_SUNPLUS 292 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 293 default ARCH_SUNPLUS 294 help 295 This enables the reset driver support for Sunplus SoCs. 296 The reset lines that can be asserted and deasserted by toggling bits 297 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 298 which means each register holds 16 reset lines. 299 300config RESET_SUNXI 301 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 302 default ARCH_SUNXI 303 select RESET_SIMPLE 304 help 305 This enables the reset driver for Allwinner SoCs. 306 307config RESET_TH1520 308 tristate "T-HEAD TH1520 reset controller" 309 depends on ARCH_THEAD || COMPILE_TEST 310 select REGMAP_MMIO 311 help 312 This driver provides support for the T-HEAD TH1520 SoC reset controller, 313 which manages hardware reset lines for SoC components such as the GPU. 314 Enable this option if you need to control hardware resets on TH1520-based 315 systems. 316 317config RESET_TI_SCI 318 tristate "TI System Control Interface (TI-SCI) reset driver" 319 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 320 help 321 This enables the reset driver support over TI System Control Interface 322 available on some new TI's SoCs. If you wish to use reset resources 323 managed by the TI System Controller, say Y here. Otherwise, say N. 324 325config RESET_TI_SYSCON 326 tristate "TI SYSCON Reset Driver" 327 depends on HAS_IOMEM 328 select MFD_SYSCON 329 help 330 This enables the reset driver support for TI devices with 331 memory-mapped reset registers as part of a syscon device node. If 332 you wish to use the reset framework for such memory-mapped devices, 333 say Y here. Otherwise, say N. 334 335config RESET_TI_TPS380X 336 tristate "TI TPS380x Reset Driver" 337 select GPIOLIB 338 help 339 This enables the reset driver support for TI TPS380x devices. If 340 you wish to use the reset framework for such devices, say Y here. 341 Otherwise, say N. 342 343config RESET_TN48M_CPLD 344 tristate "Delta Networks TN48M switch CPLD reset controller" 345 depends on MFD_TN48M_CPLD || COMPILE_TEST 346 default MFD_TN48M_CPLD 347 help 348 This enables the reset controller driver for the Delta TN48M CPLD. 349 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 350 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 351 Microchip PD69200 PoE PSE controller. 352 353 This driver can also be built as a module. If so, the module will be 354 called reset-tn48m. 355 356config RESET_UNIPHIER 357 tristate "Reset controller driver for UniPhier SoCs" 358 depends on ARCH_UNIPHIER || COMPILE_TEST 359 depends on OF && MFD_SYSCON 360 default ARCH_UNIPHIER 361 help 362 Support for reset controllers on UniPhier SoCs. 363 Say Y if you want to control reset signals provided by System Control 364 block, Media I/O block, Peripheral Block. 365 366config RESET_UNIPHIER_GLUE 367 tristate "Reset driver in glue layer for UniPhier SoCs" 368 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 369 default ARCH_UNIPHIER 370 select RESET_SIMPLE 371 help 372 Support for peripheral core reset included in its own glue layer 373 on UniPhier SoCs. Say Y if you want to control reset signals 374 provided by the glue layer. 375 376config RESET_ZYNQ 377 bool "ZYNQ Reset Driver" if COMPILE_TEST 378 default ARCH_ZYNQ 379 help 380 This enables the reset controller driver for Xilinx Zynq SoCs. 381 382config RESET_ZYNQMP 383 bool "ZYNQMP Reset Driver" if COMPILE_TEST 384 default ARCH_ZYNQMP 385 help 386 This enables the reset controller driver for Xilinx ZynqMP SoCs. 387 388source "drivers/reset/amlogic/Kconfig" 389source "drivers/reset/starfive/Kconfig" 390source "drivers/reset/sti/Kconfig" 391source "drivers/reset/hisilicon/Kconfig" 392source "drivers/reset/tegra/Kconfig" 393 394endif 395