1# SPDX-License-Identifier: GPL-2.0-only
2menuconfig CXL_BUS
3	tristate "CXL (Compute Express Link) Devices Support"
4	depends on PCI
5	select FW_LOADER
6	select FW_UPLOAD
7	select PCI_DOE
8	select FIRMWARE_TABLE
9	select NUMA_KEEP_MEMINFO if NUMA_MEMBLKS
10	select FWCTL if CXL_FEATURES
11	help
12	  CXL is a bus that is electrically compatible with PCI Express, but
13	  layers three protocols on that signalling (CXL.io, CXL.cache, and
14	  CXL.mem). The CXL.cache protocol allows devices to hold cachelines
15	  locally, the CXL.mem protocol allows devices to be fully coherent
16	  memory targets, the CXL.io protocol is equivalent to PCI Express.
17	  Say 'y' to enable support for the configuration and management of
18	  devices supporting these protocols.
19
20if CXL_BUS
21
22config CXL_PCI
23	tristate "PCI manageability"
24	default CXL_BUS
25	help
26	  The CXL specification defines a "CXL memory device" sub-class in the
27	  PCI "memory controller" base class of devices. Device's identified by
28	  this class code provide support for volatile and / or persistent
29	  memory to be mapped into the system address map (Host-managed Device
30	  Memory (HDM)).
31
32	  Say 'y/m' to enable a driver that will attach to CXL memory expander
33	  devices enumerated by the memory device class code for configuration
34	  and management primarily via the mailbox interface. See Chapter 2.3
35	  Type 3 CXL Device in the CXL 2.0 specification for more details.
36
37	  If unsure say 'm'.
38
39config CXL_MEM_RAW_COMMANDS
40	bool "RAW Command Interface for Memory Devices"
41	depends on CXL_PCI
42	help
43	  Enable CXL RAW command interface.
44
45	  The CXL driver ioctl interface may assign a kernel ioctl command
46	  number for each specification defined opcode. At any given point in
47	  time the number of opcodes that the specification defines and a device
48	  may implement may exceed the kernel's set of associated ioctl function
49	  numbers. The mismatch is either by omission, specification is too new,
50	  or by design. When prototyping new hardware, or developing / debugging
51	  the driver it is useful to be able to submit any possible command to
52	  the hardware, even commands that may crash the kernel due to their
53	  potential impact to memory currently in use by the kernel.
54
55	  If developing CXL hardware or the driver say Y, otherwise say N.
56
57config CXL_ACPI
58	tristate "CXL ACPI: Platform Support"
59	depends on ACPI
60	depends on ACPI_NUMA
61	default CXL_BUS
62	select ACPI_TABLE_LIB
63	select ACPI_HMAT
64	select CXL_PORT
65	help
66	  Enable support for host managed device memory (HDM) resources
67	  published by a platform's ACPI CXL memory layout description.  See
68	  Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
69	  specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
70	  (https://www.computeexpresslink.org/spec-landing). The CXL core
71	  consumes these resource to publish the root of a cxl_port decode
72	  hierarchy to map regions that represent System RAM, or Persistent
73	  Memory regions to be managed by LIBNVDIMM.
74
75	  If unsure say 'm'.
76
77config CXL_PMEM
78	tristate "CXL PMEM: Persistent Memory Support"
79	depends on LIBNVDIMM
80	default CXL_BUS
81	help
82	  In addition to typical memory resources a platform may also advertise
83	  support for persistent memory attached via CXL. This support is
84	  managed via a bridge driver from CXL to the LIBNVDIMM system
85	  subsystem. Say 'y/m' to enable support for enumerating and
86	  provisioning the persistent memory capacity of CXL memory expanders.
87
88	  If unsure say 'm'.
89
90config CXL_MEM
91	tristate "CXL: Memory Expansion"
92	depends on CXL_PCI
93	default CXL_BUS
94	help
95	  The CXL.mem protocol allows a device to act as a provider of "System
96	  RAM" and/or "Persistent Memory" that is fully coherent as if the
97	  memory were attached to the typical CPU memory controller. This is
98	  known as HDM "Host-managed Device Memory".
99
100	  Say 'y/m' to enable a driver that will attach to CXL.mem devices for
101	  memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
102	  specification for a detailed description of HDM.
103
104	  If unsure say 'm'.
105
106config CXL_FEATURES
107	bool "CXL: Features"
108	depends on CXL_PCI
109	help
110	  Enable support for CXL Features. A CXL device that includes a mailbox
111	  supports commands that allows listing, getting, and setting of
112	  optionally defined features such as memory sparing or post package
113	  sparing. Vendors may define custom features for the device.
114
115	  If unsure say 'n'
116
117config CXL_PORT
118	default CXL_BUS
119	tristate
120
121config CXL_SUSPEND
122	def_bool y
123	depends on SUSPEND && CXL_MEM
124
125config CXL_REGION
126	bool "CXL: Region Support"
127	default CXL_BUS
128	# For MAX_PHYSMEM_BITS
129	depends on SPARSEMEM
130	select MEMREGION
131	select GET_FREE_REGION
132	help
133	  Enable the CXL core to enumerate and provision CXL regions. A CXL
134	  region is defined by one or more CXL expanders that decode a given
135	  system-physical address range. For CXL regions established by
136	  platform-firmware this option enables memory error handling to
137	  identify the devices participating in a given interleaved memory
138	  range. Otherwise, platform-firmware managed CXL is enabled by being
139	  placed in the system address map and does not need a driver.
140
141	  If unsure say 'y'
142
143config CXL_REGION_INVALIDATION_TEST
144	bool "CXL: Region Cache Management Bypass (TEST)"
145	depends on CXL_REGION
146	help
147	  CXL Region management and security operations potentially invalidate
148	  the content of CPU caches without notifying those caches to
149	  invalidate the affected cachelines. The CXL Region driver attempts
150	  to invalidate caches when those events occur.  If that invalidation
151	  fails the region will fail to enable.  Reasons for cache
152	  invalidation failure are due to the CPU not providing a cache
153	  invalidation mechanism. For example usage of wbinvd is restricted to
154	  bare metal x86. However, for testing purposes toggling this option
155	  can disable that data integrity safety and proceed with enabling
156	  regions when there might be conflicting contents in the CPU cache.
157
158	  If unsure, or if this kernel is meant for production environments,
159	  say N.
160
161config CXL_MCE
162	def_bool y
163	depends on X86_MCE && MEMORY_FAILURE
164
165endif
166