1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_MEMBARRIER_SYNC_CORE 38 select ARCH_HAS_MEM_ENCRYPT 39 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS 40 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 41 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 42 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 43 select ARCH_HAS_PREEMPT_LAZY 44 select ARCH_HAS_PTDUMP 45 select ARCH_HAS_PTE_SPECIAL 46 select ARCH_HAS_HW_PTE_YOUNG 47 select ARCH_HAS_SETUP_DMA_OPS 48 select ARCH_HAS_SET_DIRECT_MAP 49 select ARCH_HAS_SET_MEMORY 50 select ARCH_HAS_MEM_ENCRYPT 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_SYSCALL_WRAPPER 58 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 59 select ARCH_HAS_ZONE_DMA_SET if EXPERT 60 select ARCH_HAVE_ELF_PROT 61 select ARCH_HAVE_NMI_SAFE_CMPXCHG 62 select ARCH_HAVE_TRACE_MMIO_ACCESS 63 select ARCH_INLINE_READ_LOCK if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 65 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 70 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 73 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 74 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 77 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 78 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 79 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 83 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 84 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 87 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 88 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 89 select ARCH_KEEP_MEMBLOCK 90 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 91 select ARCH_USE_CMPXCHG_LOCKREF 92 select ARCH_USE_GNU_PROPERTY 93 select ARCH_USE_MEMTEST 94 select ARCH_USE_QUEUED_RWLOCKS 95 select ARCH_USE_QUEUED_SPINLOCKS 96 select ARCH_USE_SYM_ANNOTATIONS 97 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 98 select ARCH_SUPPORTS_HUGETLBFS 99 select ARCH_SUPPORTS_MEMORY_FAILURE 100 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 101 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 102 select ARCH_SUPPORTS_LTO_CLANG_THIN 103 select ARCH_SUPPORTS_CFI_CLANG 104 select ARCH_SUPPORTS_ATOMIC_RMW 105 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 106 select ARCH_SUPPORTS_NUMA_BALANCING 107 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 108 select ARCH_SUPPORTS_PER_VMA_LOCK 109 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 110 select ARCH_SUPPORTS_RT 111 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 112 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 113 select ARCH_WANT_DEFAULT_BPF_JIT 114 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 115 select ARCH_WANT_FRAME_POINTERS 116 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 117 select ARCH_WANT_LD_ORPHAN_WARN 118 select ARCH_WANTS_EXECMEM_LATE 119 select ARCH_WANTS_NO_INSTR 120 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 121 select ARCH_HAS_UBSAN 122 select ARM_AMBA 123 select ARM_ARCH_TIMER 124 select ARM_GIC 125 select AUDIT_ARCH_COMPAT_GENERIC 126 select ARM_GIC_V2M if PCI 127 select ARM_GIC_V3 128 select ARM_GIC_V3_ITS if PCI 129 select ARM_GIC_V5 130 select ARM_PSCI_FW 131 select BUILDTIME_TABLE_SORT 132 select CLONE_BACKWARDS 133 select COMMON_CLK 134 select CPU_PM if (SUSPEND || CPU_IDLE) 135 select CPUMASK_OFFSTACK if NR_CPUS > 256 136 select DCACHE_WORD_ACCESS 137 select HAVE_EXTRA_IPI_TRACEPOINTS 138 select DYNAMIC_FTRACE if FUNCTION_TRACER 139 select DMA_BOUNCE_UNALIGNED_KMALLOC 140 select DMA_DIRECT_REMAP 141 select EDAC_SUPPORT 142 select FRAME_POINTER 143 select FUNCTION_ALIGNMENT_4B 144 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 145 select GENERIC_ALLOCATOR 146 select GENERIC_ARCH_TOPOLOGY 147 select GENERIC_CLOCKEVENTS_BROADCAST 148 select GENERIC_CPU_AUTOPROBE 149 select GENERIC_CPU_DEVICES 150 select GENERIC_CPU_VULNERABILITIES 151 select GENERIC_EARLY_IOREMAP 152 select GENERIC_IDLE_POLL_SETUP 153 select GENERIC_IOREMAP 154 select GENERIC_IRQ_IPI 155 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 156 select GENERIC_IRQ_PROBE 157 select GENERIC_IRQ_SHOW 158 select GENERIC_IRQ_SHOW_LEVEL 159 select GENERIC_LIB_DEVMEM_IS_ALLOWED 160 select GENERIC_PCI_IOMAP 161 select GENERIC_SCHED_CLOCK 162 select GENERIC_SMP_IDLE_THREAD 163 select GENERIC_TIME_VSYSCALL 164 select GENERIC_GETTIMEOFDAY 165 select GENERIC_VDSO_DATA_STORE 166 select GENERIC_VDSO_TIME_NS 167 select HARDIRQS_SW_RESEND 168 select HAS_IOPORT 169 select HAVE_MOVE_PMD 170 select HAVE_MOVE_PUD 171 select HAVE_PCI 172 select HAVE_ACPI_APEI if (ACPI && EFI) 173 select HAVE_ALIGNED_STRUCT_PAGE 174 select HAVE_ARCH_AUDITSYSCALL 175 select HAVE_ARCH_BITREVERSE 176 select HAVE_ARCH_COMPILER_H 177 select HAVE_ARCH_HUGE_VMALLOC 178 select HAVE_ARCH_HUGE_VMAP 179 select HAVE_ARCH_JUMP_LABEL 180 select HAVE_ARCH_JUMP_LABEL_RELATIVE 181 select HAVE_ARCH_KASAN 182 select HAVE_ARCH_KASAN_VMALLOC 183 select HAVE_ARCH_KASAN_SW_TAGS 184 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 185 # Some instrumentation may be unsound, hence EXPERT 186 select HAVE_ARCH_KCSAN if EXPERT 187 select HAVE_ARCH_KFENCE 188 select HAVE_ARCH_KGDB 189 select HAVE_ARCH_KSTACK_ERASE 190 select HAVE_ARCH_MMAP_RND_BITS 191 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 192 select HAVE_ARCH_PREL32_RELOCATIONS 193 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 194 select HAVE_ARCH_SECCOMP_FILTER 195 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 196 select HAVE_ARCH_TRACEHOOK 197 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 198 select HAVE_ARCH_VMAP_STACK 199 select HAVE_ARM_SMCCC 200 select HAVE_ASM_MODVERSIONS 201 select HAVE_EBPF_JIT 202 select HAVE_C_RECORDMCOUNT 203 select HAVE_CMPXCHG_DOUBLE 204 select HAVE_CMPXCHG_LOCAL 205 select HAVE_CONTEXT_TRACKING_USER 206 select HAVE_DEBUG_KMEMLEAK 207 select HAVE_DMA_CONTIGUOUS 208 select HAVE_DYNAMIC_FTRACE 209 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 210 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 211 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 212 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 213 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 214 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 215 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 216 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 217 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 218 if DYNAMIC_FTRACE_WITH_ARGS 219 select HAVE_SAMPLE_FTRACE_DIRECT 220 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 221 select HAVE_BUILDTIME_MCOUNT_SORT 222 select HAVE_EFFICIENT_UNALIGNED_ACCESS 223 select HAVE_GUP_FAST 224 select HAVE_FTRACE_GRAPH_FUNC 225 select HAVE_FUNCTION_TRACER 226 select HAVE_FUNCTION_ERROR_INJECTION 227 select HAVE_FUNCTION_GRAPH_FREGS 228 select HAVE_FUNCTION_GRAPH_TRACER 229 select HAVE_GCC_PLUGINS 230 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 231 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 232 select HAVE_HW_BREAKPOINT if PERF_EVENTS 233 select HAVE_IOREMAP_PROT 234 select HAVE_IRQ_TIME_ACCOUNTING 235 select HAVE_LIVEPATCH 236 select HAVE_MOD_ARCH_SPECIFIC 237 select HAVE_NMI 238 select HAVE_PERF_EVENTS 239 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 240 select HAVE_PERF_REGS 241 select HAVE_PERF_USER_STACK_DUMP 242 select HAVE_PREEMPT_DYNAMIC_KEY 243 select HAVE_REGS_AND_STACK_ACCESS_API 244 select HAVE_RELIABLE_STACKTRACE 245 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 246 select HAVE_FUNCTION_ARG_ACCESS_API 247 select MMU_GATHER_RCU_TABLE_FREE 248 select HAVE_RSEQ 249 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 250 select HAVE_STACKPROTECTOR 251 select HAVE_SYSCALL_TRACEPOINTS 252 select HAVE_KPROBES 253 select HAVE_KRETPROBES 254 select HAVE_GENERIC_VDSO 255 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 256 select HOTPLUG_SMT if HOTPLUG_CPU 257 select IRQ_DOMAIN 258 select IRQ_FORCED_THREADING 259 select JUMP_LABEL 260 select KASAN_VMALLOC if KASAN 261 select LOCK_MM_AND_FIND_VMA 262 select MODULES_USE_ELF_RELA 263 select NEED_DMA_MAP_STATE 264 select NEED_SG_DMA_LENGTH 265 select OF 266 select OF_EARLY_FLATTREE 267 select PCI_DOMAINS_GENERIC if PCI 268 select PCI_ECAM if (ACPI && PCI) 269 select PCI_SYSCALL if PCI 270 select POWER_RESET 271 select POWER_SUPPLY 272 select SPARSE_IRQ 273 select SWIOTLB 274 select SYSCTL_EXCEPTION_TRACE 275 select THREAD_INFO_IN_TASK 276 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 277 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 278 select TRACE_IRQFLAGS_SUPPORT 279 select TRACE_IRQFLAGS_NMI_SUPPORT 280 select HAVE_SOFTIRQ_ON_OWN_STACK 281 select USER_STACKTRACE_SUPPORT 282 select VDSO_GETRANDOM 283 select VMAP_STACK 284 help 285 ARM 64-bit (AArch64) Linux support. 286 287config RUSTC_SUPPORTS_ARM64 288 def_bool y 289 depends on CPU_LITTLE_ENDIAN 290 # Shadow call stack is only supported on certain rustc versions. 291 # 292 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 293 # required due to use of the -Zfixed-x18 flag. 294 # 295 # Otherwise, rustc version 1.82+ is required due to use of the 296 # -Zsanitizer=shadow-call-stack flag. 297 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 298 299config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 300 def_bool CC_IS_CLANG 301 # https://github.com/ClangBuiltLinux/linux/issues/1507 302 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 303 304config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 305 def_bool CC_IS_GCC 306 depends on $(cc-option,-fpatchable-function-entry=2) 307 308config 64BIT 309 def_bool y 310 311config MMU 312 def_bool y 313 314config ARM64_CONT_PTE_SHIFT 315 int 316 default 5 if PAGE_SIZE_64KB 317 default 7 if PAGE_SIZE_16KB 318 default 4 319 320config ARM64_CONT_PMD_SHIFT 321 int 322 default 5 if PAGE_SIZE_64KB 323 default 5 if PAGE_SIZE_16KB 324 default 4 325 326config ARCH_MMAP_RND_BITS_MIN 327 default 14 if PAGE_SIZE_64KB 328 default 16 if PAGE_SIZE_16KB 329 default 18 330 331# max bits determined by the following formula: 332# VA_BITS - PTDESC_TABLE_SHIFT 333config ARCH_MMAP_RND_BITS_MAX 334 default 19 if ARM64_VA_BITS=36 335 default 24 if ARM64_VA_BITS=39 336 default 27 if ARM64_VA_BITS=42 337 default 30 if ARM64_VA_BITS=47 338 default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES 339 default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES 340 default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) 341 default 14 if ARM64_64K_PAGES 342 default 16 if ARM64_16K_PAGES 343 default 18 344 345config ARCH_MMAP_RND_COMPAT_BITS_MIN 346 default 7 if ARM64_64K_PAGES 347 default 9 if ARM64_16K_PAGES 348 default 11 349 350config ARCH_MMAP_RND_COMPAT_BITS_MAX 351 default 16 352 353config NO_IOPORT_MAP 354 def_bool y if !PCI 355 356config STACKTRACE_SUPPORT 357 def_bool y 358 359config ILLEGAL_POINTER_VALUE 360 hex 361 default 0xdead000000000000 362 363config LOCKDEP_SUPPORT 364 def_bool y 365 366config GENERIC_BUG 367 def_bool y 368 depends on BUG 369 370config GENERIC_BUG_RELATIVE_POINTERS 371 def_bool y 372 depends on GENERIC_BUG 373 374config GENERIC_HWEIGHT 375 def_bool y 376 377config GENERIC_CSUM 378 def_bool y 379 380config GENERIC_CALIBRATE_DELAY 381 def_bool y 382 383config SMP 384 def_bool y 385 386config KERNEL_MODE_NEON 387 def_bool y 388 389config FIX_EARLYCON_MEM 390 def_bool y 391 392config PGTABLE_LEVELS 393 int 394 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 395 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 396 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 397 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 398 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 399 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 400 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 401 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 402 403config ARCH_SUPPORTS_UPROBES 404 def_bool y 405 406config ARCH_PROC_KCORE_TEXT 407 def_bool y 408 409config BROKEN_GAS_INST 410 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 411 412config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 413 bool 414 # Clang's __builtin_return_address() strips the PAC since 12.0.0 415 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 416 default y if CC_IS_CLANG 417 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 418 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 419 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 420 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 421 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 422 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 423 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 424 default n 425 426config KASAN_SHADOW_OFFSET 427 hex 428 depends on KASAN_GENERIC || KASAN_SW_TAGS 429 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 430 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 431 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 432 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 433 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 434 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 435 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 436 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 437 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 438 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 439 default 0xffffffffffffffff 440 441config UNWIND_TABLES 442 bool 443 444source "arch/arm64/Kconfig.platforms" 445 446menu "Kernel Features" 447 448menu "ARM errata workarounds via the alternatives framework" 449 450config AMPERE_ERRATUM_AC03_CPU_38 451 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 452 default y 453 help 454 This option adds an alternative code sequence to work around Ampere 455 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 456 457 The affected design reports FEAT_HAFDBS as not implemented in 458 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 459 as required by the architecture. The unadvertised HAFDBS 460 implementation suffers from an additional erratum where hardware 461 A/D updates can occur after a PTE has been marked invalid. 462 463 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 464 which avoids enabling unadvertised hardware Access Flag management 465 at stage-2. 466 467 If unsure, say Y. 468 469config AMPERE_ERRATUM_AC04_CPU_23 470 bool "AmpereOne: AC04_CPU_23: Failure to synchronize writes to HCR_EL2 may corrupt address translations." 471 default y 472 help 473 This option adds an alternative code sequence to work around Ampere 474 errata AC04_CPU_23 on AmpereOne. 475 476 Updates to HCR_EL2 can rarely corrupt simultaneous translations for 477 data addresses initiated by load/store instructions. Only 478 instruction initiated translations are vulnerable, not translations 479 from prefetches for example. A DSB before the store to HCR_EL2 is 480 sufficient to prevent older instructions from hitting the window 481 for corruption, and an ISB after is sufficient to prevent younger 482 instructions from hitting the window for corruption. 483 484 If unsure, say Y. 485 486config ARM64_WORKAROUND_CLEAN_CACHE 487 bool 488 489config ARM64_ERRATUM_826319 490 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 491 default y 492 select ARM64_WORKAROUND_CLEAN_CACHE 493 help 494 This option adds an alternative code sequence to work around ARM 495 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 496 AXI master interface and an L2 cache. 497 498 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 499 and is unable to accept a certain write via this interface, it will 500 not progress on read data presented on the read data channel and the 501 system can deadlock. 502 503 The workaround promotes data cache clean instructions to 504 data cache clean-and-invalidate. 505 Please note that this does not necessarily enable the workaround, 506 as it depends on the alternative framework, which will only patch 507 the kernel if an affected CPU is detected. 508 509 If unsure, say Y. 510 511config ARM64_ERRATUM_827319 512 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 513 default y 514 select ARM64_WORKAROUND_CLEAN_CACHE 515 help 516 This option adds an alternative code sequence to work around ARM 517 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 518 master interface and an L2 cache. 519 520 Under certain conditions this erratum can cause a clean line eviction 521 to occur at the same time as another transaction to the same address 522 on the AMBA 5 CHI interface, which can cause data corruption if the 523 interconnect reorders the two transactions. 524 525 The workaround promotes data cache clean instructions to 526 data cache clean-and-invalidate. 527 Please note that this does not necessarily enable the workaround, 528 as it depends on the alternative framework, which will only patch 529 the kernel if an affected CPU is detected. 530 531 If unsure, say Y. 532 533config ARM64_ERRATUM_824069 534 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 535 default y 536 select ARM64_WORKAROUND_CLEAN_CACHE 537 help 538 This option adds an alternative code sequence to work around ARM 539 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 540 to a coherent interconnect. 541 542 If a Cortex-A53 processor is executing a store or prefetch for 543 write instruction at the same time as a processor in another 544 cluster is executing a cache maintenance operation to the same 545 address, then this erratum might cause a clean cache line to be 546 incorrectly marked as dirty. 547 548 The workaround promotes data cache clean instructions to 549 data cache clean-and-invalidate. 550 Please note that this option does not necessarily enable the 551 workaround, as it depends on the alternative framework, which will 552 only patch the kernel if an affected CPU is detected. 553 554 If unsure, say Y. 555 556config ARM64_ERRATUM_819472 557 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 558 default y 559 select ARM64_WORKAROUND_CLEAN_CACHE 560 help 561 This option adds an alternative code sequence to work around ARM 562 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 563 present when it is connected to a coherent interconnect. 564 565 If the processor is executing a load and store exclusive sequence at 566 the same time as a processor in another cluster is executing a cache 567 maintenance operation to the same address, then this erratum might 568 cause data corruption. 569 570 The workaround promotes data cache clean instructions to 571 data cache clean-and-invalidate. 572 Please note that this does not necessarily enable the workaround, 573 as it depends on the alternative framework, which will only patch 574 the kernel if an affected CPU is detected. 575 576 If unsure, say Y. 577 578config ARM64_ERRATUM_832075 579 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 580 default y 581 help 582 This option adds an alternative code sequence to work around ARM 583 erratum 832075 on Cortex-A57 parts up to r1p2. 584 585 Affected Cortex-A57 parts might deadlock when exclusive load/store 586 instructions to Write-Back memory are mixed with Device loads. 587 588 The workaround is to promote device loads to use Load-Acquire 589 semantics. 590 Please note that this does not necessarily enable the workaround, 591 as it depends on the alternative framework, which will only patch 592 the kernel if an affected CPU is detected. 593 594 If unsure, say Y. 595 596config ARM64_ERRATUM_834220 597 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 598 depends on KVM 599 help 600 This option adds an alternative code sequence to work around ARM 601 erratum 834220 on Cortex-A57 parts up to r1p2. 602 603 Affected Cortex-A57 parts might report a Stage 2 translation 604 fault as the result of a Stage 1 fault for load crossing a 605 page boundary when there is a permission or device memory 606 alignment fault at Stage 1 and a translation fault at Stage 2. 607 608 The workaround is to verify that the Stage 1 translation 609 doesn't generate a fault before handling the Stage 2 fault. 610 Please note that this does not necessarily enable the workaround, 611 as it depends on the alternative framework, which will only patch 612 the kernel if an affected CPU is detected. 613 614 If unsure, say N. 615 616config ARM64_ERRATUM_1742098 617 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 618 depends on COMPAT 619 default y 620 help 621 This option removes the AES hwcap for aarch32 user-space to 622 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 623 624 Affected parts may corrupt the AES state if an interrupt is 625 taken between a pair of AES instructions. These instructions 626 are only present if the cryptography extensions are present. 627 All software should have a fallback implementation for CPUs 628 that don't implement the cryptography extensions. 629 630 If unsure, say Y. 631 632config ARM64_ERRATUM_845719 633 bool "Cortex-A53: 845719: a load might read incorrect data" 634 depends on COMPAT 635 default y 636 help 637 This option adds an alternative code sequence to work around ARM 638 erratum 845719 on Cortex-A53 parts up to r0p4. 639 640 When running a compat (AArch32) userspace on an affected Cortex-A53 641 part, a load at EL0 from a virtual address that matches the bottom 32 642 bits of the virtual address used by a recent load at (AArch64) EL1 643 might return incorrect data. 644 645 The workaround is to write the contextidr_el1 register on exception 646 return to a 32-bit task. 647 Please note that this does not necessarily enable the workaround, 648 as it depends on the alternative framework, which will only patch 649 the kernel if an affected CPU is detected. 650 651 If unsure, say Y. 652 653config ARM64_ERRATUM_843419 654 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 655 default y 656 help 657 This option links the kernel with '--fix-cortex-a53-843419' and 658 enables PLT support to replace certain ADRP instructions, which can 659 cause subsequent memory accesses to use an incorrect address on 660 Cortex-A53 parts up to r0p4. 661 662 If unsure, say Y. 663 664config ARM64_ERRATUM_1024718 665 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 666 default y 667 help 668 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 669 670 Affected Cortex-A55 cores (all revisions) could cause incorrect 671 update of the hardware dirty bit when the DBM/AP bits are updated 672 without a break-before-make. The workaround is to disable the usage 673 of hardware DBM locally on the affected cores. CPUs not affected by 674 this erratum will continue to use the feature. 675 676 If unsure, say Y. 677 678config ARM64_ERRATUM_1418040 679 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 680 default y 681 depends on COMPAT 682 help 683 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 684 errata 1188873 and 1418040. 685 686 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 687 cause register corruption when accessing the timer registers 688 from AArch32 userspace. 689 690 If unsure, say Y. 691 692config ARM64_WORKAROUND_SPECULATIVE_AT 693 bool 694 695config ARM64_ERRATUM_1165522 696 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 697 default y 698 select ARM64_WORKAROUND_SPECULATIVE_AT 699 help 700 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 701 702 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 703 corrupted TLBs by speculating an AT instruction during a guest 704 context switch. 705 706 If unsure, say Y. 707 708config ARM64_ERRATUM_1319367 709 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 710 default y 711 select ARM64_WORKAROUND_SPECULATIVE_AT 712 help 713 This option adds work arounds for ARM Cortex-A57 erratum 1319537 714 and A72 erratum 1319367 715 716 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 717 speculating an AT instruction during a guest context switch. 718 719 If unsure, say Y. 720 721config ARM64_ERRATUM_1530923 722 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 723 default y 724 select ARM64_WORKAROUND_SPECULATIVE_AT 725 help 726 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 727 728 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 729 corrupted TLBs by speculating an AT instruction during a guest 730 context switch. 731 732 If unsure, say Y. 733 734config ARM64_WORKAROUND_REPEAT_TLBI 735 bool 736 737config ARM64_ERRATUM_2441007 738 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 739 select ARM64_WORKAROUND_REPEAT_TLBI 740 help 741 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 742 743 Under very rare circumstances, affected Cortex-A55 CPUs 744 may not handle a race between a break-before-make sequence on one 745 CPU, and another CPU accessing the same page. This could allow a 746 store to a page that has been unmapped. 747 748 Work around this by adding the affected CPUs to the list that needs 749 TLB sequences to be done twice. 750 751 If unsure, say N. 752 753config ARM64_ERRATUM_1286807 754 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 755 select ARM64_WORKAROUND_REPEAT_TLBI 756 help 757 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 758 759 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 760 address for a cacheable mapping of a location is being 761 accessed by a core while another core is remapping the virtual 762 address to a new physical page using the recommended 763 break-before-make sequence, then under very rare circumstances 764 TLBI+DSB completes before a read using the translation being 765 invalidated has been observed by other observers. The 766 workaround repeats the TLBI+DSB operation. 767 768 If unsure, say N. 769 770config ARM64_ERRATUM_1463225 771 bool "Cortex-A76: Software Step might prevent interrupt recognition" 772 default y 773 help 774 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 775 776 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 777 of a system call instruction (SVC) can prevent recognition of 778 subsequent interrupts when software stepping is disabled in the 779 exception handler of the system call and either kernel debugging 780 is enabled or VHE is in use. 781 782 Work around the erratum by triggering a dummy step exception 783 when handling a system call from a task that is being stepped 784 in a VHE configuration of the kernel. 785 786 If unsure, say Y. 787 788config ARM64_ERRATUM_1542419 789 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 790 help 791 This option adds a workaround for ARM Neoverse-N1 erratum 792 1542419. 793 794 Affected Neoverse-N1 cores could execute a stale instruction when 795 modified by another CPU. The workaround depends on a firmware 796 counterpart. 797 798 Workaround the issue by hiding the DIC feature from EL0. This 799 forces user-space to perform cache maintenance. 800 801 If unsure, say N. 802 803config ARM64_ERRATUM_1508412 804 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 805 default y 806 help 807 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 808 809 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 810 of a store-exclusive or read of PAR_EL1 and a load with device or 811 non-cacheable memory attributes. The workaround depends on a firmware 812 counterpart. 813 814 KVM guests must also have the workaround implemented or they can 815 deadlock the system. 816 817 Work around the issue by inserting DMB SY barriers around PAR_EL1 818 register reads and warning KVM users. The DMB barrier is sufficient 819 to prevent a speculative PAR_EL1 read. 820 821 If unsure, say Y. 822 823config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 824 bool 825 826config ARM64_ERRATUM_2051678 827 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 828 default y 829 help 830 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 831 Affected Cortex-A510 might not respect the ordering rules for 832 hardware update of the page table's dirty bit. The workaround 833 is to not enable the feature on affected CPUs. 834 835 If unsure, say Y. 836 837config ARM64_ERRATUM_2077057 838 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 839 default y 840 help 841 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 842 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 843 expected, but a Pointer Authentication trap is taken instead. The 844 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 845 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 846 847 This can only happen when EL2 is stepping EL1. 848 849 When these conditions occur, the SPSR_EL2 value is unchanged from the 850 previous guest entry, and can be restored from the in-memory copy. 851 852 If unsure, say Y. 853 854config ARM64_ERRATUM_2658417 855 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 856 default y 857 help 858 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 859 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 860 BFMMLA or VMMLA instructions in rare circumstances when a pair of 861 A510 CPUs are using shared neon hardware. As the sharing is not 862 discoverable by the kernel, hide the BF16 HWCAP to indicate that 863 user-space should not be using these instructions. 864 865 If unsure, say Y. 866 867config ARM64_ERRATUM_2119858 868 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 869 default y 870 depends on CORESIGHT_TRBE 871 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 872 help 873 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 874 875 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 876 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 877 the event of a WRAP event. 878 879 Work around the issue by always making sure we move the TRBPTR_EL1 by 880 256 bytes before enabling the buffer and filling the first 256 bytes of 881 the buffer with ETM ignore packets upon disabling. 882 883 If unsure, say Y. 884 885config ARM64_ERRATUM_2139208 886 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 887 default y 888 depends on CORESIGHT_TRBE 889 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 890 help 891 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 892 893 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 894 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 895 the event of a WRAP event. 896 897 Work around the issue by always making sure we move the TRBPTR_EL1 by 898 256 bytes before enabling the buffer and filling the first 256 bytes of 899 the buffer with ETM ignore packets upon disabling. 900 901 If unsure, say Y. 902 903config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 904 bool 905 906config ARM64_ERRATUM_2054223 907 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 908 default y 909 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 910 help 911 Enable workaround for ARM Cortex-A710 erratum 2054223 912 913 Affected cores may fail to flush the trace data on a TSB instruction, when 914 the PE is in trace prohibited state. This will cause losing a few bytes 915 of the trace cached. 916 917 Workaround is to issue two TSB consecutively on affected cores. 918 919 If unsure, say Y. 920 921config ARM64_ERRATUM_2067961 922 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 923 default y 924 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 925 help 926 Enable workaround for ARM Neoverse-N2 erratum 2067961 927 928 Affected cores may fail to flush the trace data on a TSB instruction, when 929 the PE is in trace prohibited state. This will cause losing a few bytes 930 of the trace cached. 931 932 Workaround is to issue two TSB consecutively on affected cores. 933 934 If unsure, say Y. 935 936config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 937 bool 938 939config ARM64_ERRATUM_2253138 940 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 941 depends on CORESIGHT_TRBE 942 default y 943 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 944 help 945 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 946 947 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 948 for TRBE. Under some conditions, the TRBE might generate a write to the next 949 virtually addressed page following the last page of the TRBE address space 950 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 951 952 Work around this in the driver by always making sure that there is a 953 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 954 955 If unsure, say Y. 956 957config ARM64_ERRATUM_2224489 958 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 959 depends on CORESIGHT_TRBE 960 default y 961 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 962 help 963 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 964 965 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 966 for TRBE. Under some conditions, the TRBE might generate a write to the next 967 virtually addressed page following the last page of the TRBE address space 968 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 969 970 Work around this in the driver by always making sure that there is a 971 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 972 973 If unsure, say Y. 974 975config ARM64_ERRATUM_2441009 976 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 977 select ARM64_WORKAROUND_REPEAT_TLBI 978 help 979 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 980 981 Under very rare circumstances, affected Cortex-A510 CPUs 982 may not handle a race between a break-before-make sequence on one 983 CPU, and another CPU accessing the same page. This could allow a 984 store to a page that has been unmapped. 985 986 Work around this by adding the affected CPUs to the list that needs 987 TLB sequences to be done twice. 988 989 If unsure, say N. 990 991config ARM64_ERRATUM_2064142 992 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 993 depends on CORESIGHT_TRBE 994 default y 995 help 996 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 997 998 Affected Cortex-A510 core might fail to write into system registers after the 999 TRBE has been disabled. Under some conditions after the TRBE has been disabled 1000 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 1001 and TRBTRG_EL1 will be ignored and will not be effected. 1002 1003 Work around this in the driver by executing TSB CSYNC and DSB after collection 1004 is stopped and before performing a system register write to one of the affected 1005 registers. 1006 1007 If unsure, say Y. 1008 1009config ARM64_ERRATUM_2038923 1010 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 1011 depends on CORESIGHT_TRBE 1012 default y 1013 help 1014 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 1015 1016 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 1017 prohibited within the CPU. As a result, the trace buffer or trace buffer state 1018 might be corrupted. This happens after TRBE buffer has been enabled by setting 1019 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 1020 execution changes from a context, in which trace is prohibited to one where it 1021 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1022 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1023 the trace buffer state might be corrupted. 1024 1025 Work around this in the driver by preventing an inconsistent view of whether the 1026 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1027 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1028 two ISB instructions if no ERET is to take place. 1029 1030 If unsure, say Y. 1031 1032config ARM64_ERRATUM_1902691 1033 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1034 depends on CORESIGHT_TRBE 1035 default y 1036 help 1037 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1038 1039 Affected Cortex-A510 core might cause trace data corruption, when being written 1040 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1041 trace data. 1042 1043 Work around this problem in the driver by just preventing TRBE initialization on 1044 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1045 on such implementations. This will cover the kernel for any firmware that doesn't 1046 do this already. 1047 1048 If unsure, say Y. 1049 1050config ARM64_ERRATUM_2457168 1051 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1052 depends on ARM64_AMU_EXTN 1053 default y 1054 help 1055 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1056 1057 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1058 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1059 incorrectly giving a significantly higher output value. 1060 1061 Work around this problem by returning 0 when reading the affected counter in 1062 key locations that results in disabling all users of this counter. This effect 1063 is the same to firmware disabling affected counters. 1064 1065 If unsure, say Y. 1066 1067config ARM64_ERRATUM_2645198 1068 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1069 default y 1070 help 1071 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1072 1073 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1074 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1075 next instruction abort caused by permission fault. 1076 1077 Only user-space does executable to non-executable permission transition via 1078 mprotect() system call. Workaround the problem by doing a break-before-make 1079 TLB invalidation, for all changes to executable user space mappings. 1080 1081 If unsure, say Y. 1082 1083config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1084 bool 1085 1086config ARM64_ERRATUM_2966298 1087 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1088 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1089 default y 1090 help 1091 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1092 1093 On an affected Cortex-A520 core, a speculatively executed unprivileged 1094 load might leak data from a privileged level via a cache side channel. 1095 1096 Work around this problem by executing a TLBI before returning to EL0. 1097 1098 If unsure, say Y. 1099 1100config ARM64_ERRATUM_3117295 1101 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1102 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1103 default y 1104 help 1105 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1106 1107 On an affected Cortex-A510 core, a speculatively executed unprivileged 1108 load might leak data from a privileged level via a cache side channel. 1109 1110 Work around this problem by executing a TLBI before returning to EL0. 1111 1112 If unsure, say Y. 1113 1114config ARM64_ERRATUM_3194386 1115 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1116 default y 1117 help 1118 This option adds the workaround for the following errata: 1119 1120 * ARM Cortex-A76 erratum 3324349 1121 * ARM Cortex-A77 erratum 3324348 1122 * ARM Cortex-A78 erratum 3324344 1123 * ARM Cortex-A78C erratum 3324346 1124 * ARM Cortex-A78C erratum 3324347 1125 * ARM Cortex-A710 erratam 3324338 1126 * ARM Cortex-A715 errartum 3456084 1127 * ARM Cortex-A720 erratum 3456091 1128 * ARM Cortex-A725 erratum 3456106 1129 * ARM Cortex-X1 erratum 3324344 1130 * ARM Cortex-X1C erratum 3324346 1131 * ARM Cortex-X2 erratum 3324338 1132 * ARM Cortex-X3 erratum 3324335 1133 * ARM Cortex-X4 erratum 3194386 1134 * ARM Cortex-X925 erratum 3324334 1135 * ARM Neoverse-N1 erratum 3324349 1136 * ARM Neoverse N2 erratum 3324339 1137 * ARM Neoverse-N3 erratum 3456111 1138 * ARM Neoverse-V1 erratum 3324341 1139 * ARM Neoverse V2 erratum 3324336 1140 * ARM Neoverse-V3 erratum 3312417 1141 1142 On affected cores "MSR SSBS, #0" instructions may not affect 1143 subsequent speculative instructions, which may permit unexepected 1144 speculative store bypassing. 1145 1146 Work around this problem by placing a Speculation Barrier (SB) or 1147 Instruction Synchronization Barrier (ISB) after kernel changes to 1148 SSBS. The presence of the SSBS special-purpose register is hidden 1149 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1150 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1151 1152 If unsure, say Y. 1153 1154config CAVIUM_ERRATUM_22375 1155 bool "Cavium erratum 22375, 24313" 1156 default y 1157 help 1158 Enable workaround for errata 22375 and 24313. 1159 1160 This implements two gicv3-its errata workarounds for ThunderX. Both 1161 with a small impact affecting only ITS table allocation. 1162 1163 erratum 22375: only alloc 8MB table size 1164 erratum 24313: ignore memory access type 1165 1166 The fixes are in ITS initialization and basically ignore memory access 1167 type and table size provided by the TYPER and BASER registers. 1168 1169 If unsure, say Y. 1170 1171config CAVIUM_ERRATUM_23144 1172 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1173 depends on NUMA 1174 default y 1175 help 1176 ITS SYNC command hang for cross node io and collections/cpu mapping. 1177 1178 If unsure, say Y. 1179 1180config CAVIUM_ERRATUM_23154 1181 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1182 default y 1183 help 1184 The ThunderX GICv3 implementation requires a modified version for 1185 reading the IAR status to ensure data synchronization 1186 (access to icc_iar1_el1 is not sync'ed before and after). 1187 1188 It also suffers from erratum 38545 (also present on Marvell's 1189 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1190 spuriously presented to the CPU interface. 1191 1192 If unsure, say Y. 1193 1194config CAVIUM_ERRATUM_27456 1195 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1196 default y 1197 help 1198 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1199 instructions may cause the icache to become corrupted if it 1200 contains data for a non-current ASID. The fix is to 1201 invalidate the icache when changing the mm context. 1202 1203 If unsure, say Y. 1204 1205config CAVIUM_ERRATUM_30115 1206 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1207 default y 1208 help 1209 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1210 1.2, and T83 Pass 1.0, KVM guest execution may disable 1211 interrupts in host. Trapping both GICv3 group-0 and group-1 1212 accesses sidesteps the issue. 1213 1214 If unsure, say Y. 1215 1216config CAVIUM_TX2_ERRATUM_219 1217 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1218 default y 1219 help 1220 On Cavium ThunderX2, a load, store or prefetch instruction between a 1221 TTBR update and the corresponding context synchronizing operation can 1222 cause a spurious Data Abort to be delivered to any hardware thread in 1223 the CPU core. 1224 1225 Work around the issue by avoiding the problematic code sequence and 1226 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1227 trap handler performs the corresponding register access, skips the 1228 instruction and ensures context synchronization by virtue of the 1229 exception return. 1230 1231 If unsure, say Y. 1232 1233config FUJITSU_ERRATUM_010001 1234 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1235 default y 1236 help 1237 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1238 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1239 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1240 This fault occurs under a specific hardware condition when a 1241 load/store instruction performs an address translation using: 1242 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1243 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1244 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1245 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1246 1247 The workaround is to ensure these bits are clear in TCR_ELx. 1248 The workaround only affects the Fujitsu-A64FX. 1249 1250 If unsure, say Y. 1251 1252config HISILICON_ERRATUM_161600802 1253 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1254 default y 1255 help 1256 The HiSilicon Hip07 SoC uses the wrong redistributor base 1257 when issued ITS commands such as VMOVP and VMAPP, and requires 1258 a 128kB offset to be applied to the target address in this commands. 1259 1260 If unsure, say Y. 1261 1262config HISILICON_ERRATUM_162100801 1263 bool "Hip09 162100801 erratum support" 1264 default y 1265 help 1266 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1267 during unmapping operation, which will cause some vSGIs lost. 1268 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1269 after VMOVP. 1270 1271 If unsure, say Y. 1272 1273config QCOM_FALKOR_ERRATUM_1003 1274 bool "Falkor E1003: Incorrect translation due to ASID change" 1275 default y 1276 help 1277 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1278 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1279 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1280 then only for entries in the walk cache, since the leaf translation 1281 is unchanged. Work around the erratum by invalidating the walk cache 1282 entries for the trampoline before entering the kernel proper. 1283 1284config QCOM_FALKOR_ERRATUM_1009 1285 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1286 default y 1287 select ARM64_WORKAROUND_REPEAT_TLBI 1288 help 1289 On Falkor v1, the CPU may prematurely complete a DSB following a 1290 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1291 one more time to fix the issue. 1292 1293 If unsure, say Y. 1294 1295config QCOM_QDF2400_ERRATUM_0065 1296 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1297 default y 1298 help 1299 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1300 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1301 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1302 1303 If unsure, say Y. 1304 1305config QCOM_FALKOR_ERRATUM_E1041 1306 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1307 default y 1308 help 1309 Falkor CPU may speculatively fetch instructions from an improper 1310 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1311 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1312 1313 If unsure, say Y. 1314 1315config NVIDIA_CARMEL_CNP_ERRATUM 1316 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1317 default y 1318 help 1319 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1320 invalidate shared TLB entries installed by a different core, as it would 1321 on standard ARM cores. 1322 1323 If unsure, say Y. 1324 1325config ROCKCHIP_ERRATUM_3568002 1326 bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" 1327 default y 1328 help 1329 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI 1330 addressing limited to the first 32bit of physical address space. 1331 1332 If unsure, say Y. 1333 1334config ROCKCHIP_ERRATUM_3588001 1335 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1336 default y 1337 help 1338 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1339 This means, that its sharability feature may not be used, even though it 1340 is supported by the IP itself. 1341 1342 If unsure, say Y. 1343 1344config SOCIONEXT_SYNQUACER_PREITS 1345 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1346 default y 1347 help 1348 Socionext Synquacer SoCs implement a separate h/w block to generate 1349 MSI doorbell writes with non-zero values for the device ID. 1350 1351 If unsure, say Y. 1352 1353endmenu # "ARM errata workarounds via the alternatives framework" 1354 1355choice 1356 prompt "Page size" 1357 default ARM64_4K_PAGES 1358 help 1359 Page size (translation granule) configuration. 1360 1361config ARM64_4K_PAGES 1362 bool "4KB" 1363 select HAVE_PAGE_SIZE_4KB 1364 help 1365 This feature enables 4KB pages support. 1366 1367config ARM64_16K_PAGES 1368 bool "16KB" 1369 select HAVE_PAGE_SIZE_16KB 1370 help 1371 The system will use 16KB pages support. AArch32 emulation 1372 requires applications compiled with 16K (or a multiple of 16K) 1373 aligned segments. 1374 1375config ARM64_64K_PAGES 1376 bool "64KB" 1377 select HAVE_PAGE_SIZE_64KB 1378 help 1379 This feature enables 64KB pages support (4KB by default) 1380 allowing only two levels of page tables and faster TLB 1381 look-up. AArch32 emulation requires applications compiled 1382 with 64K aligned segments. 1383 1384endchoice 1385 1386choice 1387 prompt "Virtual address space size" 1388 default ARM64_VA_BITS_52 1389 help 1390 Allows choosing one of multiple possible virtual address 1391 space sizes. The level of translation table is determined by 1392 a combination of page size and virtual address space size. 1393 1394config ARM64_VA_BITS_36 1395 bool "36-bit" if EXPERT 1396 depends on PAGE_SIZE_16KB 1397 1398config ARM64_VA_BITS_39 1399 bool "39-bit" 1400 depends on PAGE_SIZE_4KB 1401 1402config ARM64_VA_BITS_42 1403 bool "42-bit" 1404 depends on PAGE_SIZE_64KB 1405 1406config ARM64_VA_BITS_47 1407 bool "47-bit" 1408 depends on PAGE_SIZE_16KB 1409 1410config ARM64_VA_BITS_48 1411 bool "48-bit" 1412 1413config ARM64_VA_BITS_52 1414 bool "52-bit" 1415 help 1416 Enable 52-bit virtual addressing for userspace when explicitly 1417 requested via a hint to mmap(). The kernel will also use 52-bit 1418 virtual addresses for its own mappings (provided HW support for 1419 this feature is available, otherwise it reverts to 48-bit). 1420 1421 NOTE: Enabling 52-bit virtual addressing in conjunction with 1422 ARMv8.3 Pointer Authentication will result in the PAC being 1423 reduced from 7 bits to 3 bits, which may have a significant 1424 impact on its susceptibility to brute-force attacks. 1425 1426 If unsure, select 48-bit virtual addressing instead. 1427 1428endchoice 1429 1430config ARM64_FORCE_52BIT 1431 bool "Force 52-bit virtual addresses for userspace" 1432 depends on ARM64_VA_BITS_52 && EXPERT 1433 help 1434 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1435 to maintain compatibility with older software by providing 48-bit VAs 1436 unless a hint is supplied to mmap. 1437 1438 This configuration option disables the 48-bit compatibility logic, and 1439 forces all userspace addresses to be 52-bit on HW that supports it. One 1440 should only enable this configuration option for stress testing userspace 1441 memory management code. If unsure say N here. 1442 1443config ARM64_VA_BITS 1444 int 1445 default 36 if ARM64_VA_BITS_36 1446 default 39 if ARM64_VA_BITS_39 1447 default 42 if ARM64_VA_BITS_42 1448 default 47 if ARM64_VA_BITS_47 1449 default 48 if ARM64_VA_BITS_48 1450 default 52 if ARM64_VA_BITS_52 1451 1452choice 1453 prompt "Physical address space size" 1454 default ARM64_PA_BITS_48 1455 help 1456 Choose the maximum physical address range that the kernel will 1457 support. 1458 1459config ARM64_PA_BITS_48 1460 bool "48-bit" 1461 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1462 1463config ARM64_PA_BITS_52 1464 bool "52-bit" 1465 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1466 help 1467 Enable support for a 52-bit physical address space, introduced as 1468 part of the ARMv8.2-LPA extension. 1469 1470 With this enabled, the kernel will also continue to work on CPUs that 1471 do not support ARMv8.2-LPA, but with some added memory overhead (and 1472 minor performance overhead). 1473 1474endchoice 1475 1476config ARM64_PA_BITS 1477 int 1478 default 48 if ARM64_PA_BITS_48 1479 default 52 if ARM64_PA_BITS_52 1480 1481config ARM64_LPA2 1482 def_bool y 1483 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1484 1485choice 1486 prompt "Endianness" 1487 default CPU_LITTLE_ENDIAN 1488 help 1489 Select the endianness of data accesses performed by the CPU. Userspace 1490 applications will need to be compiled and linked for the endianness 1491 that is selected here. 1492 1493config CPU_BIG_ENDIAN 1494 bool "Build big-endian kernel" 1495 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1496 depends on AS_IS_GNU || AS_VERSION >= 150000 1497 help 1498 Say Y if you plan on running a kernel with a big-endian userspace. 1499 1500config CPU_LITTLE_ENDIAN 1501 bool "Build little-endian kernel" 1502 help 1503 Say Y if you plan on running a kernel with a little-endian userspace. 1504 This is usually the case for distributions targeting arm64. 1505 1506endchoice 1507 1508config SCHED_MC 1509 bool "Multi-core scheduler support" 1510 help 1511 Multi-core scheduler support improves the CPU scheduler's decision 1512 making when dealing with multi-core CPU chips at a cost of slightly 1513 increased overhead in some places. If unsure say N here. 1514 1515config SCHED_CLUSTER 1516 bool "Cluster scheduler support" 1517 help 1518 Cluster scheduler support improves the CPU scheduler's decision 1519 making when dealing with machines that have clusters of CPUs. 1520 Cluster usually means a couple of CPUs which are placed closely 1521 by sharing mid-level caches, last-level cache tags or internal 1522 busses. 1523 1524config SCHED_SMT 1525 bool "SMT scheduler support" 1526 help 1527 Improves the CPU scheduler's decision making when dealing with 1528 MultiThreading at a cost of slightly increased overhead in some 1529 places. If unsure say N here. 1530 1531config NR_CPUS 1532 int "Maximum number of CPUs (2-4096)" 1533 range 2 4096 1534 default "512" 1535 1536config HOTPLUG_CPU 1537 bool "Support for hot-pluggable CPUs" 1538 select GENERIC_IRQ_MIGRATION 1539 help 1540 Say Y here to experiment with turning CPUs off and on. CPUs 1541 can be controlled through /sys/devices/system/cpu. 1542 1543# Common NUMA Features 1544config NUMA 1545 bool "NUMA Memory Allocation and Scheduler Support" 1546 select GENERIC_ARCH_NUMA 1547 select OF_NUMA 1548 select HAVE_SETUP_PER_CPU_AREA 1549 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1550 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1551 select USE_PERCPU_NUMA_NODE_ID 1552 help 1553 Enable NUMA (Non-Uniform Memory Access) support. 1554 1555 The kernel will try to allocate memory used by a CPU on the 1556 local memory of the CPU and add some more 1557 NUMA awareness to the kernel. 1558 1559config NODES_SHIFT 1560 int "Maximum NUMA Nodes (as a power of 2)" 1561 range 1 10 1562 default "4" 1563 depends on NUMA 1564 help 1565 Specify the maximum number of NUMA Nodes available on the target 1566 system. Increases memory reserved to accommodate various tables. 1567 1568source "kernel/Kconfig.hz" 1569 1570config ARCH_SPARSEMEM_ENABLE 1571 def_bool y 1572 select SPARSEMEM_VMEMMAP_ENABLE 1573 select SPARSEMEM_VMEMMAP 1574 1575config HW_PERF_EVENTS 1576 def_bool y 1577 depends on ARM_PMU 1578 1579# Supported by clang >= 7.0 or GCC >= 12.0.0 1580config CC_HAVE_SHADOW_CALL_STACK 1581 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1582 1583config PARAVIRT 1584 bool "Enable paravirtualization code" 1585 help 1586 This changes the kernel so it can modify itself when it is run 1587 under a hypervisor, potentially improving performance significantly 1588 over full virtualization. 1589 1590config PARAVIRT_TIME_ACCOUNTING 1591 bool "Paravirtual steal time accounting" 1592 select PARAVIRT 1593 help 1594 Select this option to enable fine granularity task steal time 1595 accounting. Time spent executing other tasks in parallel with 1596 the current vCPU is discounted from the vCPU power. To account for 1597 that, there can be a small performance impact. 1598 1599 If in doubt, say N here. 1600 1601config ARCH_SUPPORTS_KEXEC 1602 def_bool PM_SLEEP_SMP 1603 1604config ARCH_SUPPORTS_KEXEC_FILE 1605 def_bool y 1606 1607config ARCH_SELECTS_KEXEC_FILE 1608 def_bool y 1609 depends on KEXEC_FILE 1610 select HAVE_IMA_KEXEC if IMA 1611 1612config ARCH_SUPPORTS_KEXEC_SIG 1613 def_bool y 1614 1615config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1616 def_bool y 1617 1618config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1619 def_bool y 1620 1621config ARCH_SUPPORTS_KEXEC_HANDOVER 1622 def_bool y 1623 1624config ARCH_SUPPORTS_CRASH_DUMP 1625 def_bool y 1626 1627config ARCH_DEFAULT_CRASH_DUMP 1628 def_bool y 1629 1630config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1631 def_bool CRASH_RESERVE 1632 1633config TRANS_TABLE 1634 def_bool y 1635 depends on HIBERNATION || KEXEC_CORE 1636 1637config XEN_DOM0 1638 def_bool y 1639 depends on XEN 1640 1641config XEN 1642 bool "Xen guest support on ARM64" 1643 depends on ARM64 && OF 1644 select SWIOTLB_XEN 1645 select PARAVIRT 1646 help 1647 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1648 1649# include/linux/mmzone.h requires the following to be true: 1650# 1651# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1652# 1653# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1654# 1655# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1656# ----+-------------------+--------------+----------------------+-------------------------+ 1657# 4K | 27 | 12 | 15 | 10 | 1658# 16K | 27 | 14 | 13 | 11 | 1659# 64K | 29 | 16 | 13 | 13 | 1660config ARCH_FORCE_MAX_ORDER 1661 int 1662 default "13" if ARM64_64K_PAGES 1663 default "11" if ARM64_16K_PAGES 1664 default "10" 1665 help 1666 The kernel page allocator limits the size of maximal physically 1667 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1668 defines the maximal power of two of number of pages that can be 1669 allocated as a single contiguous block. This option allows 1670 overriding the default setting when ability to allocate very 1671 large blocks of physically contiguous memory is required. 1672 1673 The maximal size of allocation cannot exceed the size of the 1674 section, so the value of MAX_PAGE_ORDER should satisfy 1675 1676 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1677 1678 Don't change if unsure. 1679 1680config UNMAP_KERNEL_AT_EL0 1681 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1682 default y 1683 help 1684 Speculation attacks against some high-performance processors can 1685 be used to bypass MMU permission checks and leak kernel data to 1686 userspace. This can be defended against by unmapping the kernel 1687 when running in userspace, mapping it back in on exception entry 1688 via a trampoline page in the vector table. 1689 1690 If unsure, say Y. 1691 1692config MITIGATE_SPECTRE_BRANCH_HISTORY 1693 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1694 default y 1695 help 1696 Speculation attacks against some high-performance processors can 1697 make use of branch history to influence future speculation. 1698 When taking an exception from user-space, a sequence of branches 1699 or a firmware call overwrites the branch history. 1700 1701config RODATA_FULL_DEFAULT_ENABLED 1702 bool "Apply r/o permissions of VM areas also to their linear aliases" 1703 default y 1704 help 1705 Apply read-only attributes of VM areas to the linear alias of 1706 the backing pages as well. This prevents code or read-only data 1707 from being modified (inadvertently or intentionally) via another 1708 mapping of the same memory page. This additional enhancement can 1709 be turned off at runtime by passing rodata=[off|on] (and turned on 1710 with rodata=full if this option is set to 'n') 1711 1712 This requires the linear region to be mapped down to pages, 1713 which may adversely affect performance in some cases. 1714 1715config ARM64_SW_TTBR0_PAN 1716 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1717 depends on !KCSAN 1718 select ARM64_PAN 1719 help 1720 Enabling this option prevents the kernel from accessing 1721 user-space memory directly by pointing TTBR0_EL1 to a reserved 1722 zeroed area and reserved ASID. The user access routines 1723 restore the valid TTBR0_EL1 temporarily. 1724 1725config ARM64_TAGGED_ADDR_ABI 1726 bool "Enable the tagged user addresses syscall ABI" 1727 default y 1728 help 1729 When this option is enabled, user applications can opt in to a 1730 relaxed ABI via prctl() allowing tagged addresses to be passed 1731 to system calls as pointer arguments. For details, see 1732 Documentation/arch/arm64/tagged-address-abi.rst. 1733 1734menuconfig COMPAT 1735 bool "Kernel support for 32-bit EL0" 1736 depends on ARM64_4K_PAGES || EXPERT 1737 select HAVE_UID16 1738 select OLD_SIGSUSPEND3 1739 select COMPAT_OLD_SIGACTION 1740 help 1741 This option enables support for a 32-bit EL0 running under a 64-bit 1742 kernel at EL1. AArch32-specific components such as system calls, 1743 the user helper functions, VFP support and the ptrace interface are 1744 handled appropriately by the kernel. 1745 1746 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1747 that you will only be able to execute AArch32 binaries that were compiled 1748 with page size aligned segments. 1749 1750 If you want to execute 32-bit userspace applications, say Y. 1751 1752if COMPAT 1753 1754config KUSER_HELPERS 1755 bool "Enable kuser helpers page for 32-bit applications" 1756 default y 1757 help 1758 Warning: disabling this option may break 32-bit user programs. 1759 1760 Provide kuser helpers to compat tasks. The kernel provides 1761 helper code to userspace in read only form at a fixed location 1762 to allow userspace to be independent of the CPU type fitted to 1763 the system. This permits binaries to be run on ARMv4 through 1764 to ARMv8 without modification. 1765 1766 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1767 1768 However, the fixed address nature of these helpers can be used 1769 by ROP (return orientated programming) authors when creating 1770 exploits. 1771 1772 If all of the binaries and libraries which run on your platform 1773 are built specifically for your platform, and make no use of 1774 these helpers, then you can turn this option off to hinder 1775 such exploits. However, in that case, if a binary or library 1776 relying on those helpers is run, it will not function correctly. 1777 1778 Say N here only if you are absolutely certain that you do not 1779 need these helpers; otherwise, the safe option is to say Y. 1780 1781config COMPAT_VDSO 1782 bool "Enable vDSO for 32-bit applications" 1783 depends on !CPU_BIG_ENDIAN 1784 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1785 select GENERIC_COMPAT_VDSO 1786 default y 1787 help 1788 Place in the process address space of 32-bit applications an 1789 ELF shared object providing fast implementations of gettimeofday 1790 and clock_gettime. 1791 1792 You must have a 32-bit build of glibc 2.22 or later for programs 1793 to seamlessly take advantage of this. 1794 1795config THUMB2_COMPAT_VDSO 1796 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1797 depends on COMPAT_VDSO 1798 default y 1799 help 1800 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1801 otherwise with '-marm'. 1802 1803config COMPAT_ALIGNMENT_FIXUPS 1804 bool "Fix up misaligned multi-word loads and stores in user space" 1805 1806menuconfig ARMV8_DEPRECATED 1807 bool "Emulate deprecated/obsolete ARMv8 instructions" 1808 depends on SYSCTL 1809 help 1810 Legacy software support may require certain instructions 1811 that have been deprecated or obsoleted in the architecture. 1812 1813 Enable this config to enable selective emulation of these 1814 features. 1815 1816 If unsure, say Y 1817 1818if ARMV8_DEPRECATED 1819 1820config SWP_EMULATION 1821 bool "Emulate SWP/SWPB instructions" 1822 help 1823 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1824 they are always undefined. Say Y here to enable software 1825 emulation of these instructions for userspace using LDXR/STXR. 1826 This feature can be controlled at runtime with the abi.swp 1827 sysctl which is disabled by default. 1828 1829 In some older versions of glibc [<=2.8] SWP is used during futex 1830 trylock() operations with the assumption that the code will not 1831 be preempted. This invalid assumption may be more likely to fail 1832 with SWP emulation enabled, leading to deadlock of the user 1833 application. 1834 1835 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1836 on an external transaction monitoring block called a global 1837 monitor to maintain update atomicity. If your system does not 1838 implement a global monitor, this option can cause programs that 1839 perform SWP operations to uncached memory to deadlock. 1840 1841 If unsure, say Y 1842 1843config CP15_BARRIER_EMULATION 1844 bool "Emulate CP15 Barrier instructions" 1845 help 1846 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1847 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1848 strongly recommended to use the ISB, DSB, and DMB 1849 instructions instead. 1850 1851 Say Y here to enable software emulation of these 1852 instructions for AArch32 userspace code. When this option is 1853 enabled, CP15 barrier usage is traced which can help 1854 identify software that needs updating. This feature can be 1855 controlled at runtime with the abi.cp15_barrier sysctl. 1856 1857 If unsure, say Y 1858 1859config SETEND_EMULATION 1860 bool "Emulate SETEND instruction" 1861 help 1862 The SETEND instruction alters the data-endianness of the 1863 AArch32 EL0, and is deprecated in ARMv8. 1864 1865 Say Y here to enable software emulation of the instruction 1866 for AArch32 userspace code. This feature can be controlled 1867 at runtime with the abi.setend sysctl. 1868 1869 Note: All the cpus on the system must have mixed endian support at EL0 1870 for this feature to be enabled. If a new CPU - which doesn't support mixed 1871 endian - is hotplugged in after this feature has been enabled, there could 1872 be unexpected results in the applications. 1873 1874 If unsure, say Y 1875endif # ARMV8_DEPRECATED 1876 1877endif # COMPAT 1878 1879menu "ARMv8.1 architectural features" 1880 1881config ARM64_HW_AFDBM 1882 bool "Support for hardware updates of the Access and Dirty page flags" 1883 default y 1884 help 1885 The ARMv8.1 architecture extensions introduce support for 1886 hardware updates of the access and dirty information in page 1887 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1888 capable processors, accesses to pages with PTE_AF cleared will 1889 set this bit instead of raising an access flag fault. 1890 Similarly, writes to read-only pages with the DBM bit set will 1891 clear the read-only bit (AP[2]) instead of raising a 1892 permission fault. 1893 1894 Kernels built with this configuration option enabled continue 1895 to work on pre-ARMv8.1 hardware and the performance impact is 1896 minimal. If unsure, say Y. 1897 1898config ARM64_PAN 1899 bool "Enable support for Privileged Access Never (PAN)" 1900 default y 1901 help 1902 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1903 prevents the kernel or hypervisor from accessing user-space (EL0) 1904 memory directly. 1905 1906 Choosing this option will cause any unprotected (not using 1907 copy_to_user et al) memory access to fail with a permission fault. 1908 1909 The feature is detected at runtime, and will remain as a 'nop' 1910 instruction if the cpu does not implement the feature. 1911 1912config ARM64_LSE_ATOMICS 1913 bool 1914 default ARM64_USE_LSE_ATOMICS 1915 1916config ARM64_USE_LSE_ATOMICS 1917 bool "Atomic instructions" 1918 default y 1919 help 1920 As part of the Large System Extensions, ARMv8.1 introduces new 1921 atomic instructions that are designed specifically to scale in 1922 very large systems. 1923 1924 Say Y here to make use of these instructions for the in-kernel 1925 atomic routines. This incurs a small overhead on CPUs that do 1926 not support these instructions. 1927 1928endmenu # "ARMv8.1 architectural features" 1929 1930menu "ARMv8.2 architectural features" 1931 1932config ARM64_PMEM 1933 bool "Enable support for persistent memory" 1934 select ARCH_HAS_PMEM_API 1935 select ARCH_HAS_UACCESS_FLUSHCACHE 1936 help 1937 Say Y to enable support for the persistent memory API based on the 1938 ARMv8.2 DCPoP feature. 1939 1940 The feature is detected at runtime, and the kernel will use DC CVAC 1941 operations if DC CVAP is not supported (following the behaviour of 1942 DC CVAP itself if the system does not define a point of persistence). 1943 1944config ARM64_RAS_EXTN 1945 bool "Enable support for RAS CPU Extensions" 1946 default y 1947 help 1948 CPUs that support the Reliability, Availability and Serviceability 1949 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1950 errors, classify them and report them to software. 1951 1952 On CPUs with these extensions system software can use additional 1953 barriers to determine if faults are pending and read the 1954 classification from a new set of registers. 1955 1956 Selecting this feature will allow the kernel to use these barriers 1957 and access the new registers if the system supports the extension. 1958 Platform RAS features may additionally depend on firmware support. 1959 1960config ARM64_CNP 1961 bool "Enable support for Common Not Private (CNP) translations" 1962 default y 1963 help 1964 Common Not Private (CNP) allows translation table entries to 1965 be shared between different PEs in the same inner shareable 1966 domain, so the hardware can use this fact to optimise the 1967 caching of such entries in the TLB. 1968 1969 Selecting this option allows the CNP feature to be detected 1970 at runtime, and does not affect PEs that do not implement 1971 this feature. 1972 1973endmenu # "ARMv8.2 architectural features" 1974 1975menu "ARMv8.3 architectural features" 1976 1977config ARM64_PTR_AUTH 1978 bool "Enable support for pointer authentication" 1979 default y 1980 help 1981 Pointer authentication (part of the ARMv8.3 Extensions) provides 1982 instructions for signing and authenticating pointers against secret 1983 keys, which can be used to mitigate Return Oriented Programming (ROP) 1984 and other attacks. 1985 1986 This option enables these instructions at EL0 (i.e. for userspace). 1987 Choosing this option will cause the kernel to initialise secret keys 1988 for each process at exec() time, with these keys being 1989 context-switched along with the process. 1990 1991 The feature is detected at runtime. If the feature is not present in 1992 hardware it will not be advertised to userspace/KVM guest nor will it 1993 be enabled. 1994 1995 If the feature is present on the boot CPU but not on a late CPU, then 1996 the late CPU will be parked. Also, if the boot CPU does not have 1997 address auth and the late CPU has then the late CPU will still boot 1998 but with the feature disabled. On such a system, this option should 1999 not be selected. 2000 2001config ARM64_PTR_AUTH_KERNEL 2002 bool "Use pointer authentication for kernel" 2003 default y 2004 depends on ARM64_PTR_AUTH 2005 # Modern compilers insert a .note.gnu.property section note for PAC 2006 # which is only understood by binutils starting with version 2.33.1. 2007 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 2008 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 2009 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2010 help 2011 If the compiler supports the -mbranch-protection or 2012 -msign-return-address flag (e.g. GCC 7 or later), then this option 2013 will cause the kernel itself to be compiled with return address 2014 protection. In this case, and if the target hardware is known to 2015 support pointer authentication, then CONFIG_STACKPROTECTOR can be 2016 disabled with minimal loss of protection. 2017 2018 This feature works with FUNCTION_GRAPH_TRACER option only if 2019 DYNAMIC_FTRACE_WITH_ARGS is enabled. 2020 2021config CC_HAS_BRANCH_PROT_PAC_RET 2022 # GCC 9 or later, clang 8 or later 2023 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 2024 2025config AS_HAS_CFI_NEGATE_RA_STATE 2026 # binutils 2.34+ 2027 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2028 2029endmenu # "ARMv8.3 architectural features" 2030 2031menu "ARMv8.4 architectural features" 2032 2033config ARM64_AMU_EXTN 2034 bool "Enable support for the Activity Monitors Unit CPU extension" 2035 default y 2036 help 2037 The activity monitors extension is an optional extension introduced 2038 by the ARMv8.4 CPU architecture. This enables support for version 1 2039 of the activity monitors architecture, AMUv1. 2040 2041 To enable the use of this extension on CPUs that implement it, say Y. 2042 2043 Note that for architectural reasons, firmware _must_ implement AMU 2044 support when running on CPUs that present the activity monitors 2045 extension. The required support is present in: 2046 * Version 1.5 and later of the ARM Trusted Firmware 2047 2048 For kernels that have this configuration enabled but boot with broken 2049 firmware, you may need to say N here until the firmware is fixed. 2050 Otherwise you may experience firmware panics or lockups when 2051 accessing the counter registers. Even if you are not observing these 2052 symptoms, the values returned by the register reads might not 2053 correctly reflect reality. Most commonly, the value read will be 0, 2054 indicating that the counter is not enabled. 2055 2056config ARM64_TLB_RANGE 2057 bool "Enable support for tlbi range feature" 2058 default y 2059 help 2060 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2061 range of input addresses. 2062 2063endmenu # "ARMv8.4 architectural features" 2064 2065menu "ARMv8.5 architectural features" 2066 2067config AS_HAS_ARMV8_5 2068 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2069 2070config ARM64_BTI 2071 bool "Branch Target Identification support" 2072 default y 2073 help 2074 Branch Target Identification (part of the ARMv8.5 Extensions) 2075 provides a mechanism to limit the set of locations to which computed 2076 branch instructions such as BR or BLR can jump. 2077 2078 To make use of BTI on CPUs that support it, say Y. 2079 2080 BTI is intended to provide complementary protection to other control 2081 flow integrity protection mechanisms, such as the Pointer 2082 authentication mechanism provided as part of the ARMv8.3 Extensions. 2083 For this reason, it does not make sense to enable this option without 2084 also enabling support for pointer authentication. Thus, when 2085 enabling this option you should also select ARM64_PTR_AUTH=y. 2086 2087 Userspace binaries must also be specifically compiled to make use of 2088 this mechanism. If you say N here or the hardware does not support 2089 BTI, such binaries can still run, but you get no additional 2090 enforcement of branch destinations. 2091 2092config ARM64_BTI_KERNEL 2093 bool "Use Branch Target Identification for kernel" 2094 default y 2095 depends on ARM64_BTI 2096 depends on ARM64_PTR_AUTH_KERNEL 2097 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2098 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2099 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2100 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2101 depends on !CC_IS_GCC 2102 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2103 help 2104 Build the kernel with Branch Target Identification annotations 2105 and enable enforcement of this for kernel code. When this option 2106 is enabled and the system supports BTI all kernel code including 2107 modular code must have BTI enabled. 2108 2109config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2110 # GCC 9 or later, clang 8 or later 2111 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2112 2113config ARM64_E0PD 2114 bool "Enable support for E0PD" 2115 default y 2116 help 2117 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2118 that EL0 accesses made via TTBR1 always fault in constant time, 2119 providing similar benefits to KASLR as those provided by KPTI, but 2120 with lower overhead and without disrupting legitimate access to 2121 kernel memory such as SPE. 2122 2123 This option enables E0PD for TTBR1 where available. 2124 2125config ARM64_AS_HAS_MTE 2126 # Initial support for MTE went in binutils 2.32.0, checked with 2127 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2128 # as a late addition to the final architecture spec (LDGM/STGM) 2129 # is only supported in the newer 2.32.x and 2.33 binutils 2130 # versions, hence the extra "stgm" instruction check below. 2131 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2132 2133config ARM64_MTE 2134 bool "Memory Tagging Extension support" 2135 default y 2136 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2137 depends on AS_HAS_ARMV8_5 2138 # Required for tag checking in the uaccess routines 2139 select ARM64_PAN 2140 select ARCH_HAS_SUBPAGE_FAULTS 2141 select ARCH_USES_HIGH_VMA_FLAGS 2142 select ARCH_USES_PG_ARCH_2 2143 select ARCH_USES_PG_ARCH_3 2144 help 2145 Memory Tagging (part of the ARMv8.5 Extensions) provides 2146 architectural support for run-time, always-on detection of 2147 various classes of memory error to aid with software debugging 2148 to eliminate vulnerabilities arising from memory-unsafe 2149 languages. 2150 2151 This option enables the support for the Memory Tagging 2152 Extension at EL0 (i.e. for userspace). 2153 2154 Selecting this option allows the feature to be detected at 2155 runtime. Any secondary CPU not implementing this feature will 2156 not be allowed a late bring-up. 2157 2158 Userspace binaries that want to use this feature must 2159 explicitly opt in. The mechanism for the userspace is 2160 described in: 2161 2162 Documentation/arch/arm64/memory-tagging-extension.rst. 2163 2164endmenu # "ARMv8.5 architectural features" 2165 2166menu "ARMv8.7 architectural features" 2167 2168config ARM64_EPAN 2169 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2170 default y 2171 depends on ARM64_PAN 2172 help 2173 Enhanced Privileged Access Never (EPAN) allows Privileged 2174 Access Never to be used with Execute-only mappings. 2175 2176 The feature is detected at runtime, and will remain disabled 2177 if the cpu does not implement the feature. 2178endmenu # "ARMv8.7 architectural features" 2179 2180config AS_HAS_MOPS 2181 def_bool $(as-instr,.arch_extension mops) 2182 2183menu "ARMv8.9 architectural features" 2184 2185config ARM64_POE 2186 prompt "Permission Overlay Extension" 2187 def_bool y 2188 select ARCH_USES_HIGH_VMA_FLAGS 2189 select ARCH_HAS_PKEYS 2190 help 2191 The Permission Overlay Extension is used to implement Memory 2192 Protection Keys. Memory Protection Keys provides a mechanism for 2193 enforcing page-based protections, but without requiring modification 2194 of the page tables when an application changes protection domains. 2195 2196 For details, see Documentation/core-api/protection-keys.rst 2197 2198 If unsure, say y. 2199 2200config ARCH_PKEY_BITS 2201 int 2202 default 3 2203 2204config ARM64_HAFT 2205 bool "Support for Hardware managed Access Flag for Table Descriptors" 2206 depends on ARM64_HW_AFDBM 2207 default y 2208 help 2209 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2210 Flag for Table descriptors. When enabled an architectural executed 2211 memory access will update the Access Flag in each Table descriptor 2212 which is accessed during the translation table walk and for which 2213 the Access Flag is 0. The Access Flag of the Table descriptor use 2214 the same bit of PTE_AF. 2215 2216 The feature will only be enabled if all the CPUs in the system 2217 support this feature. If unsure, say Y. 2218 2219endmenu # "ARMv8.9 architectural features" 2220 2221menu "v9.4 architectural features" 2222 2223config ARM64_GCS 2224 bool "Enable support for Guarded Control Stack (GCS)" 2225 default y 2226 select ARCH_HAS_USER_SHADOW_STACK 2227 select ARCH_USES_HIGH_VMA_FLAGS 2228 depends on !UPROBES 2229 help 2230 Guarded Control Stack (GCS) provides support for a separate 2231 stack with restricted access which contains only return 2232 addresses. This can be used to harden against some attacks 2233 by comparing return address used by the program with what is 2234 stored in the GCS, and may also be used to efficiently obtain 2235 the call stack for applications such as profiling. 2236 2237 The feature is detected at runtime, and will remain disabled 2238 if the system does not implement the feature. 2239 2240endmenu # "v9.4 architectural features" 2241 2242config ARM64_SVE 2243 bool "ARM Scalable Vector Extension support" 2244 default y 2245 help 2246 The Scalable Vector Extension (SVE) is an extension to the AArch64 2247 execution state which complements and extends the SIMD functionality 2248 of the base architecture to support much larger vectors and to enable 2249 additional vectorisation opportunities. 2250 2251 To enable use of this extension on CPUs that implement it, say Y. 2252 2253 On CPUs that support the SVE2 extensions, this option will enable 2254 those too. 2255 2256 Note that for architectural reasons, firmware _must_ implement SVE 2257 support when running on SVE capable hardware. The required support 2258 is present in: 2259 2260 * version 1.5 and later of the ARM Trusted Firmware 2261 * the AArch64 boot wrapper since commit 5e1261e08abf 2262 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2263 2264 For other firmware implementations, consult the firmware documentation 2265 or vendor. 2266 2267 If you need the kernel to boot on SVE-capable hardware with broken 2268 firmware, you may need to say N here until you get your firmware 2269 fixed. Otherwise, you may experience firmware panics or lockups when 2270 booting the kernel. If unsure and you are not observing these 2271 symptoms, you should assume that it is safe to say Y. 2272 2273config ARM64_SME 2274 bool "ARM Scalable Matrix Extension support" 2275 default y 2276 depends on ARM64_SVE 2277 help 2278 The Scalable Matrix Extension (SME) is an extension to the AArch64 2279 execution state which utilises a substantial subset of the SVE 2280 instruction set, together with the addition of new architectural 2281 register state capable of holding two dimensional matrix tiles to 2282 enable various matrix operations. 2283 2284config ARM64_PSEUDO_NMI 2285 bool "Support for NMI-like interrupts" 2286 select ARM_GIC_V3 2287 help 2288 Adds support for mimicking Non-Maskable Interrupts through the use of 2289 GIC interrupt priority. This support requires version 3 or later of 2290 ARM GIC. 2291 2292 This high priority configuration for interrupts needs to be 2293 explicitly enabled by setting the kernel parameter 2294 "irqchip.gicv3_pseudo_nmi" to 1. 2295 2296 If unsure, say N 2297 2298if ARM64_PSEUDO_NMI 2299config ARM64_DEBUG_PRIORITY_MASKING 2300 bool "Debug interrupt priority masking" 2301 help 2302 This adds runtime checks to functions enabling/disabling 2303 interrupts when using priority masking. The additional checks verify 2304 the validity of ICC_PMR_EL1 when calling concerned functions. 2305 2306 If unsure, say N 2307endif # ARM64_PSEUDO_NMI 2308 2309config RELOCATABLE 2310 bool "Build a relocatable kernel image" if EXPERT 2311 select ARCH_HAS_RELR 2312 default y 2313 help 2314 This builds the kernel as a Position Independent Executable (PIE), 2315 which retains all relocation metadata required to relocate the 2316 kernel binary at runtime to a different virtual address than the 2317 address it was linked at. 2318 Since AArch64 uses the RELA relocation format, this requires a 2319 relocation pass at runtime even if the kernel is loaded at the 2320 same address it was linked at. 2321 2322config RANDOMIZE_BASE 2323 bool "Randomize the address of the kernel image" 2324 select RELOCATABLE 2325 help 2326 Randomizes the virtual address at which the kernel image is 2327 loaded, as a security feature that deters exploit attempts 2328 relying on knowledge of the location of kernel internals. 2329 2330 It is the bootloader's job to provide entropy, by passing a 2331 random u64 value in /chosen/kaslr-seed at kernel entry. 2332 2333 When booting via the UEFI stub, it will invoke the firmware's 2334 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2335 to the kernel proper. In addition, it will randomise the physical 2336 location of the kernel Image as well. 2337 2338 If unsure, say N. 2339 2340config RANDOMIZE_MODULE_REGION_FULL 2341 bool "Randomize the module region over a 2 GB range" 2342 depends on RANDOMIZE_BASE 2343 default y 2344 help 2345 Randomizes the location of the module region inside a 2 GB window 2346 covering the core kernel. This way, it is less likely for modules 2347 to leak information about the location of core kernel data structures 2348 but it does imply that function calls between modules and the core 2349 kernel will need to be resolved via veneers in the module PLT. 2350 2351 When this option is not set, the module region will be randomized over 2352 a limited range that contains the [_stext, _etext] interval of the 2353 core kernel, so branch relocations are almost always in range unless 2354 the region is exhausted. In this particular case of region 2355 exhaustion, modules might be able to fall back to a larger 2GB area. 2356 2357config CC_HAVE_STACKPROTECTOR_SYSREG 2358 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2359 2360config STACKPROTECTOR_PER_TASK 2361 def_bool y 2362 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2363 2364config UNWIND_PATCH_PAC_INTO_SCS 2365 bool "Enable shadow call stack dynamically using code patching" 2366 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2367 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2368 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2369 depends on SHADOW_CALL_STACK 2370 select UNWIND_TABLES 2371 select DYNAMIC_SCS 2372 2373config ARM64_CONTPTE 2374 bool "Contiguous PTE mappings for user memory" if EXPERT 2375 depends on TRANSPARENT_HUGEPAGE 2376 default y 2377 help 2378 When enabled, user mappings are configured using the PTE contiguous 2379 bit, for any mappings that meet the size and alignment requirements. 2380 This reduces TLB pressure and improves performance. 2381 2382endmenu # "Kernel Features" 2383 2384menu "Boot options" 2385 2386config ARM64_ACPI_PARKING_PROTOCOL 2387 bool "Enable support for the ARM64 ACPI parking protocol" 2388 depends on ACPI 2389 help 2390 Enable support for the ARM64 ACPI parking protocol. If disabled 2391 the kernel will not allow booting through the ARM64 ACPI parking 2392 protocol even if the corresponding data is present in the ACPI 2393 MADT table. 2394 2395config CMDLINE 2396 string "Default kernel command string" 2397 default "" 2398 help 2399 Provide a set of default command-line options at build time by 2400 entering them here. As a minimum, you should specify the the 2401 root device (e.g. root=/dev/nfs). 2402 2403choice 2404 prompt "Kernel command line type" 2405 depends on CMDLINE != "" 2406 default CMDLINE_FROM_BOOTLOADER 2407 help 2408 Choose how the kernel will handle the provided default kernel 2409 command line string. 2410 2411config CMDLINE_FROM_BOOTLOADER 2412 bool "Use bootloader kernel arguments if available" 2413 help 2414 Uses the command-line options passed by the boot loader. If 2415 the boot loader doesn't provide any, the default kernel command 2416 string provided in CMDLINE will be used. 2417 2418config CMDLINE_FORCE 2419 bool "Always use the default kernel command string" 2420 help 2421 Always use the default kernel command string, even if the boot 2422 loader passes other arguments to the kernel. 2423 This is useful if you cannot or don't want to change the 2424 command-line options your boot loader passes to the kernel. 2425 2426endchoice 2427 2428config EFI_STUB 2429 bool 2430 2431config EFI 2432 bool "UEFI runtime support" 2433 depends on OF && !CPU_BIG_ENDIAN 2434 depends on KERNEL_MODE_NEON 2435 select ARCH_SUPPORTS_ACPI 2436 select LIBFDT 2437 select UCS2_STRING 2438 select EFI_PARAMS_FROM_FDT 2439 select EFI_RUNTIME_WRAPPERS 2440 select EFI_STUB 2441 select EFI_GENERIC_STUB 2442 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2443 default y 2444 help 2445 This option provides support for runtime services provided 2446 by UEFI firmware (such as non-volatile variables, realtime 2447 clock, and platform reset). A UEFI stub is also provided to 2448 allow the kernel to be booted as an EFI application. This 2449 is only useful on systems that have UEFI firmware. 2450 2451config COMPRESSED_INSTALL 2452 bool "Install compressed image by default" 2453 help 2454 This makes the regular "make install" install the compressed 2455 image we built, not the legacy uncompressed one. 2456 2457 You can check that a compressed image works for you by doing 2458 "make zinstall" first, and verifying that everything is fine 2459 in your environment before making "make install" do this for 2460 you. 2461 2462config DMI 2463 bool "Enable support for SMBIOS (DMI) tables" 2464 depends on EFI 2465 default y 2466 help 2467 This enables SMBIOS/DMI feature for systems. 2468 2469 This option is only useful on systems that have UEFI firmware. 2470 However, even with this option, the resultant kernel should 2471 continue to boot on existing non-UEFI platforms. 2472 2473endmenu # "Boot options" 2474 2475menu "Power management options" 2476 2477source "kernel/power/Kconfig" 2478 2479config ARCH_HIBERNATION_POSSIBLE 2480 def_bool y 2481 depends on CPU_PM 2482 2483config ARCH_HIBERNATION_HEADER 2484 def_bool y 2485 depends on HIBERNATION 2486 2487config ARCH_SUSPEND_POSSIBLE 2488 def_bool y 2489 2490endmenu # "Power management options" 2491 2492menu "CPU Power Management" 2493 2494source "drivers/cpuidle/Kconfig" 2495 2496source "drivers/cpufreq/Kconfig" 2497 2498endmenu # "CPU Power Management" 2499 2500source "drivers/acpi/Kconfig" 2501 2502source "arch/arm64/kvm/Kconfig" 2503 2504source "kernel/livepatch/Kconfig" 2505