1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CC_PLATFORM 23 select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_LAZY_MMU_MODE 38 select ARCH_HAS_MEMBARRIER_SYNC_CORE 39 select ARCH_HAS_MEM_ENCRYPT 40 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS 41 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 42 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 43 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 44 select ARCH_HAS_PREEMPT_LAZY 45 select ARCH_HAS_PTDUMP 46 select ARCH_HAS_PTE_SPECIAL 47 select ARCH_HAS_HW_PTE_YOUNG 48 select ARCH_HAS_SETUP_DMA_OPS 49 select ARCH_HAS_SET_DIRECT_MAP 50 select ARCH_HAS_SET_MEMORY 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_SYSCALL_WRAPPER 58 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 59 select ARCH_HAS_ZONE_DMA_SET if EXPERT 60 select ARCH_HAVE_ELF_PROT 61 select ARCH_HAVE_NMI_SAFE_CMPXCHG 62 select ARCH_HAVE_TRACE_MMIO_ACCESS 63 select ARCH_KEEP_MEMBLOCK 64 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 65 select ARCH_USE_CMPXCHG_LOCKREF 66 select ARCH_USE_GNU_PROPERTY 67 select ARCH_USE_MEMTEST 68 select ARCH_USE_QUEUED_RWLOCKS 69 select ARCH_USE_QUEUED_SPINLOCKS 70 select ARCH_USE_SYM_ANNOTATIONS 71 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 72 select ARCH_SUPPORTS_HUGETLBFS 73 select ARCH_SUPPORTS_MEMORY_FAILURE 74 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 75 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 76 select ARCH_SUPPORTS_LTO_CLANG_THIN 77 select ARCH_SUPPORTS_CFI 78 select ARCH_SUPPORTS_ATOMIC_RMW 79 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 80 select ARCH_SUPPORTS_NUMA_BALANCING 81 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 82 select ARCH_SUPPORTS_PER_VMA_LOCK 83 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 84 select ARCH_SUPPORTS_RT 85 select ARCH_SUPPORTS_SCHED_SMT 86 select ARCH_SUPPORTS_SCHED_CLUSTER 87 select ARCH_SUPPORTS_SCHED_MC 88 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 89 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 90 select ARCH_WANT_DEFAULT_BPF_JIT 91 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 92 select ARCH_WANT_FRAME_POINTERS 93 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 94 select ARCH_WANT_LD_ORPHAN_WARN 95 select ARCH_WANTS_EXECMEM_LATE 96 select ARCH_WANTS_NO_INSTR 97 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 98 select ARCH_HAS_UBSAN 99 select ARM_AMBA 100 select ARM_ARCH_TIMER 101 select ARM_GIC 102 select AUDIT_ARCH_COMPAT_GENERIC 103 select ARM_GIC_V2M if PCI 104 select ARM_GIC_V3 105 select ARM_GIC_V3_ITS if PCI 106 select ARM_GIC_V5 107 select ARM_PSCI_FW 108 select BUILDTIME_TABLE_SORT 109 select CLONE_BACKWARDS 110 select COMMON_CLK 111 select CPU_PM if (SUSPEND || CPU_IDLE) 112 select CPUMASK_OFFSTACK if NR_CPUS > 256 113 select DCACHE_WORD_ACCESS 114 select HAVE_EXTRA_IPI_TRACEPOINTS 115 select DYNAMIC_FTRACE if FUNCTION_TRACER 116 select DMA_BOUNCE_UNALIGNED_KMALLOC 117 select DMA_DIRECT_REMAP 118 select EDAC_SUPPORT 119 select FRAME_POINTER 120 select FUNCTION_ALIGNMENT_4B 121 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 122 select GENERIC_ALLOCATOR 123 select GENERIC_ARCH_TOPOLOGY 124 select GENERIC_CLOCKEVENTS_BROADCAST 125 select GENERIC_CPU_AUTOPROBE 126 select GENERIC_CPU_CACHE_MAINTENANCE 127 select GENERIC_CPU_DEVICES 128 select GENERIC_CPU_VULNERABILITIES 129 select GENERIC_EARLY_IOREMAP 130 select GENERIC_IDLE_POLL_SETUP 131 select GENERIC_IOREMAP 132 select GENERIC_IRQ_ENTRY 133 select GENERIC_IRQ_IPI 134 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 135 select GENERIC_IRQ_PROBE 136 select GENERIC_IRQ_SHOW 137 select GENERIC_IRQ_SHOW_LEVEL 138 select GENERIC_LIB_DEVMEM_IS_ALLOWED 139 select GENERIC_PCI_IOMAP 140 select GENERIC_SCHED_CLOCK 141 select GENERIC_SMP_IDLE_THREAD 142 select GENERIC_TIME_VSYSCALL 143 select GENERIC_GETTIMEOFDAY 144 select HARDIRQS_SW_RESEND 145 select HAS_IOPORT 146 select HAVE_MOVE_PMD 147 select HAVE_MOVE_PUD 148 select HAVE_PCI 149 select HAVE_ACPI_APEI if (ACPI && EFI) 150 select HAVE_ALIGNED_STRUCT_PAGE 151 select HAVE_ARCH_AUDITSYSCALL 152 select HAVE_ARCH_BITREVERSE 153 select HAVE_ARCH_COMPILER_H 154 select HAVE_ARCH_HUGE_VMALLOC 155 select HAVE_ARCH_HUGE_VMAP 156 select HAVE_ARCH_JUMP_LABEL 157 select HAVE_ARCH_JUMP_LABEL_RELATIVE 158 select HAVE_ARCH_KASAN 159 select HAVE_ARCH_KASAN_VMALLOC 160 select HAVE_ARCH_KASAN_SW_TAGS 161 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 162 # Some instrumentation may be unsound, hence EXPERT 163 select HAVE_ARCH_KCSAN if EXPERT 164 select HAVE_ARCH_KFENCE 165 select HAVE_ARCH_KGDB 166 select HAVE_ARCH_KSTACK_ERASE 167 select HAVE_ARCH_MMAP_RND_BITS 168 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 169 select HAVE_ARCH_PREL32_RELOCATIONS 170 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 171 select HAVE_ARCH_SECCOMP_FILTER 172 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 173 select HAVE_ARCH_TRACEHOOK 174 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 175 select HAVE_ARCH_VMAP_STACK 176 select HAVE_ARM_SMCCC 177 select HAVE_ASM_MODVERSIONS 178 select HAVE_EBPF_JIT 179 select HAVE_C_RECORDMCOUNT 180 select HAVE_CMPXCHG_DOUBLE 181 select HAVE_CMPXCHG_LOCAL 182 select HAVE_CONTEXT_TRACKING_USER 183 select HAVE_DEBUG_KMEMLEAK 184 select HAVE_DMA_CONTIGUOUS 185 select HAVE_DYNAMIC_FTRACE 186 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 187 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 188 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 189 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 190 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 191 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 192 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI && \ 193 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 194 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 195 if DYNAMIC_FTRACE_WITH_ARGS 196 select HAVE_SAMPLE_FTRACE_DIRECT 197 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 198 select HAVE_BUILDTIME_MCOUNT_SORT 199 select HAVE_EFFICIENT_UNALIGNED_ACCESS 200 select HAVE_GUP_FAST 201 select HAVE_FTRACE_GRAPH_FUNC 202 select HAVE_FUNCTION_TRACER 203 select HAVE_FUNCTION_ERROR_INJECTION 204 select HAVE_FUNCTION_GRAPH_FREGS 205 select HAVE_FUNCTION_GRAPH_TRACER 206 select HAVE_GCC_PLUGINS 207 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 208 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 209 select HAVE_HW_BREAKPOINT if PERF_EVENTS 210 select HAVE_IOREMAP_PROT 211 select HAVE_IRQ_TIME_ACCOUNTING 212 select HAVE_LIVEPATCH 213 select HAVE_MOD_ARCH_SPECIFIC 214 select HAVE_NMI 215 select HAVE_PERF_EVENTS 216 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 217 select HAVE_PERF_REGS 218 select HAVE_PERF_USER_STACK_DUMP 219 select HAVE_PREEMPT_DYNAMIC_KEY 220 select HAVE_REGS_AND_STACK_ACCESS_API 221 select HAVE_RELIABLE_STACKTRACE 222 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 223 select HAVE_FUNCTION_ARG_ACCESS_API 224 select MMU_GATHER_RCU_TABLE_FREE 225 select HAVE_RSEQ 226 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 227 select HAVE_STACKPROTECTOR 228 select HAVE_STATIC_CALL if CFI 229 select HAVE_SYSCALL_TRACEPOINTS 230 select HAVE_KPROBES 231 select HAVE_KRETPROBES 232 select HAVE_GENERIC_VDSO 233 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 234 select HOTPLUG_SMT if HOTPLUG_CPU 235 select IRQ_DOMAIN 236 select IRQ_FORCED_THREADING 237 select JUMP_LABEL 238 select KASAN_VMALLOC if KASAN 239 select LOCK_MM_AND_FIND_VMA 240 select MODULES_USE_ELF_RELA 241 select NEED_DMA_MAP_STATE 242 select NEED_SG_DMA_LENGTH 243 select OF 244 select OF_EARLY_FLATTREE 245 select PCI_DOMAINS_GENERIC if PCI 246 select PCI_ECAM if (ACPI && PCI) 247 select PCI_SYSCALL if PCI 248 select POWER_RESET 249 select POWER_SUPPLY 250 select SPARSE_IRQ 251 select SWIOTLB 252 select SYSCTL_EXCEPTION_TRACE 253 select THREAD_INFO_IN_TASK 254 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 255 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 256 select TRACE_IRQFLAGS_SUPPORT 257 select TRACE_IRQFLAGS_NMI_SUPPORT 258 select HAVE_SOFTIRQ_ON_OWN_STACK 259 select USER_STACKTRACE_SUPPORT 260 select VDSO_GETRANDOM 261 select VMAP_STACK 262 help 263 ARM 64-bit (AArch64) Linux support. 264 265config RUSTC_SUPPORTS_ARM64 266 def_bool y 267 depends on CPU_LITTLE_ENDIAN 268 269config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 270 def_bool CC_IS_CLANG 271 # https://github.com/ClangBuiltLinux/linux/issues/1507 272 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 273 274config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 275 def_bool CC_IS_GCC 276 depends on $(cc-option,-fpatchable-function-entry=2) 277 278config 64BIT 279 def_bool y 280 281config MMU 282 def_bool y 283 284config ARM64_CONT_PTE_SHIFT 285 int 286 default 5 if PAGE_SIZE_64KB 287 default 7 if PAGE_SIZE_16KB 288 default 4 289 290config ARM64_CONT_PMD_SHIFT 291 int 292 default 5 if PAGE_SIZE_64KB 293 default 5 if PAGE_SIZE_16KB 294 default 4 295 296config ARCH_MMAP_RND_BITS_MIN 297 default 14 if PAGE_SIZE_64KB 298 default 16 if PAGE_SIZE_16KB 299 default 18 300 301# max bits determined by the following formula: 302# VA_BITS - PTDESC_TABLE_SHIFT 303config ARCH_MMAP_RND_BITS_MAX 304 default 19 if ARM64_VA_BITS=36 305 default 24 if ARM64_VA_BITS=39 306 default 27 if ARM64_VA_BITS=42 307 default 30 if ARM64_VA_BITS=47 308 default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES 309 default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES 310 default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) 311 default 14 if ARM64_64K_PAGES 312 default 16 if ARM64_16K_PAGES 313 default 18 314 315config ARCH_MMAP_RND_COMPAT_BITS_MIN 316 default 7 if ARM64_64K_PAGES 317 default 9 if ARM64_16K_PAGES 318 default 11 319 320config ARCH_MMAP_RND_COMPAT_BITS_MAX 321 default 16 322 323config NO_IOPORT_MAP 324 def_bool y if !PCI 325 326config STACKTRACE_SUPPORT 327 def_bool y 328 329config ILLEGAL_POINTER_VALUE 330 hex 331 default 0xdead000000000000 332 333config LOCKDEP_SUPPORT 334 def_bool y 335 336config GENERIC_BUG 337 def_bool y 338 depends on BUG 339 340config GENERIC_BUG_RELATIVE_POINTERS 341 def_bool y 342 depends on GENERIC_BUG 343 344config GENERIC_HWEIGHT 345 def_bool y 346 347config GENERIC_CSUM 348 def_bool y 349 350config GENERIC_CALIBRATE_DELAY 351 def_bool y 352 353config SMP 354 def_bool y 355 356config KERNEL_MODE_NEON 357 def_bool y 358 359config FIX_EARLYCON_MEM 360 def_bool y 361 362config PGTABLE_LEVELS 363 int 364 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 365 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 366 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 367 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 368 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 369 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 370 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 371 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 372 373config ARCH_SUPPORTS_UPROBES 374 def_bool y 375 376config ARCH_PROC_KCORE_TEXT 377 def_bool y 378 379config BROKEN_GAS_INST 380 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 381 382config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 383 bool 384 # Clang's __builtin_return_address() strips the PAC since 12.0.0 385 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 386 default y if CC_IS_CLANG 387 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 388 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 389 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 390 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 391 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 392 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 393 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 394 default n 395 396config KASAN_SHADOW_OFFSET 397 hex 398 depends on KASAN_GENERIC || KASAN_SW_TAGS 399 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 400 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 401 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 402 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 403 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 404 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 405 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 406 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 407 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 408 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 409 default 0xffffffffffffffff 410 411config UNWIND_TABLES 412 bool 413 414source "arch/arm64/Kconfig.platforms" 415 416menu "Kernel Features" 417 418menu "ARM errata workarounds via the alternatives framework" 419 420config AMPERE_ERRATUM_AC03_CPU_38 421 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 422 default y 423 help 424 This option adds an alternative code sequence to work around Ampere 425 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 426 427 The affected design reports FEAT_HAFDBS as not implemented in 428 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 429 as required by the architecture. The unadvertised HAFDBS 430 implementation suffers from an additional erratum where hardware 431 A/D updates can occur after a PTE has been marked invalid. 432 433 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 434 which avoids enabling unadvertised hardware Access Flag management 435 at stage-2. 436 437 If unsure, say Y. 438 439config AMPERE_ERRATUM_AC04_CPU_23 440 bool "AmpereOne: AC04_CPU_23: Failure to synchronize writes to HCR_EL2 may corrupt address translations." 441 default y 442 help 443 This option adds an alternative code sequence to work around Ampere 444 errata AC04_CPU_23 on AmpereOne. 445 446 Updates to HCR_EL2 can rarely corrupt simultaneous translations for 447 data addresses initiated by load/store instructions. Only 448 instruction initiated translations are vulnerable, not translations 449 from prefetches for example. A DSB before the store to HCR_EL2 is 450 sufficient to prevent older instructions from hitting the window 451 for corruption, and an ISB after is sufficient to prevent younger 452 instructions from hitting the window for corruption. 453 454 If unsure, say Y. 455 456config ARM64_WORKAROUND_CLEAN_CACHE 457 bool 458 459config ARM64_ERRATUM_826319 460 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 461 default y 462 select ARM64_WORKAROUND_CLEAN_CACHE 463 help 464 This option adds an alternative code sequence to work around ARM 465 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 466 AXI master interface and an L2 cache. 467 468 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 469 and is unable to accept a certain write via this interface, it will 470 not progress on read data presented on the read data channel and the 471 system can deadlock. 472 473 The workaround promotes data cache clean instructions to 474 data cache clean-and-invalidate. 475 Please note that this does not necessarily enable the workaround, 476 as it depends on the alternative framework, which will only patch 477 the kernel if an affected CPU is detected. 478 479 If unsure, say Y. 480 481config ARM64_ERRATUM_827319 482 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 483 default y 484 select ARM64_WORKAROUND_CLEAN_CACHE 485 help 486 This option adds an alternative code sequence to work around ARM 487 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 488 master interface and an L2 cache. 489 490 Under certain conditions this erratum can cause a clean line eviction 491 to occur at the same time as another transaction to the same address 492 on the AMBA 5 CHI interface, which can cause data corruption if the 493 interconnect reorders the two transactions. 494 495 The workaround promotes data cache clean instructions to 496 data cache clean-and-invalidate. 497 Please note that this does not necessarily enable the workaround, 498 as it depends on the alternative framework, which will only patch 499 the kernel if an affected CPU is detected. 500 501 If unsure, say Y. 502 503config ARM64_ERRATUM_824069 504 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 505 default y 506 select ARM64_WORKAROUND_CLEAN_CACHE 507 help 508 This option adds an alternative code sequence to work around ARM 509 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 510 to a coherent interconnect. 511 512 If a Cortex-A53 processor is executing a store or prefetch for 513 write instruction at the same time as a processor in another 514 cluster is executing a cache maintenance operation to the same 515 address, then this erratum might cause a clean cache line to be 516 incorrectly marked as dirty. 517 518 The workaround promotes data cache clean instructions to 519 data cache clean-and-invalidate. 520 Please note that this option does not necessarily enable the 521 workaround, as it depends on the alternative framework, which will 522 only patch the kernel if an affected CPU is detected. 523 524 If unsure, say Y. 525 526config ARM64_ERRATUM_819472 527 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 528 default y 529 select ARM64_WORKAROUND_CLEAN_CACHE 530 help 531 This option adds an alternative code sequence to work around ARM 532 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 533 present when it is connected to a coherent interconnect. 534 535 If the processor is executing a load and store exclusive sequence at 536 the same time as a processor in another cluster is executing a cache 537 maintenance operation to the same address, then this erratum might 538 cause data corruption. 539 540 The workaround promotes data cache clean instructions to 541 data cache clean-and-invalidate. 542 Please note that this does not necessarily enable the workaround, 543 as it depends on the alternative framework, which will only patch 544 the kernel if an affected CPU is detected. 545 546 If unsure, say Y. 547 548config ARM64_ERRATUM_832075 549 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 550 default y 551 help 552 This option adds an alternative code sequence to work around ARM 553 erratum 832075 on Cortex-A57 parts up to r1p2. 554 555 Affected Cortex-A57 parts might deadlock when exclusive load/store 556 instructions to Write-Back memory are mixed with Device loads. 557 558 The workaround is to promote device loads to use Load-Acquire 559 semantics. 560 Please note that this does not necessarily enable the workaround, 561 as it depends on the alternative framework, which will only patch 562 the kernel if an affected CPU is detected. 563 564 If unsure, say Y. 565 566config ARM64_ERRATUM_834220 567 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 568 depends on KVM 569 help 570 This option adds an alternative code sequence to work around ARM 571 erratum 834220 on Cortex-A57 parts up to r1p2. 572 573 Affected Cortex-A57 parts might report a Stage 2 translation 574 fault as the result of a Stage 1 fault for load crossing a 575 page boundary when there is a permission or device memory 576 alignment fault at Stage 1 and a translation fault at Stage 2. 577 578 The workaround is to verify that the Stage 1 translation 579 doesn't generate a fault before handling the Stage 2 fault. 580 Please note that this does not necessarily enable the workaround, 581 as it depends on the alternative framework, which will only patch 582 the kernel if an affected CPU is detected. 583 584 If unsure, say N. 585 586config ARM64_ERRATUM_1742098 587 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 588 depends on COMPAT 589 default y 590 help 591 This option removes the AES hwcap for aarch32 user-space to 592 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 593 594 Affected parts may corrupt the AES state if an interrupt is 595 taken between a pair of AES instructions. These instructions 596 are only present if the cryptography extensions are present. 597 All software should have a fallback implementation for CPUs 598 that don't implement the cryptography extensions. 599 600 If unsure, say Y. 601 602config ARM64_ERRATUM_845719 603 bool "Cortex-A53: 845719: a load might read incorrect data" 604 depends on COMPAT 605 default y 606 help 607 This option adds an alternative code sequence to work around ARM 608 erratum 845719 on Cortex-A53 parts up to r0p4. 609 610 When running a compat (AArch32) userspace on an affected Cortex-A53 611 part, a load at EL0 from a virtual address that matches the bottom 32 612 bits of the virtual address used by a recent load at (AArch64) EL1 613 might return incorrect data. 614 615 The workaround is to write the contextidr_el1 register on exception 616 return to a 32-bit task. 617 Please note that this does not necessarily enable the workaround, 618 as it depends on the alternative framework, which will only patch 619 the kernel if an affected CPU is detected. 620 621 If unsure, say Y. 622 623config ARM64_ERRATUM_843419 624 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 625 default y 626 help 627 This option links the kernel with '--fix-cortex-a53-843419' and 628 enables PLT support to replace certain ADRP instructions, which can 629 cause subsequent memory accesses to use an incorrect address on 630 Cortex-A53 parts up to r0p4. 631 632 If unsure, say Y. 633 634config ARM64_ERRATUM_1024718 635 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 636 default y 637 help 638 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 639 640 Affected Cortex-A55 cores (all revisions) could cause incorrect 641 update of the hardware dirty bit when the DBM/AP bits are updated 642 without a break-before-make. The workaround is to disable the usage 643 of hardware DBM locally on the affected cores. CPUs not affected by 644 this erratum will continue to use the feature. 645 646 If unsure, say Y. 647 648config ARM64_ERRATUM_1418040 649 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 650 default y 651 depends on COMPAT 652 help 653 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 654 errata 1188873 and 1418040. 655 656 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 657 cause register corruption when accessing the timer registers 658 from AArch32 userspace. 659 660 If unsure, say Y. 661 662config ARM64_WORKAROUND_SPECULATIVE_AT 663 bool 664 665config ARM64_ERRATUM_1165522 666 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 667 default y 668 select ARM64_WORKAROUND_SPECULATIVE_AT 669 help 670 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 671 672 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 673 corrupted TLBs by speculating an AT instruction during a guest 674 context switch. 675 676 If unsure, say Y. 677 678config ARM64_ERRATUM_1319367 679 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 680 default y 681 select ARM64_WORKAROUND_SPECULATIVE_AT 682 help 683 This option adds work arounds for ARM Cortex-A57 erratum 1319537 684 and A72 erratum 1319367 685 686 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 687 speculating an AT instruction during a guest context switch. 688 689 If unsure, say Y. 690 691config ARM64_ERRATUM_1530923 692 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 693 default y 694 select ARM64_WORKAROUND_SPECULATIVE_AT 695 help 696 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 697 698 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 699 corrupted TLBs by speculating an AT instruction during a guest 700 context switch. 701 702 If unsure, say Y. 703 704config ARM64_WORKAROUND_REPEAT_TLBI 705 bool 706 707config ARM64_ERRATUM_2441007 708 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 709 select ARM64_WORKAROUND_REPEAT_TLBI 710 help 711 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 712 713 Under very rare circumstances, affected Cortex-A55 CPUs 714 may not handle a race between a break-before-make sequence on one 715 CPU, and another CPU accessing the same page. This could allow a 716 store to a page that has been unmapped. 717 718 Work around this by adding the affected CPUs to the list that needs 719 TLB sequences to be done twice. 720 721 If unsure, say N. 722 723config ARM64_ERRATUM_1286807 724 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 725 select ARM64_WORKAROUND_REPEAT_TLBI 726 help 727 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 728 729 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 730 address for a cacheable mapping of a location is being 731 accessed by a core while another core is remapping the virtual 732 address to a new physical page using the recommended 733 break-before-make sequence, then under very rare circumstances 734 TLBI+DSB completes before a read using the translation being 735 invalidated has been observed by other observers. The 736 workaround repeats the TLBI+DSB operation. 737 738 If unsure, say N. 739 740config ARM64_ERRATUM_1463225 741 bool "Cortex-A76: Software Step might prevent interrupt recognition" 742 default y 743 help 744 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 745 746 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 747 of a system call instruction (SVC) can prevent recognition of 748 subsequent interrupts when software stepping is disabled in the 749 exception handler of the system call and either kernel debugging 750 is enabled or VHE is in use. 751 752 Work around the erratum by triggering a dummy step exception 753 when handling a system call from a task that is being stepped 754 in a VHE configuration of the kernel. 755 756 If unsure, say Y. 757 758config ARM64_ERRATUM_1542419 759 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 760 help 761 This option adds a workaround for ARM Neoverse-N1 erratum 762 1542419. 763 764 Affected Neoverse-N1 cores could execute a stale instruction when 765 modified by another CPU. The workaround depends on a firmware 766 counterpart. 767 768 Workaround the issue by hiding the DIC feature from EL0. This 769 forces user-space to perform cache maintenance. 770 771 If unsure, say N. 772 773config ARM64_ERRATUM_1508412 774 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 775 default y 776 help 777 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 778 779 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 780 of a store-exclusive or read of PAR_EL1 and a load with device or 781 non-cacheable memory attributes. The workaround depends on a firmware 782 counterpart. 783 784 KVM guests must also have the workaround implemented or they can 785 deadlock the system. 786 787 Work around the issue by inserting DMB SY barriers around PAR_EL1 788 register reads and warning KVM users. The DMB barrier is sufficient 789 to prevent a speculative PAR_EL1 read. 790 791 If unsure, say Y. 792 793config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 794 bool 795 796config ARM64_ERRATUM_2051678 797 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 798 default y 799 help 800 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 801 Affected Cortex-A510 might not respect the ordering rules for 802 hardware update of the page table's dirty bit. The workaround 803 is to not enable the feature on affected CPUs. 804 805 If unsure, say Y. 806 807config ARM64_ERRATUM_2077057 808 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 809 default y 810 help 811 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 812 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 813 expected, but a Pointer Authentication trap is taken instead. The 814 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 815 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 816 817 This can only happen when EL2 is stepping EL1. 818 819 When these conditions occur, the SPSR_EL2 value is unchanged from the 820 previous guest entry, and can be restored from the in-memory copy. 821 822 If unsure, say Y. 823 824config ARM64_ERRATUM_2658417 825 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 826 default y 827 help 828 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 829 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 830 BFMMLA or VMMLA instructions in rare circumstances when a pair of 831 A510 CPUs are using shared neon hardware. As the sharing is not 832 discoverable by the kernel, hide the BF16 HWCAP to indicate that 833 user-space should not be using these instructions. 834 835 If unsure, say Y. 836 837config ARM64_ERRATUM_2119858 838 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 839 default y 840 depends on CORESIGHT_TRBE 841 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 842 help 843 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 844 845 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 846 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 847 the event of a WRAP event. 848 849 Work around the issue by always making sure we move the TRBPTR_EL1 by 850 256 bytes before enabling the buffer and filling the first 256 bytes of 851 the buffer with ETM ignore packets upon disabling. 852 853 If unsure, say Y. 854 855config ARM64_ERRATUM_2139208 856 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 857 default y 858 depends on CORESIGHT_TRBE 859 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 860 help 861 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 862 863 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 864 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 865 the event of a WRAP event. 866 867 Work around the issue by always making sure we move the TRBPTR_EL1 by 868 256 bytes before enabling the buffer and filling the first 256 bytes of 869 the buffer with ETM ignore packets upon disabling. 870 871 If unsure, say Y. 872 873config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 874 bool 875 876config ARM64_ERRATUM_2054223 877 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 878 default y 879 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 880 help 881 Enable workaround for ARM Cortex-A710 erratum 2054223 882 883 Affected cores may fail to flush the trace data on a TSB instruction, when 884 the PE is in trace prohibited state. This will cause losing a few bytes 885 of the trace cached. 886 887 Workaround is to issue two TSB consecutively on affected cores. 888 889 If unsure, say Y. 890 891config ARM64_ERRATUM_2067961 892 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 893 default y 894 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 895 help 896 Enable workaround for ARM Neoverse-N2 erratum 2067961 897 898 Affected cores may fail to flush the trace data on a TSB instruction, when 899 the PE is in trace prohibited state. This will cause losing a few bytes 900 of the trace cached. 901 902 Workaround is to issue two TSB consecutively on affected cores. 903 904 If unsure, say Y. 905 906config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 907 bool 908 909config ARM64_ERRATUM_2253138 910 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 911 depends on CORESIGHT_TRBE 912 default y 913 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 914 help 915 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 916 917 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 918 for TRBE. Under some conditions, the TRBE might generate a write to the next 919 virtually addressed page following the last page of the TRBE address space 920 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 921 922 Work around this in the driver by always making sure that there is a 923 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 924 925 If unsure, say Y. 926 927config ARM64_ERRATUM_2224489 928 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 929 depends on CORESIGHT_TRBE 930 default y 931 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 932 help 933 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 934 935 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 936 for TRBE. Under some conditions, the TRBE might generate a write to the next 937 virtually addressed page following the last page of the TRBE address space 938 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 939 940 Work around this in the driver by always making sure that there is a 941 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 942 943 If unsure, say Y. 944 945config ARM64_ERRATUM_2441009 946 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 947 select ARM64_WORKAROUND_REPEAT_TLBI 948 help 949 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 950 951 Under very rare circumstances, affected Cortex-A510 CPUs 952 may not handle a race between a break-before-make sequence on one 953 CPU, and another CPU accessing the same page. This could allow a 954 store to a page that has been unmapped. 955 956 Work around this by adding the affected CPUs to the list that needs 957 TLB sequences to be done twice. 958 959 If unsure, say N. 960 961config ARM64_ERRATUM_2064142 962 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 963 depends on CORESIGHT_TRBE 964 default y 965 help 966 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 967 968 Affected Cortex-A510 core might fail to write into system registers after the 969 TRBE has been disabled. Under some conditions after the TRBE has been disabled 970 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 971 and TRBTRG_EL1 will be ignored and will not be effected. 972 973 Work around this in the driver by executing TSB CSYNC and DSB after collection 974 is stopped and before performing a system register write to one of the affected 975 registers. 976 977 If unsure, say Y. 978 979config ARM64_ERRATUM_2038923 980 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 981 depends on CORESIGHT_TRBE 982 default y 983 help 984 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 985 986 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 987 prohibited within the CPU. As a result, the trace buffer or trace buffer state 988 might be corrupted. This happens after TRBE buffer has been enabled by setting 989 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 990 execution changes from a context, in which trace is prohibited to one where it 991 isn't, or vice versa. In these mentioned conditions, the view of whether trace 992 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 993 the trace buffer state might be corrupted. 994 995 Work around this in the driver by preventing an inconsistent view of whether the 996 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 997 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 998 two ISB instructions if no ERET is to take place. 999 1000 If unsure, say Y. 1001 1002config ARM64_ERRATUM_1902691 1003 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1004 depends on CORESIGHT_TRBE 1005 default y 1006 help 1007 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1008 1009 Affected Cortex-A510 core might cause trace data corruption, when being written 1010 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1011 trace data. 1012 1013 Work around this problem in the driver by just preventing TRBE initialization on 1014 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1015 on such implementations. This will cover the kernel for any firmware that doesn't 1016 do this already. 1017 1018 If unsure, say Y. 1019 1020config ARM64_ERRATUM_2457168 1021 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1022 depends on ARM64_AMU_EXTN 1023 default y 1024 help 1025 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1026 1027 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1028 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1029 incorrectly giving a significantly higher output value. 1030 1031 Work around this problem by returning 0 when reading the affected counter in 1032 key locations that results in disabling all users of this counter. This effect 1033 is the same to firmware disabling affected counters. 1034 1035 If unsure, say Y. 1036 1037config ARM64_ERRATUM_2645198 1038 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1039 default y 1040 help 1041 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1042 1043 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1044 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1045 next instruction abort caused by permission fault. 1046 1047 Only user-space does executable to non-executable permission transition via 1048 mprotect() system call. Workaround the problem by doing a break-before-make 1049 TLB invalidation, for all changes to executable user space mappings. 1050 1051 If unsure, say Y. 1052 1053config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1054 bool 1055 1056config ARM64_ERRATUM_2966298 1057 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1058 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1059 default y 1060 help 1061 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1062 1063 On an affected Cortex-A520 core, a speculatively executed unprivileged 1064 load might leak data from a privileged level via a cache side channel. 1065 1066 Work around this problem by executing a TLBI before returning to EL0. 1067 1068 If unsure, say Y. 1069 1070config ARM64_ERRATUM_3117295 1071 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1072 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1073 default y 1074 help 1075 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1076 1077 On an affected Cortex-A510 core, a speculatively executed unprivileged 1078 load might leak data from a privileged level via a cache side channel. 1079 1080 Work around this problem by executing a TLBI before returning to EL0. 1081 1082 If unsure, say Y. 1083 1084config ARM64_ERRATUM_3194386 1085 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1086 default y 1087 help 1088 This option adds the workaround for the following errata: 1089 1090 * ARM Cortex-A76 erratum 3324349 1091 * ARM Cortex-A77 erratum 3324348 1092 * ARM Cortex-A78 erratum 3324344 1093 * ARM Cortex-A78C erratum 3324346 1094 * ARM Cortex-A78C erratum 3324347 1095 * ARM Cortex-A710 erratam 3324338 1096 * ARM Cortex-A715 errartum 3456084 1097 * ARM Cortex-A720 erratum 3456091 1098 * ARM Cortex-A725 erratum 3456106 1099 * ARM Cortex-X1 erratum 3324344 1100 * ARM Cortex-X1C erratum 3324346 1101 * ARM Cortex-X2 erratum 3324338 1102 * ARM Cortex-X3 erratum 3324335 1103 * ARM Cortex-X4 erratum 3194386 1104 * ARM Cortex-X925 erratum 3324334 1105 * ARM Neoverse-N1 erratum 3324349 1106 * ARM Neoverse N2 erratum 3324339 1107 * ARM Neoverse-N3 erratum 3456111 1108 * ARM Neoverse-V1 erratum 3324341 1109 * ARM Neoverse V2 erratum 3324336 1110 * ARM Neoverse-V3 erratum 3312417 1111 * ARM Neoverse-V3AE erratum 3312417 1112 1113 On affected cores "MSR SSBS, #0" instructions may not affect 1114 subsequent speculative instructions, which may permit unexepected 1115 speculative store bypassing. 1116 1117 Work around this problem by placing a Speculation Barrier (SB) or 1118 Instruction Synchronization Barrier (ISB) after kernel changes to 1119 SSBS. The presence of the SSBS special-purpose register is hidden 1120 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1121 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1122 1123 If unsure, say Y. 1124 1125config ARM64_ERRATUM_4311569 1126 bool "SI L1: 4311569: workaround for premature CMO completion erratum" 1127 default y 1128 help 1129 This option adds the workaround for ARM SI L1 erratum 4311569. 1130 1131 The erratum of SI L1 can cause an early response to a combined write 1132 and cache maintenance operation (WR+CMO) before the operation is fully 1133 completed to the Point of Serialization (POS). 1134 This can result in a non-I/O coherent agent observing stale data, 1135 potentially leading to system instability or incorrect behavior. 1136 1137 Enabling this option implements a software workaround by inserting a 1138 second loop of Cache Maintenance Operation (CMO) immediately following the 1139 end of function to do CMOs. This ensures that the data is correctly serialized 1140 before the buffer is handed off to a non-coherent agent. 1141 1142 If unsure, say Y. 1143 1144config CAVIUM_ERRATUM_22375 1145 bool "Cavium erratum 22375, 24313" 1146 default y 1147 help 1148 Enable workaround for errata 22375 and 24313. 1149 1150 This implements two gicv3-its errata workarounds for ThunderX. Both 1151 with a small impact affecting only ITS table allocation. 1152 1153 erratum 22375: only alloc 8MB table size 1154 erratum 24313: ignore memory access type 1155 1156 The fixes are in ITS initialization and basically ignore memory access 1157 type and table size provided by the TYPER and BASER registers. 1158 1159 If unsure, say Y. 1160 1161config CAVIUM_ERRATUM_23144 1162 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1163 depends on NUMA 1164 default y 1165 help 1166 ITS SYNC command hang for cross node io and collections/cpu mapping. 1167 1168 If unsure, say Y. 1169 1170config CAVIUM_ERRATUM_23154 1171 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1172 default y 1173 help 1174 The ThunderX GICv3 implementation requires a modified version for 1175 reading the IAR status to ensure data synchronization 1176 (access to icc_iar1_el1 is not sync'ed before and after). 1177 1178 It also suffers from erratum 38545 (also present on Marvell's 1179 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1180 spuriously presented to the CPU interface. 1181 1182 If unsure, say Y. 1183 1184config CAVIUM_ERRATUM_27456 1185 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1186 default y 1187 help 1188 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1189 instructions may cause the icache to become corrupted if it 1190 contains data for a non-current ASID. The fix is to 1191 invalidate the icache when changing the mm context. 1192 1193 If unsure, say Y. 1194 1195config CAVIUM_ERRATUM_30115 1196 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1197 default y 1198 help 1199 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1200 1.2, and T83 Pass 1.0, KVM guest execution may disable 1201 interrupts in host. Trapping both GICv3 group-0 and group-1 1202 accesses sidesteps the issue. 1203 1204 If unsure, say Y. 1205 1206config CAVIUM_TX2_ERRATUM_219 1207 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1208 default y 1209 help 1210 On Cavium ThunderX2, a load, store or prefetch instruction between a 1211 TTBR update and the corresponding context synchronizing operation can 1212 cause a spurious Data Abort to be delivered to any hardware thread in 1213 the CPU core. 1214 1215 Work around the issue by avoiding the problematic code sequence and 1216 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1217 trap handler performs the corresponding register access, skips the 1218 instruction and ensures context synchronization by virtue of the 1219 exception return. 1220 1221 If unsure, say Y. 1222 1223config FUJITSU_ERRATUM_010001 1224 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1225 default y 1226 help 1227 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1228 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1229 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1230 This fault occurs under a specific hardware condition when a 1231 load/store instruction performs an address translation using: 1232 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1233 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1234 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1235 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1236 1237 The workaround is to ensure these bits are clear in TCR_ELx. 1238 The workaround only affects the Fujitsu-A64FX. 1239 1240 If unsure, say Y. 1241 1242config HISILICON_ERRATUM_161600802 1243 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1244 default y 1245 help 1246 The HiSilicon Hip07 SoC uses the wrong redistributor base 1247 when issued ITS commands such as VMOVP and VMAPP, and requires 1248 a 128kB offset to be applied to the target address in this commands. 1249 1250 If unsure, say Y. 1251 1252config HISILICON_ERRATUM_162100801 1253 bool "Hip09 162100801 erratum support" 1254 default y 1255 help 1256 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1257 during unmapping operation, which will cause some vSGIs lost. 1258 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1259 after VMOVP. 1260 1261 If unsure, say Y. 1262 1263config QCOM_FALKOR_ERRATUM_1003 1264 bool "Falkor E1003: Incorrect translation due to ASID change" 1265 default y 1266 help 1267 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1268 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1269 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1270 then only for entries in the walk cache, since the leaf translation 1271 is unchanged. Work around the erratum by invalidating the walk cache 1272 entries for the trampoline before entering the kernel proper. 1273 1274config QCOM_FALKOR_ERRATUM_1009 1275 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1276 default y 1277 select ARM64_WORKAROUND_REPEAT_TLBI 1278 help 1279 On Falkor v1, the CPU may prematurely complete a DSB following a 1280 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1281 one more time to fix the issue. 1282 1283 If unsure, say Y. 1284 1285config QCOM_QDF2400_ERRATUM_0065 1286 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1287 default y 1288 help 1289 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1290 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1291 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1292 1293 If unsure, say Y. 1294 1295config QCOM_FALKOR_ERRATUM_E1041 1296 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1297 default y 1298 help 1299 Falkor CPU may speculatively fetch instructions from an improper 1300 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1301 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1302 1303 If unsure, say Y. 1304 1305config NVIDIA_CARMEL_CNP_ERRATUM 1306 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1307 default y 1308 help 1309 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1310 invalidate shared TLB entries installed by a different core, as it would 1311 on standard ARM cores. 1312 1313 If unsure, say Y. 1314 1315config ROCKCHIP_ERRATUM_3568002 1316 bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" 1317 default y 1318 help 1319 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI 1320 addressing limited to the first 32bit of physical address space. 1321 1322 If unsure, say Y. 1323 1324config ROCKCHIP_ERRATUM_3588001 1325 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1326 default y 1327 help 1328 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1329 This means, that its sharability feature may not be used, even though it 1330 is supported by the IP itself. 1331 1332 If unsure, say Y. 1333 1334config SOCIONEXT_SYNQUACER_PREITS 1335 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1336 default y 1337 help 1338 Socionext Synquacer SoCs implement a separate h/w block to generate 1339 MSI doorbell writes with non-zero values for the device ID. 1340 1341 If unsure, say Y. 1342 1343endmenu # "ARM errata workarounds via the alternatives framework" 1344 1345choice 1346 prompt "Page size" 1347 default ARM64_4K_PAGES 1348 help 1349 Page size (translation granule) configuration. 1350 1351config ARM64_4K_PAGES 1352 bool "4KB" 1353 select HAVE_PAGE_SIZE_4KB 1354 help 1355 This feature enables 4KB pages support. 1356 1357config ARM64_16K_PAGES 1358 bool "16KB" 1359 select HAVE_PAGE_SIZE_16KB 1360 help 1361 The system will use 16KB pages support. AArch32 emulation 1362 requires applications compiled with 16K (or a multiple of 16K) 1363 aligned segments. 1364 1365config ARM64_64K_PAGES 1366 bool "64KB" 1367 select HAVE_PAGE_SIZE_64KB 1368 help 1369 This feature enables 64KB pages support (4KB by default) 1370 allowing only two levels of page tables and faster TLB 1371 look-up. AArch32 emulation requires applications compiled 1372 with 64K aligned segments. 1373 1374endchoice 1375 1376choice 1377 prompt "Virtual address space size" 1378 default ARM64_VA_BITS_52 1379 help 1380 Allows choosing one of multiple possible virtual address 1381 space sizes. The level of translation table is determined by 1382 a combination of page size and virtual address space size. 1383 1384config ARM64_VA_BITS_36 1385 bool "36-bit" if EXPERT 1386 depends on PAGE_SIZE_16KB 1387 1388config ARM64_VA_BITS_39 1389 bool "39-bit" 1390 depends on PAGE_SIZE_4KB 1391 1392config ARM64_VA_BITS_42 1393 bool "42-bit" 1394 depends on PAGE_SIZE_64KB 1395 1396config ARM64_VA_BITS_47 1397 bool "47-bit" 1398 depends on PAGE_SIZE_16KB 1399 1400config ARM64_VA_BITS_48 1401 bool "48-bit" 1402 1403config ARM64_VA_BITS_52 1404 bool "52-bit" 1405 help 1406 Enable 52-bit virtual addressing for userspace when explicitly 1407 requested via a hint to mmap(). The kernel will also use 52-bit 1408 virtual addresses for its own mappings (provided HW support for 1409 this feature is available, otherwise it reverts to 48-bit). 1410 1411 NOTE: Enabling 52-bit virtual addressing in conjunction with 1412 ARMv8.3 Pointer Authentication will result in the PAC being 1413 reduced from 7 bits to 3 bits, which may have a significant 1414 impact on its susceptibility to brute-force attacks. 1415 1416 If unsure, select 48-bit virtual addressing instead. 1417 1418endchoice 1419 1420config ARM64_FORCE_52BIT 1421 bool "Force 52-bit virtual addresses for userspace" 1422 depends on ARM64_VA_BITS_52 && EXPERT 1423 help 1424 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1425 to maintain compatibility with older software by providing 48-bit VAs 1426 unless a hint is supplied to mmap. 1427 1428 This configuration option disables the 48-bit compatibility logic, and 1429 forces all userspace addresses to be 52-bit on HW that supports it. One 1430 should only enable this configuration option for stress testing userspace 1431 memory management code. If unsure say N here. 1432 1433config ARM64_VA_BITS 1434 int 1435 default 36 if ARM64_VA_BITS_36 1436 default 39 if ARM64_VA_BITS_39 1437 default 42 if ARM64_VA_BITS_42 1438 default 47 if ARM64_VA_BITS_47 1439 default 48 if ARM64_VA_BITS_48 1440 default 52 if ARM64_VA_BITS_52 1441 1442choice 1443 prompt "Physical address space size" 1444 default ARM64_PA_BITS_48 1445 help 1446 Choose the maximum physical address range that the kernel will 1447 support. 1448 1449config ARM64_PA_BITS_48 1450 bool "48-bit" 1451 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1452 1453config ARM64_PA_BITS_52 1454 bool "52-bit" 1455 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1456 help 1457 Enable support for a 52-bit physical address space, introduced as 1458 part of the ARMv8.2-LPA extension. 1459 1460 With this enabled, the kernel will also continue to work on CPUs that 1461 do not support ARMv8.2-LPA, but with some added memory overhead (and 1462 minor performance overhead). 1463 1464endchoice 1465 1466config ARM64_PA_BITS 1467 int 1468 default 48 if ARM64_PA_BITS_48 1469 default 52 if ARM64_PA_BITS_52 1470 1471config ARM64_LPA2 1472 def_bool y 1473 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1474 1475choice 1476 prompt "Endianness" 1477 default CPU_LITTLE_ENDIAN 1478 help 1479 Select the endianness of data accesses performed by the CPU. Userspace 1480 applications will need to be compiled and linked for the endianness 1481 that is selected here. 1482 1483config CPU_BIG_ENDIAN 1484 bool "Build big-endian kernel" 1485 depends on BROKEN 1486 help 1487 Say Y if you plan on running a kernel with a big-endian userspace. 1488 1489config CPU_LITTLE_ENDIAN 1490 bool "Build little-endian kernel" 1491 help 1492 Say Y if you plan on running a kernel with a little-endian userspace. 1493 This is usually the case for distributions targeting arm64. 1494 1495endchoice 1496 1497config NR_CPUS 1498 int "Maximum number of CPUs (2-4096)" 1499 range 2 4096 1500 default "512" 1501 1502config HOTPLUG_CPU 1503 bool "Support for hot-pluggable CPUs" 1504 select GENERIC_IRQ_MIGRATION 1505 help 1506 Say Y here to experiment with turning CPUs off and on. CPUs 1507 can be controlled through /sys/devices/system/cpu. 1508 1509# Common NUMA Features 1510config NUMA 1511 bool "NUMA Memory Allocation and Scheduler Support" 1512 select GENERIC_ARCH_NUMA 1513 select OF_NUMA 1514 select HAVE_SETUP_PER_CPU_AREA 1515 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1516 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1517 select USE_PERCPU_NUMA_NODE_ID 1518 help 1519 Enable NUMA (Non-Uniform Memory Access) support. 1520 1521 The kernel will try to allocate memory used by a CPU on the 1522 local memory of the CPU and add some more 1523 NUMA awareness to the kernel. 1524 1525config NODES_SHIFT 1526 int "Maximum NUMA Nodes (as a power of 2)" 1527 range 1 10 1528 default "4" 1529 depends on NUMA 1530 help 1531 Specify the maximum number of NUMA Nodes available on the target 1532 system. Increases memory reserved to accommodate various tables. 1533 1534source "kernel/Kconfig.hz" 1535 1536config ARCH_SPARSEMEM_ENABLE 1537 def_bool y 1538 select SPARSEMEM_VMEMMAP_ENABLE 1539 1540config HW_PERF_EVENTS 1541 def_bool y 1542 depends on ARM_PMU 1543 1544# Supported by clang >= 7.0 or GCC >= 12.0.0 1545config CC_HAVE_SHADOW_CALL_STACK 1546 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1547 1548config PARAVIRT 1549 bool "Enable paravirtualization code" 1550 select HAVE_PV_STEAL_CLOCK_GEN 1551 help 1552 This changes the kernel so it can modify itself when it is run 1553 under a hypervisor, potentially improving performance significantly 1554 over full virtualization. 1555 1556config PARAVIRT_TIME_ACCOUNTING 1557 bool "Paravirtual steal time accounting" 1558 select PARAVIRT 1559 help 1560 Select this option to enable fine granularity task steal time 1561 accounting. Time spent executing other tasks in parallel with 1562 the current vCPU is discounted from the vCPU power. To account for 1563 that, there can be a small performance impact. 1564 1565 If in doubt, say N here. 1566 1567config ARCH_SUPPORTS_KEXEC 1568 def_bool PM_SLEEP_SMP 1569 1570config ARCH_SUPPORTS_KEXEC_FILE 1571 def_bool y 1572 1573config ARCH_SELECTS_KEXEC_FILE 1574 def_bool y 1575 depends on KEXEC_FILE 1576 select HAVE_IMA_KEXEC if IMA 1577 1578config ARCH_SUPPORTS_KEXEC_SIG 1579 def_bool y 1580 1581config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1582 def_bool y 1583 1584config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1585 def_bool y 1586 1587config ARCH_SUPPORTS_KEXEC_HANDOVER 1588 def_bool y 1589 1590config ARCH_SUPPORTS_CRASH_DUMP 1591 def_bool y 1592 1593config ARCH_DEFAULT_CRASH_DUMP 1594 def_bool y 1595 1596config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1597 def_bool CRASH_RESERVE 1598 1599config TRANS_TABLE 1600 def_bool y 1601 depends on HIBERNATION || KEXEC_CORE 1602 1603config XEN_DOM0 1604 def_bool y 1605 depends on XEN 1606 1607config XEN 1608 bool "Xen guest support on ARM64" 1609 depends on ARM64 && OF 1610 select SWIOTLB_XEN 1611 select PARAVIRT 1612 help 1613 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1614 1615# include/linux/mmzone.h requires the following to be true: 1616# 1617# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1618# 1619# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1620# 1621# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1622# ----+-------------------+--------------+----------------------+-------------------------+ 1623# 4K | 27 | 12 | 15 | 10 | 1624# 16K | 27 | 14 | 13 | 11 | 1625# 64K | 29 | 16 | 13 | 13 | 1626config ARCH_FORCE_MAX_ORDER 1627 int 1628 default "13" if ARM64_64K_PAGES 1629 default "11" if ARM64_16K_PAGES 1630 default "10" 1631 help 1632 The kernel page allocator limits the size of maximal physically 1633 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1634 defines the maximal power of two of number of pages that can be 1635 allocated as a single contiguous block. This option allows 1636 overriding the default setting when ability to allocate very 1637 large blocks of physically contiguous memory is required. 1638 1639 The maximal size of allocation cannot exceed the size of the 1640 section, so the value of MAX_PAGE_ORDER should satisfy 1641 1642 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1643 1644 Don't change if unsure. 1645 1646config UNMAP_KERNEL_AT_EL0 1647 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1648 default y 1649 help 1650 Speculation attacks against some high-performance processors can 1651 be used to bypass MMU permission checks and leak kernel data to 1652 userspace. This can be defended against by unmapping the kernel 1653 when running in userspace, mapping it back in on exception entry 1654 via a trampoline page in the vector table. 1655 1656 If unsure, say Y. 1657 1658config MITIGATE_SPECTRE_BRANCH_HISTORY 1659 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1660 default y 1661 help 1662 Speculation attacks against some high-performance processors can 1663 make use of branch history to influence future speculation. 1664 When taking an exception from user-space, a sequence of branches 1665 or a firmware call overwrites the branch history. 1666 1667config ARM64_SW_TTBR0_PAN 1668 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1669 depends on !KCSAN 1670 help 1671 Enabling this option prevents the kernel from accessing 1672 user-space memory directly by pointing TTBR0_EL1 to a reserved 1673 zeroed area and reserved ASID. The user access routines 1674 restore the valid TTBR0_EL1 temporarily. 1675 1676config ARM64_TAGGED_ADDR_ABI 1677 bool "Enable the tagged user addresses syscall ABI" 1678 default y 1679 help 1680 When this option is enabled, user applications can opt in to a 1681 relaxed ABI via prctl() allowing tagged addresses to be passed 1682 to system calls as pointer arguments. For details, see 1683 Documentation/arch/arm64/tagged-address-abi.rst. 1684 1685menuconfig COMPAT 1686 bool "Kernel support for 32-bit EL0" 1687 depends on ARM64_4K_PAGES || EXPERT 1688 select HAVE_UID16 1689 select OLD_SIGSUSPEND3 1690 select COMPAT_OLD_SIGACTION 1691 help 1692 This option enables support for a 32-bit EL0 running under a 64-bit 1693 kernel at EL1. AArch32-specific components such as system calls, 1694 the user helper functions, VFP support and the ptrace interface are 1695 handled appropriately by the kernel. 1696 1697 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1698 that you will only be able to execute AArch32 binaries that were compiled 1699 with page size aligned segments. 1700 1701 If you want to execute 32-bit userspace applications, say Y. 1702 1703if COMPAT 1704 1705config KUSER_HELPERS 1706 bool "Enable kuser helpers page for 32-bit applications" 1707 default y 1708 help 1709 Warning: disabling this option may break 32-bit user programs. 1710 1711 Provide kuser helpers to compat tasks. The kernel provides 1712 helper code to userspace in read only form at a fixed location 1713 to allow userspace to be independent of the CPU type fitted to 1714 the system. This permits binaries to be run on ARMv4 through 1715 to ARMv8 without modification. 1716 1717 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1718 1719 However, the fixed address nature of these helpers can be used 1720 by ROP (return orientated programming) authors when creating 1721 exploits. 1722 1723 If all of the binaries and libraries which run on your platform 1724 are built specifically for your platform, and make no use of 1725 these helpers, then you can turn this option off to hinder 1726 such exploits. However, in that case, if a binary or library 1727 relying on those helpers is run, it will not function correctly. 1728 1729 Say N here only if you are absolutely certain that you do not 1730 need these helpers; otherwise, the safe option is to say Y. 1731 1732config COMPAT_VDSO 1733 bool "Enable vDSO for 32-bit applications" 1734 depends on !CPU_BIG_ENDIAN 1735 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1736 default y 1737 help 1738 Place in the process address space of 32-bit applications an 1739 ELF shared object providing fast implementations of gettimeofday 1740 and clock_gettime. 1741 1742 You must have a 32-bit build of glibc 2.22 or later for programs 1743 to seamlessly take advantage of this. 1744 1745config THUMB2_COMPAT_VDSO 1746 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1747 depends on COMPAT_VDSO 1748 default y 1749 help 1750 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1751 otherwise with '-marm'. 1752 1753config COMPAT_ALIGNMENT_FIXUPS 1754 bool "Fix up misaligned multi-word loads and stores in user space" 1755 1756menuconfig ARMV8_DEPRECATED 1757 bool "Emulate deprecated/obsolete ARMv8 instructions" 1758 depends on SYSCTL 1759 help 1760 Legacy software support may require certain instructions 1761 that have been deprecated or obsoleted in the architecture. 1762 1763 Enable this config to enable selective emulation of these 1764 features. 1765 1766 If unsure, say Y 1767 1768if ARMV8_DEPRECATED 1769 1770config SWP_EMULATION 1771 bool "Emulate SWP/SWPB instructions" 1772 help 1773 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1774 they are always undefined. Say Y here to enable software 1775 emulation of these instructions for userspace using LDXR/STXR. 1776 This feature can be controlled at runtime with the abi.swp 1777 sysctl which is disabled by default. 1778 1779 In some older versions of glibc [<=2.8] SWP is used during futex 1780 trylock() operations with the assumption that the code will not 1781 be preempted. This invalid assumption may be more likely to fail 1782 with SWP emulation enabled, leading to deadlock of the user 1783 application. 1784 1785 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1786 on an external transaction monitoring block called a global 1787 monitor to maintain update atomicity. If your system does not 1788 implement a global monitor, this option can cause programs that 1789 perform SWP operations to uncached memory to deadlock. 1790 1791 If unsure, say Y 1792 1793config CP15_BARRIER_EMULATION 1794 bool "Emulate CP15 Barrier instructions" 1795 help 1796 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1797 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1798 strongly recommended to use the ISB, DSB, and DMB 1799 instructions instead. 1800 1801 Say Y here to enable software emulation of these 1802 instructions for AArch32 userspace code. When this option is 1803 enabled, CP15 barrier usage is traced which can help 1804 identify software that needs updating. This feature can be 1805 controlled at runtime with the abi.cp15_barrier sysctl. 1806 1807 If unsure, say Y 1808 1809config SETEND_EMULATION 1810 bool "Emulate SETEND instruction" 1811 help 1812 The SETEND instruction alters the data-endianness of the 1813 AArch32 EL0, and is deprecated in ARMv8. 1814 1815 Say Y here to enable software emulation of the instruction 1816 for AArch32 userspace code. This feature can be controlled 1817 at runtime with the abi.setend sysctl. 1818 1819 Note: All the cpus on the system must have mixed endian support at EL0 1820 for this feature to be enabled. If a new CPU - which doesn't support mixed 1821 endian - is hotplugged in after this feature has been enabled, there could 1822 be unexpected results in the applications. 1823 1824 If unsure, say Y 1825endif # ARMV8_DEPRECATED 1826 1827endif # COMPAT 1828 1829menu "ARMv8.1 architectural features" 1830 1831config ARM64_HW_AFDBM 1832 bool "Support for hardware updates of the Access and Dirty page flags" 1833 default y 1834 help 1835 The ARMv8.1 architecture extensions introduce support for 1836 hardware updates of the access and dirty information in page 1837 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1838 capable processors, accesses to pages with PTE_AF cleared will 1839 set this bit instead of raising an access flag fault. 1840 Similarly, writes to read-only pages with the DBM bit set will 1841 clear the read-only bit (AP[2]) instead of raising a 1842 permission fault. 1843 1844 Kernels built with this configuration option enabled continue 1845 to work on pre-ARMv8.1 hardware and the performance impact is 1846 minimal. If unsure, say Y. 1847 1848endmenu # "ARMv8.1 architectural features" 1849 1850menu "ARMv8.2 architectural features" 1851 1852config ARM64_PMEM 1853 bool "Enable support for persistent memory" 1854 select ARCH_HAS_PMEM_API 1855 select ARCH_HAS_UACCESS_FLUSHCACHE 1856 help 1857 Say Y to enable support for the persistent memory API based on the 1858 ARMv8.2 DCPoP feature. 1859 1860 The feature is detected at runtime, and the kernel will use DC CVAC 1861 operations if DC CVAP is not supported (following the behaviour of 1862 DC CVAP itself if the system does not define a point of persistence). 1863 1864config ARM64_RAS_EXTN 1865 bool "Enable support for RAS CPU Extensions" 1866 default y 1867 help 1868 CPUs that support the Reliability, Availability and Serviceability 1869 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1870 errors, classify them and report them to software. 1871 1872 On CPUs with these extensions system software can use additional 1873 barriers to determine if faults are pending and read the 1874 classification from a new set of registers. 1875 1876 Selecting this feature will allow the kernel to use these barriers 1877 and access the new registers if the system supports the extension. 1878 Platform RAS features may additionally depend on firmware support. 1879 1880config ARM64_CNP 1881 bool "Enable support for Common Not Private (CNP) translations" 1882 default y 1883 help 1884 Common Not Private (CNP) allows translation table entries to 1885 be shared between different PEs in the same inner shareable 1886 domain, so the hardware can use this fact to optimise the 1887 caching of such entries in the TLB. 1888 1889 Selecting this option allows the CNP feature to be detected 1890 at runtime, and does not affect PEs that do not implement 1891 this feature. 1892 1893endmenu # "ARMv8.2 architectural features" 1894 1895menu "ARMv8.3 architectural features" 1896 1897config ARM64_PTR_AUTH 1898 bool "Enable support for pointer authentication" 1899 default y 1900 help 1901 Pointer authentication (part of the ARMv8.3 Extensions) provides 1902 instructions for signing and authenticating pointers against secret 1903 keys, which can be used to mitigate Return Oriented Programming (ROP) 1904 and other attacks. 1905 1906 This option enables these instructions at EL0 (i.e. for userspace). 1907 Choosing this option will cause the kernel to initialise secret keys 1908 for each process at exec() time, with these keys being 1909 context-switched along with the process. 1910 1911 The feature is detected at runtime. If the feature is not present in 1912 hardware it will not be advertised to userspace/KVM guest nor will it 1913 be enabled. 1914 1915 If the feature is present on the boot CPU but not on a late CPU, then 1916 the late CPU will be parked. Also, if the boot CPU does not have 1917 address auth and the late CPU has then the late CPU will still boot 1918 but with the feature disabled. On such a system, this option should 1919 not be selected. 1920 1921config ARM64_PTR_AUTH_KERNEL 1922 bool "Use pointer authentication for kernel" 1923 default y 1924 depends on ARM64_PTR_AUTH 1925 # Modern compilers insert a .note.gnu.property section note for PAC 1926 # which is only understood by binutils starting with version 2.33.1. 1927 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1928 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1929 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1930 help 1931 If the compiler supports the -mbranch-protection or 1932 -msign-return-address flag (e.g. GCC 7 or later), then this option 1933 will cause the kernel itself to be compiled with return address 1934 protection. In this case, and if the target hardware is known to 1935 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1936 disabled with minimal loss of protection. 1937 1938 This feature works with FUNCTION_GRAPH_TRACER option only if 1939 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1940 1941config CC_HAS_BRANCH_PROT_PAC_RET 1942 # GCC 9 or later, clang 8 or later 1943 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1944 1945config AS_HAS_CFI_NEGATE_RA_STATE 1946 # binutils 2.34+ 1947 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1948 1949endmenu # "ARMv8.3 architectural features" 1950 1951menu "ARMv8.4 architectural features" 1952 1953config ARM64_AMU_EXTN 1954 bool "Enable support for the Activity Monitors Unit CPU extension" 1955 default y 1956 help 1957 The activity monitors extension is an optional extension introduced 1958 by the ARMv8.4 CPU architecture. This enables support for version 1 1959 of the activity monitors architecture, AMUv1. 1960 1961 To enable the use of this extension on CPUs that implement it, say Y. 1962 1963 Note that for architectural reasons, firmware _must_ implement AMU 1964 support when running on CPUs that present the activity monitors 1965 extension. The required support is present in: 1966 * Version 1.5 and later of the ARM Trusted Firmware 1967 1968 For kernels that have this configuration enabled but boot with broken 1969 firmware, you may need to say N here until the firmware is fixed. 1970 Otherwise you may experience firmware panics or lockups when 1971 accessing the counter registers. Even if you are not observing these 1972 symptoms, the values returned by the register reads might not 1973 correctly reflect reality. Most commonly, the value read will be 0, 1974 indicating that the counter is not enabled. 1975 1976config ARM64_TLB_RANGE 1977 bool "Enable support for tlbi range feature" 1978 default y 1979 help 1980 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1981 range of input addresses. 1982 1983config ARM64_MPAM 1984 bool "Enable support for MPAM" 1985 select ARM64_MPAM_DRIVER 1986 select ARCH_HAS_CPU_RESCTRL 1987 help 1988 Memory System Resource Partitioning and Monitoring (MPAM) is an 1989 optional extension to the Arm architecture that allows each 1990 transaction issued to the memory system to be labelled with a 1991 Partition identifier (PARTID) and Performance Monitoring Group 1992 identifier (PMG). 1993 1994 Memory system components, such as the caches, can be configured with 1995 policies to control how much of various physical resources (such as 1996 memory bandwidth or cache memory) the transactions labelled with each 1997 PARTID can consume. Depending on the capabilities of the hardware, 1998 the PARTID and PMG can also be used as filtering criteria to measure 1999 the memory system resource consumption of different parts of a 2000 workload. 2001 2002 Use of this extension requires CPU support, support in the 2003 Memory System Components (MSC), and a description from firmware 2004 of where the MSCs are in the address space. 2005 2006 MPAM is exposed to user-space via the resctrl pseudo filesystem. 2007 2008 This option enables the extra context switch code. 2009 2010endmenu # "ARMv8.4 architectural features" 2011 2012menu "ARMv8.5 architectural features" 2013 2014config AS_HAS_ARMV8_5 2015 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2016 2017config ARM64_BTI 2018 bool "Branch Target Identification support" 2019 default y 2020 help 2021 Branch Target Identification (part of the ARMv8.5 Extensions) 2022 provides a mechanism to limit the set of locations to which computed 2023 branch instructions such as BR or BLR can jump. 2024 2025 To make use of BTI on CPUs that support it, say Y. 2026 2027 BTI is intended to provide complementary protection to other control 2028 flow integrity protection mechanisms, such as the Pointer 2029 authentication mechanism provided as part of the ARMv8.3 Extensions. 2030 For this reason, it does not make sense to enable this option without 2031 also enabling support for pointer authentication. Thus, when 2032 enabling this option you should also select ARM64_PTR_AUTH=y. 2033 2034 Userspace binaries must also be specifically compiled to make use of 2035 this mechanism. If you say N here or the hardware does not support 2036 BTI, such binaries can still run, but you get no additional 2037 enforcement of branch destinations. 2038 2039config ARM64_BTI_KERNEL 2040 bool "Use Branch Target Identification for kernel" 2041 default y 2042 depends on ARM64_BTI 2043 depends on ARM64_PTR_AUTH_KERNEL 2044 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2045 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2046 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2047 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2048 depends on !CC_IS_GCC 2049 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2050 help 2051 Build the kernel with Branch Target Identification annotations 2052 and enable enforcement of this for kernel code. When this option 2053 is enabled and the system supports BTI all kernel code including 2054 modular code must have BTI enabled. 2055 2056config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2057 # GCC 9 or later, clang 8 or later 2058 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2059 2060config ARM64_E0PD 2061 bool "Enable support for E0PD" 2062 default y 2063 help 2064 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2065 that EL0 accesses made via TTBR1 always fault in constant time, 2066 providing similar benefits to KASLR as those provided by KPTI, but 2067 with lower overhead and without disrupting legitimate access to 2068 kernel memory such as SPE. 2069 2070 This option enables E0PD for TTBR1 where available. 2071 2072config ARM64_AS_HAS_MTE 2073 # Initial support for MTE went in binutils 2.32.0, checked with 2074 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2075 # as a late addition to the final architecture spec (LDGM/STGM) 2076 # is only supported in the newer 2.32.x and 2.33 binutils 2077 # versions, hence the extra "stgm" instruction check below. 2078 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2079 2080config ARM64_MTE 2081 bool "Memory Tagging Extension support" 2082 default y 2083 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2084 depends on AS_HAS_ARMV8_5 2085 # Required for tag checking in the uaccess routines 2086 select ARCH_HAS_SUBPAGE_FAULTS 2087 select ARCH_USES_HIGH_VMA_FLAGS 2088 select ARCH_USES_PG_ARCH_2 2089 select ARCH_USES_PG_ARCH_3 2090 help 2091 Memory Tagging (part of the ARMv8.5 Extensions) provides 2092 architectural support for run-time, always-on detection of 2093 various classes of memory error to aid with software debugging 2094 to eliminate vulnerabilities arising from memory-unsafe 2095 languages. 2096 2097 This option enables the support for the Memory Tagging 2098 Extension at EL0 (i.e. for userspace). 2099 2100 Selecting this option allows the feature to be detected at 2101 runtime. Any secondary CPU not implementing this feature will 2102 not be allowed a late bring-up. 2103 2104 Userspace binaries that want to use this feature must 2105 explicitly opt in. The mechanism for the userspace is 2106 described in: 2107 2108 Documentation/arch/arm64/memory-tagging-extension.rst. 2109 2110endmenu # "ARMv8.5 architectural features" 2111 2112menu "ARMv8.7 architectural features" 2113 2114config ARM64_EPAN 2115 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2116 default y 2117 help 2118 Enhanced Privileged Access Never (EPAN) allows Privileged 2119 Access Never to be used with Execute-only mappings. 2120 2121 The feature is detected at runtime, and will remain disabled 2122 if the cpu does not implement the feature. 2123endmenu # "ARMv8.7 architectural features" 2124 2125config AS_HAS_MOPS 2126 def_bool $(as-instr,.arch_extension mops) 2127 2128menu "ARMv8.9 architectural features" 2129 2130config ARM64_POE 2131 prompt "Permission Overlay Extension" 2132 def_bool y 2133 select ARCH_USES_HIGH_VMA_FLAGS 2134 select ARCH_HAS_PKEYS 2135 help 2136 The Permission Overlay Extension is used to implement Memory 2137 Protection Keys. Memory Protection Keys provides a mechanism for 2138 enforcing page-based protections, but without requiring modification 2139 of the page tables when an application changes protection domains. 2140 2141 For details, see Documentation/core-api/protection-keys.rst 2142 2143 If unsure, say y. 2144 2145config ARCH_PKEY_BITS 2146 int 2147 default 3 2148 2149config ARM64_HAFT 2150 bool "Support for Hardware managed Access Flag for Table Descriptors" 2151 depends on ARM64_HW_AFDBM 2152 default y 2153 help 2154 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2155 Flag for Table descriptors. When enabled an architectural executed 2156 memory access will update the Access Flag in each Table descriptor 2157 which is accessed during the translation table walk and for which 2158 the Access Flag is 0. The Access Flag of the Table descriptor use 2159 the same bit of PTE_AF. 2160 2161 The feature will only be enabled if all the CPUs in the system 2162 support this feature. If unsure, say Y. 2163 2164endmenu # "ARMv8.9 architectural features" 2165 2166menu "ARMv9.4 architectural features" 2167 2168config ARM64_GCS 2169 bool "Enable support for Guarded Control Stack (GCS)" 2170 default y 2171 select ARCH_HAS_USER_SHADOW_STACK 2172 select ARCH_USES_HIGH_VMA_FLAGS 2173 help 2174 Guarded Control Stack (GCS) provides support for a separate 2175 stack with restricted access which contains only return 2176 addresses. This can be used to harden against some attacks 2177 by comparing return address used by the program with what is 2178 stored in the GCS, and may also be used to efficiently obtain 2179 the call stack for applications such as profiling. 2180 2181 The feature is detected at runtime, and will remain disabled 2182 if the system does not implement the feature. 2183 2184endmenu # "ARMv9.4 architectural features" 2185 2186config AS_HAS_LSUI 2187 def_bool $(as-instr,.arch_extension lsui) 2188 help 2189 Supported by LLVM 20+ and binutils 2.45+. 2190 2191menu "ARMv9.6 architectural features" 2192 2193config ARM64_LSUI 2194 bool "Support Unprivileged Load Store Instructions (LSUI)" 2195 default y 2196 depends on AS_HAS_LSUI && !CPU_BIG_ENDIAN 2197 help 2198 The Unprivileged Load Store Instructions (LSUI) provides 2199 variants load/store instructions that access user-space memory 2200 from the kernel without clearing PSTATE.PAN bit. 2201 2202 This feature is supported by LLVM 20+ and binutils 2.45+. 2203 2204endmenu # "ARMv9.6 architectural feature" 2205 2206config ARM64_SVE 2207 bool "ARM Scalable Vector Extension support" 2208 default y 2209 help 2210 The Scalable Vector Extension (SVE) is an extension to the AArch64 2211 execution state which complements and extends the SIMD functionality 2212 of the base architecture to support much larger vectors and to enable 2213 additional vectorisation opportunities. 2214 2215 To enable use of this extension on CPUs that implement it, say Y. 2216 2217 On CPUs that support the SVE2 extensions, this option will enable 2218 those too. 2219 2220 Note that for architectural reasons, firmware _must_ implement SVE 2221 support when running on SVE capable hardware. The required support 2222 is present in: 2223 2224 * version 1.5 and later of the ARM Trusted Firmware 2225 * the AArch64 boot wrapper since commit 5e1261e08abf 2226 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2227 2228 For other firmware implementations, consult the firmware documentation 2229 or vendor. 2230 2231 If you need the kernel to boot on SVE-capable hardware with broken 2232 firmware, you may need to say N here until you get your firmware 2233 fixed. Otherwise, you may experience firmware panics or lockups when 2234 booting the kernel. If unsure and you are not observing these 2235 symptoms, you should assume that it is safe to say Y. 2236 2237config ARM64_SME 2238 bool "ARM Scalable Matrix Extension support" 2239 default y 2240 depends on ARM64_SVE 2241 help 2242 The Scalable Matrix Extension (SME) is an extension to the AArch64 2243 execution state which utilises a substantial subset of the SVE 2244 instruction set, together with the addition of new architectural 2245 register state capable of holding two dimensional matrix tiles to 2246 enable various matrix operations. 2247 2248config ARM64_PSEUDO_NMI 2249 bool "Support for NMI-like interrupts" 2250 select ARM_GIC_V3 2251 help 2252 Adds support for mimicking Non-Maskable Interrupts through the use of 2253 GIC interrupt priority. This support requires version 3 or later of 2254 ARM GIC. 2255 2256 This high priority configuration for interrupts needs to be 2257 explicitly enabled by setting the kernel parameter 2258 "irqchip.gicv3_pseudo_nmi" to 1. 2259 2260 If unsure, say N 2261 2262if ARM64_PSEUDO_NMI 2263config ARM64_DEBUG_PRIORITY_MASKING 2264 bool "Debug interrupt priority masking" 2265 help 2266 This adds runtime checks to functions enabling/disabling 2267 interrupts when using priority masking. The additional checks verify 2268 the validity of ICC_PMR_EL1 when calling concerned functions. 2269 2270 If unsure, say N 2271endif # ARM64_PSEUDO_NMI 2272 2273config RELOCATABLE 2274 bool "Build a relocatable kernel image" if EXPERT 2275 select ARCH_HAS_RELR 2276 default y 2277 help 2278 This builds the kernel as a Position Independent Executable (PIE), 2279 which retains all relocation metadata required to relocate the 2280 kernel binary at runtime to a different virtual address than the 2281 address it was linked at. 2282 Since AArch64 uses the RELA relocation format, this requires a 2283 relocation pass at runtime even if the kernel is loaded at the 2284 same address it was linked at. 2285 2286config RANDOMIZE_BASE 2287 bool "Randomize the address of the kernel image" 2288 select RELOCATABLE 2289 help 2290 Randomizes the virtual address at which the kernel image is 2291 loaded, as a security feature that deters exploit attempts 2292 relying on knowledge of the location of kernel internals. 2293 2294 It is the bootloader's job to provide entropy, by passing a 2295 random u64 value in /chosen/kaslr-seed at kernel entry. 2296 2297 When booting via the UEFI stub, it will invoke the firmware's 2298 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2299 to the kernel proper. In addition, it will randomise the physical 2300 location of the kernel Image as well. 2301 2302 If unsure, say N. 2303 2304config RANDOMIZE_MODULE_REGION_FULL 2305 bool "Randomize the module region over a 2 GB range" 2306 depends on RANDOMIZE_BASE 2307 default y 2308 help 2309 Randomizes the location of the module region inside a 2 GB window 2310 covering the core kernel. This way, it is less likely for modules 2311 to leak information about the location of core kernel data structures 2312 but it does imply that function calls between modules and the core 2313 kernel will need to be resolved via veneers in the module PLT. 2314 2315 When this option is not set, the module region will be randomized over 2316 a limited range that contains the [_stext, _etext] interval of the 2317 core kernel, so branch relocations are almost always in range unless 2318 the region is exhausted. In this particular case of region 2319 exhaustion, modules might be able to fall back to a larger 2GB area. 2320 2321config CC_HAVE_STACKPROTECTOR_SYSREG 2322 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2323 2324config STACKPROTECTOR_PER_TASK 2325 def_bool y 2326 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2327 2328config UNWIND_PATCH_PAC_INTO_SCS 2329 bool "Enable shadow call stack dynamically using code patching" 2330 depends on CC_IS_CLANG 2331 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2332 depends on SHADOW_CALL_STACK 2333 select UNWIND_TABLES 2334 select DYNAMIC_SCS 2335 2336config ARM64_CONTPTE 2337 bool "Contiguous PTE mappings for user memory" if EXPERT 2338 depends on TRANSPARENT_HUGEPAGE 2339 default y 2340 help 2341 When enabled, user mappings are configured using the PTE contiguous 2342 bit, for any mappings that meet the size and alignment requirements. 2343 This reduces TLB pressure and improves performance. 2344 2345endmenu # "Kernel Features" 2346 2347menu "Boot options" 2348 2349config ARM64_ACPI_PARKING_PROTOCOL 2350 bool "Enable support for the ARM64 ACPI parking protocol" 2351 depends on ACPI 2352 help 2353 Enable support for the ARM64 ACPI parking protocol. If disabled 2354 the kernel will not allow booting through the ARM64 ACPI parking 2355 protocol even if the corresponding data is present in the ACPI 2356 MADT table. 2357 2358config CMDLINE 2359 string "Default kernel command string" 2360 default "" 2361 help 2362 Provide a set of default command-line options at build time by 2363 entering them here. As a minimum, you should specify the 2364 root device (e.g. root=/dev/nfs). 2365 2366choice 2367 prompt "Kernel command line type" 2368 depends on CMDLINE != "" 2369 default CMDLINE_FROM_BOOTLOADER 2370 help 2371 Choose how the kernel will handle the provided default kernel 2372 command line string. 2373 2374config CMDLINE_FROM_BOOTLOADER 2375 bool "Use bootloader kernel arguments if available" 2376 help 2377 Uses the command-line options passed by the boot loader. If 2378 the boot loader doesn't provide any, the default kernel command 2379 string provided in CMDLINE will be used. 2380 2381config CMDLINE_FORCE 2382 bool "Always use the default kernel command string" 2383 help 2384 Always use the default kernel command string, even if the boot 2385 loader passes other arguments to the kernel. 2386 This is useful if you cannot or don't want to change the 2387 command-line options your boot loader passes to the kernel. 2388 2389endchoice 2390 2391config EFI_STUB 2392 bool 2393 2394config EFI 2395 bool "UEFI runtime support" 2396 depends on OF && !CPU_BIG_ENDIAN 2397 depends on KERNEL_MODE_NEON 2398 select ARCH_SUPPORTS_ACPI 2399 select LIBFDT 2400 select UCS2_STRING 2401 select EFI_PARAMS_FROM_FDT 2402 select EFI_RUNTIME_WRAPPERS 2403 select EFI_STUB 2404 select EFI_GENERIC_STUB 2405 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2406 default y 2407 help 2408 This option provides support for runtime services provided 2409 by UEFI firmware (such as non-volatile variables, realtime 2410 clock, and platform reset). A UEFI stub is also provided to 2411 allow the kernel to be booted as an EFI application. This 2412 is only useful on systems that have UEFI firmware. 2413 2414config COMPRESSED_INSTALL 2415 bool "Install compressed image by default" 2416 help 2417 This makes the regular "make install" install the compressed 2418 image we built, not the legacy uncompressed one. 2419 2420 You can check that a compressed image works for you by doing 2421 "make zinstall" first, and verifying that everything is fine 2422 in your environment before making "make install" do this for 2423 you. 2424 2425config DMI 2426 bool "Enable support for SMBIOS (DMI) tables" 2427 depends on EFI 2428 default y 2429 help 2430 This enables SMBIOS/DMI feature for systems. 2431 2432 This option is only useful on systems that have UEFI firmware. 2433 However, even with this option, the resultant kernel should 2434 continue to boot on existing non-UEFI platforms. 2435 2436endmenu # "Boot options" 2437 2438menu "Power management options" 2439 2440source "kernel/power/Kconfig" 2441 2442config ARCH_HIBERNATION_POSSIBLE 2443 def_bool y 2444 depends on CPU_PM 2445 2446config ARCH_HIBERNATION_HEADER 2447 def_bool y 2448 depends on HIBERNATION 2449 2450config ARCH_SUSPEND_POSSIBLE 2451 def_bool y 2452 2453endmenu # "Power management options" 2454 2455menu "CPU Power Management" 2456 2457source "drivers/cpuidle/Kconfig" 2458 2459source "drivers/cpufreq/Kconfig" 2460 2461endmenu # "CPU Power Management" 2462 2463source "drivers/acpi/Kconfig" 2464 2465source "arch/arm64/kvm/Kconfig" 2466 2467source "kernel/livepatch/Kconfig" 2468