1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Header file for Analogix DP (Display Port) core interface driver. 4 * 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 */ 8 9 #ifndef _ANALOGIX_DP_CORE_H 10 #define _ANALOGIX_DP_CORE_H 11 12 #include <drm/display/drm_dp_helper.h> 13 #include <drm/drm_crtc.h> 14 #include <drm/drm_bridge.h> 15 16 #define DP_TIMEOUT_LOOP_COUNT 100 17 #define MAX_CR_LOOP 5 18 #define MAX_EQ_LOOP 5 19 #define MAX_PLL_LOCK_LOOP 5 20 21 /* Training takes 22ms if AUX channel comm fails. Use this as retry interval */ 22 #define DP_TIMEOUT_TRAINING_US 22000 23 #define DP_TIMEOUT_PSR_LOOP_MS 300 24 25 /* DP_MAX_LANE_COUNT */ 26 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 27 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 28 29 /* DP_LANE_COUNT_SET */ 30 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 31 32 /* DP_TRAINING_LANE0_SET */ 33 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 34 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 35 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 36 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 37 38 struct gpio_desc; 39 40 enum link_lane_count_type { 41 LANE_COUNT1 = 1, 42 LANE_COUNT2 = 2, 43 LANE_COUNT4 = 4 44 }; 45 46 enum link_training_state { 47 START, 48 CLOCK_RECOVERY, 49 EQUALIZER_TRAINING, 50 FINISHED, 51 FAILED 52 }; 53 54 enum voltage_swing_level { 55 VOLTAGE_LEVEL_0, 56 VOLTAGE_LEVEL_1, 57 VOLTAGE_LEVEL_2, 58 VOLTAGE_LEVEL_3, 59 }; 60 61 enum pre_emphasis_level { 62 PRE_EMPHASIS_LEVEL_0, 63 PRE_EMPHASIS_LEVEL_1, 64 PRE_EMPHASIS_LEVEL_2, 65 PRE_EMPHASIS_LEVEL_3, 66 }; 67 68 enum pattern_set { 69 PRBS7, 70 D10_2, 71 TRAINING_PTN1, 72 TRAINING_PTN2, 73 DP_NONE 74 }; 75 76 enum color_space { 77 COLOR_RGB, 78 COLOR_YCBCR422, 79 COLOR_YCBCR444 80 }; 81 82 enum color_depth { 83 COLOR_6, 84 COLOR_8, 85 COLOR_10, 86 COLOR_12 87 }; 88 89 enum color_coefficient { 90 COLOR_YCBCR601, 91 COLOR_YCBCR709 92 }; 93 94 enum dynamic_range { 95 VESA, 96 CEA 97 }; 98 99 enum clock_recovery_m_value_type { 100 CALCULATED_M, 101 REGISTER_M 102 }; 103 104 enum video_timing_recognition_type { 105 VIDEO_TIMING_FROM_CAPTURE, 106 VIDEO_TIMING_FROM_REGISTER 107 }; 108 109 enum analog_power_block { 110 AUX_BLOCK, 111 CH0_BLOCK, 112 CH1_BLOCK, 113 CH2_BLOCK, 114 CH3_BLOCK, 115 ANALOG_TOTAL, 116 POWER_ALL 117 }; 118 119 enum dp_irq_type { 120 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 121 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 122 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 123 DP_IRQ_TYPE_UNKNOWN = BIT(3), 124 }; 125 126 struct video_info { 127 char *name; 128 129 bool h_sync_polarity; 130 bool v_sync_polarity; 131 bool interlaced; 132 133 enum color_space color_space; 134 enum dynamic_range dynamic_range; 135 enum color_coefficient ycbcr_coeff; 136 enum color_depth color_depth; 137 138 int max_link_rate; 139 enum link_lane_count_type max_lane_count; 140 }; 141 142 struct link_train { 143 int eq_loop; 144 int cr_loop[4]; 145 146 u8 link_rate; 147 u8 lane_count; 148 u8 training_lane[4]; 149 150 enum link_training_state lt_state; 151 }; 152 153 struct analogix_dp_device { 154 struct drm_encoder *encoder; 155 struct device *dev; 156 struct drm_device *drm_dev; 157 struct drm_connector connector; 158 struct drm_bridge bridge; 159 struct drm_dp_aux aux; 160 struct clk *clock; 161 unsigned int irq; 162 void __iomem *reg_base; 163 164 struct video_info video_info; 165 struct link_train link_train; 166 struct phy *phy; 167 int dpms_mode; 168 struct gpio_desc *hpd_gpiod; 169 bool force_hpd; 170 bool fast_train_enable; 171 bool psr_supported; 172 173 struct analogix_dp_plat_data *plat_data; 174 }; 175 176 /* analogix_dp_reg.c */ 177 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 178 void analogix_dp_stop_video(struct analogix_dp_device *dp); 179 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); 180 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 181 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 182 void analogix_dp_reset(struct analogix_dp_device *dp); 183 void analogix_dp_swreset(struct analogix_dp_device *dp); 184 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 185 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 186 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 187 int analogix_dp_wait_pll_locked(struct analogix_dp_device *dp); 188 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 189 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 190 enum analog_power_block block, 191 bool enable); 192 int analogix_dp_init_analog_func(struct analogix_dp_device *dp); 193 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 194 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 195 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 196 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 197 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 198 void analogix_dp_init_aux(struct analogix_dp_device *dp); 199 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); 200 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 201 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 202 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 203 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 204 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 205 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 206 bool enable); 207 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 208 enum pattern_set pattern); 209 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); 210 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); 211 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 212 void analogix_dp_init_video(struct analogix_dp_device *dp); 213 214 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 215 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 216 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 217 enum clock_recovery_m_value_type type, 218 u32 m_value, 219 u32 n_value); 220 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 221 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 222 bool enable); 223 void analogix_dp_start_video(struct analogix_dp_device *dp); 224 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 225 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 226 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 227 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 228 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp); 229 int analogix_dp_send_psr_spd(struct analogix_dp_device *dp, 230 struct dp_sdp *vsc, bool blocking); 231 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, 232 struct drm_dp_aux_msg *msg); 233 234 #endif /* _ANALOGIX_DP_CORE_H */ 235