1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 #include "display/intel_display_reg_defs.h" 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * File Layout 38 * ~~~~~~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to reuse existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 #define GU_CNTL _MMIO(0x101010) 120 #define LMEM_INIT REG_BIT(7) 121 #define DRIVERFLR REG_BIT(31) 122 #define GU_DEBUG _MMIO(0x101018) 123 #define DRIVERFLR_STATUS REG_BIT(31) 124 125 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 126 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 127 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 128 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 129 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 130 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 131 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 132 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 133 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 134 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 135 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 136 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 137 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 138 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 139 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 140 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 141 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 142 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 143 144 /* 145 * Reset registers 146 */ 147 #define DEBUG_RESET_I830 _MMIO(0x6070) 148 #define DEBUG_RESET_FULL (1 << 7) 149 #define DEBUG_RESET_RENDER (1 << 8) 150 #define DEBUG_RESET_DISPLAY (1 << 9) 151 152 /* 153 * IOSF sideband 154 */ 155 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 156 #define IOSF_DEVFN_SHIFT 24 157 #define IOSF_OPCODE_SHIFT 16 158 #define IOSF_PORT_SHIFT 8 159 #define IOSF_BYTE_ENABLES_SHIFT 4 160 #define IOSF_BAR_SHIFT 1 161 #define IOSF_SB_BUSY (1 << 0) 162 #define IOSF_PORT_BUNIT 0x03 163 #define IOSF_PORT_PUNIT 0x04 164 #define IOSF_PORT_NC 0x11 165 #define IOSF_PORT_DPIO 0x12 166 #define IOSF_PORT_GPIO_NC 0x13 167 #define IOSF_PORT_CCK 0x14 168 #define IOSF_PORT_DPIO_2 0x1a 169 #define IOSF_PORT_FLISDSI 0x1b 170 #define IOSF_PORT_GPIO_SC 0x48 171 #define IOSF_PORT_GPIO_SUS 0xa8 172 #define IOSF_PORT_CCU 0xa9 173 #define CHV_IOSF_PORT_GPIO_N 0x13 174 #define CHV_IOSF_PORT_GPIO_SE 0x48 175 #define CHV_IOSF_PORT_GPIO_E 0xa8 176 #define CHV_IOSF_PORT_GPIO_SW 0xb2 177 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 178 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 179 180 /* DPIO registers */ 181 #define DPIO_DEVFN 0 182 183 /* 184 * Fence registers 185 * [0-7] @ 0x2000 gen2,gen3 186 * [8-15] @ 0x3000 945,g33,pnv 187 * 188 * [0-15] @ 0x3000 gen4,gen5 189 * 190 * [0-15] @ 0x100000 gen6,vlv,chv 191 * [0-31] @ 0x100000 gen7+ 192 */ 193 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 194 #define I830_FENCE_START_MASK 0x07f80000 195 #define I830_FENCE_TILING_Y_SHIFT 12 196 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 197 #define I830_FENCE_PITCH_SHIFT 4 198 #define I830_FENCE_REG_VALID (1 << 0) 199 #define I915_FENCE_MAX_PITCH_VAL 4 200 #define I830_FENCE_MAX_PITCH_VAL 6 201 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 202 203 #define I915_FENCE_START_MASK 0x0ff00000 204 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 205 206 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 207 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 208 #define I965_FENCE_PITCH_SHIFT 2 209 #define I965_FENCE_TILING_Y_SHIFT 1 210 #define I965_FENCE_REG_VALID (1 << 0) 211 #define I965_FENCE_MAX_PITCH_VAL 0x0400 212 213 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 214 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 215 #define GEN6_FENCE_PITCH_SHIFT 32 216 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 217 218 219 /* control register for cpu gtt access */ 220 #define TILECTL _MMIO(0x101000) 221 #define TILECTL_SWZCTL (1 << 0) 222 #define TILECTL_TLBPF (1 << 1) 223 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 224 #define TILECTL_BACKSNOOP_DIS (1 << 3) 225 226 /* 227 * Instruction and interrupt control regs 228 */ 229 #define PGTBL_CTL _MMIO(0x02020) 230 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 231 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 232 #define PGTBL_ER _MMIO(0x02024) 233 #define PRB0_BASE (0x2030 - 0x30) 234 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 235 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 236 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 237 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 238 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 239 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 240 #define RENDER_RING_BASE 0x02000 241 #define BSD_RING_BASE 0x04000 242 #define GEN6_BSD_RING_BASE 0x12000 243 #define GEN8_BSD2_RING_BASE 0x1c000 244 #define GEN11_BSD_RING_BASE 0x1c0000 245 #define GEN11_BSD2_RING_BASE 0x1c4000 246 #define GEN11_BSD3_RING_BASE 0x1d0000 247 #define GEN11_BSD4_RING_BASE 0x1d4000 248 #define XEHP_BSD5_RING_BASE 0x1e0000 249 #define XEHP_BSD6_RING_BASE 0x1e4000 250 #define XEHP_BSD7_RING_BASE 0x1f0000 251 #define XEHP_BSD8_RING_BASE 0x1f4000 252 #define VEBOX_RING_BASE 0x1a000 253 #define GEN11_VEBOX_RING_BASE 0x1c8000 254 #define GEN11_VEBOX2_RING_BASE 0x1d8000 255 #define XEHP_VEBOX3_RING_BASE 0x1e8000 256 #define XEHP_VEBOX4_RING_BASE 0x1f8000 257 #define MTL_GSC_RING_BASE 0x11a000 258 #define GEN12_COMPUTE0_RING_BASE 0x1a000 259 #define GEN12_COMPUTE1_RING_BASE 0x1c000 260 #define GEN12_COMPUTE2_RING_BASE 0x1e000 261 #define GEN12_COMPUTE3_RING_BASE 0x26000 262 #define BLT_RING_BASE 0x22000 263 #define XEHPC_BCS1_RING_BASE 0x3e0000 264 #define XEHPC_BCS2_RING_BASE 0x3e2000 265 #define XEHPC_BCS3_RING_BASE 0x3e4000 266 #define XEHPC_BCS4_RING_BASE 0x3e6000 267 #define XEHPC_BCS5_RING_BASE 0x3e8000 268 #define XEHPC_BCS6_RING_BASE 0x3ea000 269 #define XEHPC_BCS7_RING_BASE 0x3ec000 270 #define XEHPC_BCS8_RING_BASE 0x3ee000 271 #define DG1_GSC_HECI1_BASE 0x00258000 272 #define DG1_GSC_HECI2_BASE 0x00259000 273 #define DG2_GSC_HECI1_BASE 0x00373000 274 #define DG2_GSC_HECI2_BASE 0x00374000 275 #define MTL_GSC_HECI1_BASE 0x00116000 276 #define MTL_GSC_HECI2_BASE 0x00117000 277 278 #define HECI_H_CSR(base) _MMIO((base) + 0x4) 279 #define HECI_H_CSR_IE REG_BIT(0) 280 #define HECI_H_CSR_IS REG_BIT(1) 281 #define HECI_H_CSR_IG REG_BIT(2) 282 #define HECI_H_CSR_RDY REG_BIT(3) 283 #define HECI_H_CSR_RST REG_BIT(4) 284 285 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c) 286 #define HECI_H_GS1_ER_PREP REG_BIT(0) 287 288 /* 289 * The FWSTS register values are FW defined and can be different between 290 * HECI1 and HECI2 291 */ 292 #define HECI_FWSTS1 0xc40 293 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0) 294 #define HECI1_FWSTS1_CURRENT_STATE_RESET 0 295 #define HECI1_FWSTS1_PROXY_STATE_NORMAL 5 296 #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9) 297 #define HECI_FWSTS2 0xc48 298 #define HECI_FWSTS3 0xc60 299 #define HECI_FWSTS4 0xc64 300 #define HECI_FWSTS5 0xc68 301 #define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19) 302 #define HECI_FWSTS6 0xc6c 303 304 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */ 305 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \ 306 HECI_FWSTS1, \ 307 HECI_FWSTS2, \ 308 HECI_FWSTS3, \ 309 HECI_FWSTS4, \ 310 HECI_FWSTS5, \ 311 HECI_FWSTS6)) 312 313 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 314 #define GTT_CACHE_EN_ALL 0xF0007FFF 315 #define GEN7_WR_WATERMARK _MMIO(0x4028) 316 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 317 #define ARB_MODE _MMIO(0x4030) 318 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 319 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 320 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 321 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 322 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 323 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 324 #define GEN7_LRA_LIMITS_REG_NUM 13 325 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 326 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 327 328 #define FPGA_DBG _MMIO(0x42300) 329 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 330 331 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 332 #define CLAIM_ER_CLR REG_BIT(31) 333 #define CLAIM_ER_OVERFLOW REG_BIT(16) 334 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 335 336 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 337 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 338 #define GEN2_IER _MMIO(0x20a0) 339 #define GEN2_IIR _MMIO(0x20a4) 340 #define GEN2_IMR _MMIO(0x20a8) 341 #define GEN2_ISR _MMIO(0x20ac) 342 343 #define GEN2_IRQ_REGS I915_IRQ_REGS(GEN2_IMR, \ 344 GEN2_IER, \ 345 GEN2_IIR) 346 347 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 348 #define GINT_DIS (1 << 22) 349 #define GCFG_DIS (1 << 8) 350 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 351 352 #define EIR _MMIO(0x20b0) 353 #define EMR _MMIO(0x20b4) 354 #define ESR _MMIO(0x20b8) 355 #define GM45_ERROR_PAGE_TABLE (1 << 5) 356 #define GM45_ERROR_MEM_PRIV (1 << 4) 357 #define I915_ERROR_PAGE_TABLE (1 << 4) 358 #define GM45_ERROR_CP_PRIV (1 << 3) 359 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 360 #define I915_ERROR_INSTRUCTION (1 << 0) 361 362 #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR) 363 364 #define MEM_MODE _MMIO(0x20cc) 365 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 366 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 367 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 368 #define MM_BURST_LENGTH 0x00700000 369 #define MM_FIFO_WATERMARK 0x0001F000 370 #define LM_BURST_LENGTH 0x00000700 371 #define LM_FIFO_WATERMARK 0x0000001F 372 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 373 374 /* 375 * Make render/texture TLB fetches lower priority than associated data 376 * fetches. This is not turned on by default. 377 */ 378 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 379 380 /* Isoch request wait on GTT enable (Display A/B/C streams). 381 * Make isoch requests stall on the TLB update. May cause 382 * display underruns (test mode only) 383 */ 384 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 385 386 /* Block grant count for isoch requests when block count is 387 * set to a finite value. 388 */ 389 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 390 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 391 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 392 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 393 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 394 395 /* Enable render writes to complete in C2/C3/C4 power states. 396 * If this isn't enabled, render writes are prevented in low 397 * power states. That seems bad to me. 398 */ 399 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 400 401 /* This acknowledges an async flip immediately instead 402 * of waiting for 2TLB fetches. 403 */ 404 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 405 406 /* Enables non-sequential data reads through arbiter 407 */ 408 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 409 410 /* Disable FSB snooping of cacheable write cycles from binner/render 411 * command stream 412 */ 413 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 414 415 /* Arbiter time slice for non-isoch streams */ 416 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 417 #define MI_ARB_TIME_SLICE_1 (0 << 5) 418 #define MI_ARB_TIME_SLICE_2 (1 << 5) 419 #define MI_ARB_TIME_SLICE_4 (2 << 5) 420 #define MI_ARB_TIME_SLICE_6 (3 << 5) 421 #define MI_ARB_TIME_SLICE_8 (4 << 5) 422 #define MI_ARB_TIME_SLICE_10 (5 << 5) 423 #define MI_ARB_TIME_SLICE_14 (6 << 5) 424 #define MI_ARB_TIME_SLICE_16 (7 << 5) 425 426 /* Low priority grace period page size */ 427 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 428 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 429 430 /* Disable display A/B trickle feed */ 431 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 432 433 /* Set display plane priority */ 434 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 435 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 436 437 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 438 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 439 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 440 441 /* On modern GEN architectures interrupt control consists of two sets 442 * of registers. The first set pertains to the ring generating the 443 * interrupt. The second control is for the functional block generating the 444 * interrupt. These are PM, GT, DE, etc. 445 * 446 * Luckily *knocks on wood* all the ring interrupt bits match up with the 447 * GT interrupt bits, so we don't need to duplicate the defines. 448 * 449 * These defines should cover us well from SNB->HSW with minor exceptions 450 * it can also work on ILK. 451 */ 452 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 453 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 454 #define GT_BLT_USER_INTERRUPT (1 << 22) 455 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 456 #define GT_BSD_USER_INTERRUPT (1 << 12) 457 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 458 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 459 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 460 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 461 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 462 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 463 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 464 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 465 #define GT_RENDER_USER_INTERRUPT (1 << 0) 466 467 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 468 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 469 470 #define GT_PARITY_ERROR(dev_priv) \ 471 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 472 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 473 474 /* These are all the "old" interrupts */ 475 #define ILK_BSD_USER_INTERRUPT (1 << 5) 476 477 #define GEN6_BSD_RNCID _MMIO(0x12198) 478 479 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 480 #define GEN7_FF_SCHED_MASK 0x0077070 481 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 482 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 483 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 484 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 485 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 486 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 487 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 488 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 489 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 490 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 491 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 492 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 493 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 494 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 495 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 496 497 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 498 #define ILK_FBCQ_DIS REG_BIT(22) 499 #define ILK_PABSTRETCH_DIS REG_BIT(21) 500 #define ILK_SABSTRETCH_DIS REG_BIT(20) 501 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 502 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 503 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 504 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 505 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 506 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 507 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 508 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 509 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 510 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 511 512 #define DPLL_TEST _MMIO(0x606c) 513 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 514 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 515 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 516 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 517 #define DPLLB_TEST_N_BYPASS (1 << 19) 518 #define DPLLB_TEST_M_BYPASS (1 << 18) 519 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 520 #define DPLLA_TEST_N_BYPASS (1 << 3) 521 #define DPLLA_TEST_M_BYPASS (1 << 2) 522 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 523 524 #define D_STATE _MMIO(0x6104) 525 #define DSTATE_GFX_RESET_I830 (1 << 6) 526 #define DSTATE_PLL_D3_OFF (1 << 3) 527 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 528 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 529 530 #define RENCLK_GATE_D1 _MMIO(0x6204) 531 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 532 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 533 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 534 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 535 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 536 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 537 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 538 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 539 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 540 /* This bit must be unset on 855,865 */ 541 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 542 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 543 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 544 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 545 /* This bit must be set on 855,865. */ 546 # define SV_CLOCK_GATE_DISABLE (1 << 0) 547 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 548 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 549 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 550 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 551 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 552 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 553 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 554 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 555 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 556 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 557 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 558 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 559 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 560 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 561 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 562 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 563 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 564 565 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 566 /* This bit must always be set on 965G/965GM */ 567 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 568 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 569 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 570 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 571 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 572 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 573 /* This bit must always be set on 965G */ 574 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 575 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 576 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 577 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 578 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 579 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 580 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 581 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 582 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 583 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 584 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 585 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 586 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 587 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 588 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 589 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 590 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 591 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 592 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 593 594 #define RENCLK_GATE_D2 _MMIO(0x6208) 595 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 596 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 597 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 598 599 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 600 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 601 602 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 603 #define DEUC _MMIO(0x6214) /* CRL only */ 604 605 #define BXT_RP_STATE_CAP _MMIO(0x138170) 606 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 607 608 #define MTL_RP_STATE_CAP _MMIO(0x138000) 609 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) 610 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 611 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 612 613 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) 614 #define MTL_MPE_FREQUENCY _MMIO(0x13802c) 615 #define MTL_RPE_MASK REG_GENMASK(8, 0) 616 617 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 618 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 619 #define PROCHOT_MASK REG_BIT(0) 620 #define THERMAL_LIMIT_MASK REG_BIT(1) 621 #define RATL_MASK REG_BIT(5) 622 #define VR_THERMALERT_MASK REG_BIT(6) 623 #define VR_TDC_MASK REG_BIT(7) 624 #define POWER_LIMIT_4_MASK REG_BIT(8) 625 #define POWER_LIMIT_1_MASK REG_BIT(10) 626 #define POWER_LIMIT_2_MASK REG_BIT(11) 627 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) 628 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) 629 630 #define CHV_CLK_CTL1 _MMIO(0x101100) 631 #define VLV_CLK_CTL2 _MMIO(0x101104) 632 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 633 634 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 635 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 636 #define PIPEB_HLINE_INT_EN REG_BIT(28) 637 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 638 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 639 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 640 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 641 #define PIPE_PSR_INT_EN REG_BIT(22) 642 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 643 #define PIPEA_HLINE_INT_EN REG_BIT(20) 644 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 645 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 646 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 647 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 648 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 649 #define PIPEC_HLINE_INT_EN REG_BIT(12) 650 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 651 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 652 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 653 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 654 655 #define PCH_3DCGDIS0 _MMIO(0x46020) 656 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 657 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 658 659 #define PCH_3DCGDIS1 _MMIO(0x46024) 660 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 661 662 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 663 #define MASTER_INTERRUPT_ENABLE (1 << 31) 664 665 #define GTISR _MMIO(0x44010) 666 #define GTIMR _MMIO(0x44014) 667 #define GTIIR _MMIO(0x44018) 668 #define GTIER _MMIO(0x4401c) 669 670 #define GT_IRQ_REGS I915_IRQ_REGS(GTIMR, \ 671 GTIER, \ 672 GTIIR) 673 674 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 675 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 676 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 677 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 678 679 #define GEN8_GT_IRQ_REGS(which) I915_IRQ_REGS(GEN8_GT_IMR(which), \ 680 GEN8_GT_IER(which), \ 681 GEN8_GT_IIR(which)) 682 683 #define GEN8_RCS_IRQ_SHIFT 0 684 #define GEN8_BCS_IRQ_SHIFT 16 685 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 686 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 687 #define GEN8_VECS_IRQ_SHIFT 0 688 #define GEN8_WD_IRQ_SHIFT 16 689 690 #define GEN8_PCU_ISR _MMIO(0x444e0) 691 #define GEN8_PCU_IMR _MMIO(0x444e4) 692 #define GEN8_PCU_IIR _MMIO(0x444e8) 693 #define GEN8_PCU_IER _MMIO(0x444ec) 694 695 #define GEN8_PCU_IRQ_REGS I915_IRQ_REGS(GEN8_PCU_IMR, \ 696 GEN8_PCU_IER, \ 697 GEN8_PCU_IIR) 698 699 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 700 #define DG1_MSTR_IRQ REG_BIT(31) 701 #define DG1_MSTR_TILE(t) REG_BIT(t) 702 703 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 704 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 705 #define ILK_ELPIN_409_SELECT REG_BIT(25) 706 #define ILK_DPARB_GATE REG_BIT(22) 707 #define ILK_VSDPFD_FULL REG_BIT(21) 708 709 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 710 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28) 711 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9) 712 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8) 713 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7) 714 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5) 715 716 #define IVB_CHICKEN3 _MMIO(0x4200c) 717 #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) 718 #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) 719 720 #define CHICKEN_PAR2_1 _MMIO(0x42090) 721 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) 722 723 #define VLV_PMWGICZ _MMIO(0x1300a4) 724 725 #define HSW_EDRAM_CAP _MMIO(0x120010) 726 #define EDRAM_ENABLED 0x1 727 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 728 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 729 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 730 731 #define GEN6_PCODE_DATA _MMIO(0x138128) 732 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 733 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 734 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 735 736 #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914) 737 #define STOLEN_ACCESS_ALLOWED 0x1 738 739 /* IVYBRIDGE DPF */ 740 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 741 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 742 #define GEN7_PARITY_ERROR_VALID (1 << 13) 743 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 744 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 745 #define GEN7_PARITY_ERROR_ROW(reg) \ 746 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 747 #define GEN7_PARITY_ERROR_BANK(reg) \ 748 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 749 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 750 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 751 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 752 753 /* These are the 4 32-bit write offset registers for each stream 754 * output buffer. It determines the offset from the 755 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 756 */ 757 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 758 759 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 760 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 761 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 762 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 763 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 764 765 #define GGC _MMIO(0x108040) 766 #define GMS_MASK REG_GENMASK(15, 8) 767 #define GGMS_MASK REG_GENMASK(7, 6) 768 769 #define GEN6_GSMBASE _MMIO(0x108100) 770 #define GEN6_DSMBASE _MMIO(0x1080C0) 771 #define GEN6_BDSM_MASK REG_GENMASK64(31, 20) 772 #define GEN11_BDSM_MASK REG_GENMASK64(63, 20) 773 774 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 775 #define SGSI_SIDECLK_DIS REG_BIT(17) 776 #define SGGI_DIS REG_BIT(15) 777 #define SGR_DIS REG_BIT(13) 778 779 #define MTL_MEDIA_GSI_BASE 0x380000 780 781 #define DSPCLK_GATE_D _MMIO(0x6200) 782 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 783 784 #endif /* _I915_REG_H_ */ 785