1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2017 Intel Corporation */
3
4 #ifndef __IPU3_CIO2_H
5 #define __IPU3_CIO2_H
6
7 #include <linux/bits.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/kernel.h>
10 #include <linux/mutex.h>
11 #include <linux/types.h>
12
13 #include <asm/page.h>
14
15 #include <media/media-device.h>
16 #include <media/media-entity.h>
17 #include <media/v4l2-async.h>
18 #include <media/v4l2-dev.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-subdev.h>
21 #include <media/videobuf2-core.h>
22 #include <media/videobuf2-v4l2.h>
23
24 struct cio2_fbpt_entry; /* defined here, after the first usage */
25 struct pci_dev;
26
27 #define CIO2_NAME "ipu3-cio2"
28 #define CIO2_DEVICE_NAME "Intel IPU3 CIO2"
29 #define CIO2_ENTITY_NAME "ipu3-csi2"
30 #define CIO2_PCI_ID 0x9d32
31 #define CIO2_PCI_BAR 0
32 #define CIO2_DMA_MASK DMA_BIT_MASK(39)
33
34 #define CIO2_IMAGE_MAX_WIDTH 4224U
35 #define CIO2_IMAGE_MAX_HEIGHT 3136U
36
37 /* 32MB = 8xFBPT_entry */
38 #define CIO2_MAX_LOPS 8
39 #define CIO2_MAX_BUFFERS (PAGE_SIZE / 16 / CIO2_MAX_LOPS)
40 #define CIO2_LOP_ENTRIES (PAGE_SIZE / sizeof(u32))
41
42 #define CIO2_PAD_SINK 0U
43 #define CIO2_PAD_SOURCE 1U
44 #define CIO2_PADS 2U
45
46 #define CIO2_NUM_DMA_CHAN 20U
47 #define CIO2_NUM_PORTS 4U /* DPHYs */
48
49 /* 1 for each sensor */
50 #define CIO2_QUEUES CIO2_NUM_PORTS
51
52 /* Register and bit field definitions */
53 #define CIO2_REG_PIPE_BASE(n) ((n) * 0x0400) /* n = 0..3 */
54 #define CIO2_REG_CSIRX_BASE 0x000
55 #define CIO2_REG_MIPIBE_BASE 0x100
56 #define CIO2_REG_PIXELGEN_BAS 0x200
57 #define CIO2_REG_IRQCTRL_BASE 0x300
58 #define CIO2_REG_GPREG_BASE 0x1000
59
60 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_CSIRX_BASE */
61 #define CIO2_REG_CSIRX_ENABLE (CIO2_REG_CSIRX_BASE + 0x0)
62 #define CIO2_REG_CSIRX_NOF_ENABLED_LANES (CIO2_REG_CSIRX_BASE + 0x4)
63 #define CIO2_REG_CSIRX_SP_IF_CONFIG (CIO2_REG_CSIRX_BASE + 0x10)
64 #define CIO2_REG_CSIRX_LP_IF_CONFIG (CIO2_REG_CSIRX_BASE + 0x14)
65 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT 0x00
66 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT_VC_INACTIVE 0x01
67 #define CIO2_CSIRX_IF_CONFIG_PASS 0x02
68 #define CIO2_CSIRX_IF_CONFIG_FLAG_ERROR BIT(2)
69 #define CIO2_REG_CSIRX_STATUS (CIO2_REG_CSIRX_BASE + 0x18)
70 #define CIO2_REG_CSIRX_STATUS_DLANE_HS (CIO2_REG_CSIRX_BASE + 0x1c)
71 #define CIO2_CSIRX_STATUS_DLANE_HS_MASK 0xff
72 #define CIO2_REG_CSIRX_STATUS_DLANE_LP (CIO2_REG_CSIRX_BASE + 0x20)
73 #define CIO2_CSIRX_STATUS_DLANE_LP_MASK 0xffffff
74 /* Termination enable and settle in 0.0625ns units, lane=0..3 or -1 for clock */
75 #define CIO2_REG_CSIRX_DLY_CNT_TERMEN(lane) \
76 (CIO2_REG_CSIRX_BASE + 0x2c + 8 * (lane))
77 #define CIO2_REG_CSIRX_DLY_CNT_SETTLE(lane) \
78 (CIO2_REG_CSIRX_BASE + 0x30 + 8 * (lane))
79 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_MIPIBE_BASE */
80 #define CIO2_REG_MIPIBE_ENABLE (CIO2_REG_MIPIBE_BASE + 0x0)
81 #define CIO2_REG_MIPIBE_STATUS (CIO2_REG_MIPIBE_BASE + 0x4)
82 #define CIO2_REG_MIPIBE_COMP_FORMAT(vc) \
83 (CIO2_REG_MIPIBE_BASE + 0x8 + 0x4 * (vc))
84 #define CIO2_REG_MIPIBE_FORCE_RAW8 (CIO2_REG_MIPIBE_BASE + 0x20)
85 #define CIO2_REG_MIPIBE_FORCE_RAW8_ENABLE BIT(0)
86 #define CIO2_REG_MIPIBE_FORCE_RAW8_USE_TYPEID BIT(1)
87 #define CIO2_REG_MIPIBE_FORCE_RAW8_TYPEID_SHIFT 2U
88
89 #define CIO2_REG_MIPIBE_IRQ_STATUS (CIO2_REG_MIPIBE_BASE + 0x24)
90 #define CIO2_REG_MIPIBE_IRQ_CLEAR (CIO2_REG_MIPIBE_BASE + 0x28)
91 #define CIO2_REG_MIPIBE_GLOBAL_LUT_DISREGARD (CIO2_REG_MIPIBE_BASE + 0x68)
92 #define CIO2_MIPIBE_GLOBAL_LUT_DISREGARD 1U
93 #define CIO2_REG_MIPIBE_PKT_STALL_STATUS (CIO2_REG_MIPIBE_BASE + 0x6c)
94 #define CIO2_REG_MIPIBE_PARSE_GSP_THROUGH_LP_LUT_REG_IDX \
95 (CIO2_REG_MIPIBE_BASE + 0x70)
96 #define CIO2_REG_MIPIBE_SP_LUT_ENTRY(vc) \
97 (CIO2_REG_MIPIBE_BASE + 0x74 + 4 * (vc))
98 #define CIO2_REG_MIPIBE_LP_LUT_ENTRY(m) /* m = 0..15 */ \
99 (CIO2_REG_MIPIBE_BASE + 0x84 + 4 * (m))
100 #define CIO2_MIPIBE_LP_LUT_ENTRY_DISREGARD 1U
101 #define CIO2_MIPIBE_LP_LUT_ENTRY_SID_SHIFT 1U
102 #define CIO2_MIPIBE_LP_LUT_ENTRY_VC_SHIFT 5U
103 #define CIO2_MIPIBE_LP_LUT_ENTRY_FORMAT_TYPE_SHIFT 7U
104
105 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_IRQCTRL_BASE */
106 /* IRQ registers are 18-bit wide, see cio2_irq_error for bit definitions */
107 #define CIO2_REG_IRQCTRL_EDGE (CIO2_REG_IRQCTRL_BASE + 0x00)
108 #define CIO2_REG_IRQCTRL_MASK (CIO2_REG_IRQCTRL_BASE + 0x04)
109 #define CIO2_REG_IRQCTRL_STATUS (CIO2_REG_IRQCTRL_BASE + 0x08)
110 #define CIO2_REG_IRQCTRL_CLEAR (CIO2_REG_IRQCTRL_BASE + 0x0c)
111 #define CIO2_REG_IRQCTRL_ENABLE (CIO2_REG_IRQCTRL_BASE + 0x10)
112 #define CIO2_REG_IRQCTRL_LEVEL_NOT_PULSE (CIO2_REG_IRQCTRL_BASE + 0x14)
113
114 #define CIO2_REG_GPREG_SRST (CIO2_REG_GPREG_BASE + 0x0)
115 #define CIO2_GPREG_SRST_ALL 0xffff /* Reset all */
116 #define CIO2_REG_FB_HPLL_FREQ (CIO2_REG_GPREG_BASE + 0x08)
117 #define CIO2_REG_ISCLK_RATIO (CIO2_REG_GPREG_BASE + 0xc)
118
119 #define CIO2_REG_CGC 0x1400
120 #define CIO2_CGC_CSI2_TGE BIT(0)
121 #define CIO2_CGC_PRIM_TGE BIT(1)
122 #define CIO2_CGC_SIDE_TGE BIT(2)
123 #define CIO2_CGC_XOSC_TGE BIT(3)
124 #define CIO2_CGC_MPLL_SHUTDOWN_EN BIT(4)
125 #define CIO2_CGC_D3I3_TGE BIT(5)
126 #define CIO2_CGC_CSI2_INTERFRAME_TGE BIT(6)
127 #define CIO2_CGC_CSI2_PORT_DCGE BIT(8)
128 #define CIO2_CGC_CSI2_DCGE BIT(9)
129 #define CIO2_CGC_SIDE_DCGE BIT(10)
130 #define CIO2_CGC_PRIM_DCGE BIT(11)
131 #define CIO2_CGC_ROSC_DCGE BIT(12)
132 #define CIO2_CGC_XOSC_DCGE BIT(13)
133 #define CIO2_CGC_FLIS_DCGE BIT(14)
134 #define CIO2_CGC_CLKGATE_HOLDOFF_SHIFT 20U
135 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF_SHIFT 24U
136 #define CIO2_REG_D0I3C 0x1408
137 #define CIO2_D0I3C_I3 BIT(2) /* Set D0I3 */
138 #define CIO2_D0I3C_RR BIT(3) /* Restore? */
139 #define CIO2_REG_SWRESET 0x140c
140 #define CIO2_SWRESET_SWRESET 1U
141 #define CIO2_REG_SENSOR_ACTIVE 0x1410
142 #define CIO2_REG_INT_STS 0x1414
143 #define CIO2_REG_INT_STS_EXT_OE 0x1418
144 #define CIO2_INT_EXT_OE_DMAOE_SHIFT 0U
145 #define CIO2_INT_EXT_OE_DMAOE_MASK 0x7ffff
146 #define CIO2_INT_EXT_OE_OES_SHIFT 24U
147 #define CIO2_INT_EXT_OE_OES_MASK (0xf << CIO2_INT_EXT_OE_OES_SHIFT)
148 #define CIO2_REG_INT_EN 0x1420
149 #define CIO2_REG_INT_EN_IRQ (1 << 24)
150 #define CIO2_REG_INT_EN_IOS(dma) (1U << (((dma) >> 1U) + 12U))
151 /*
152 * Interrupt on completion bit, Eg. DMA 0-3 maps to bit 0-3,
153 * DMA4 & DMA5 map to bit 4 ... DMA18 & DMA19 map to bit 11 Et cetera
154 */
155 #define CIO2_INT_IOC(dma) (1U << ((dma) < 4U ? (dma) : ((dma) >> 1U) + 2U))
156 #define CIO2_INT_IOC_SHIFT 0
157 #define CIO2_INT_IOC_MASK (0x7ff << CIO2_INT_IOC_SHIFT)
158 #define CIO2_INT_IOS_IOLN(dma) (1U << (((dma) >> 1U) + 12U))
159 #define CIO2_INT_IOS_IOLN_SHIFT 12
160 #define CIO2_INT_IOS_IOLN_MASK (0x3ff << CIO2_INT_IOS_IOLN_SHIFT)
161 #define CIO2_INT_IOIE BIT(22)
162 #define CIO2_INT_IOOE BIT(23)
163 #define CIO2_INT_IOIRQ BIT(24)
164 #define CIO2_REG_INT_EN_EXT_OE 0x1424
165 #define CIO2_REG_DMA_DBG 0x1448
166 #define CIO2_REG_DMA_DBG_DMA_INDEX_SHIFT 0U
167 #define CIO2_REG_PBM_ARB_CTRL 0x1460
168 #define CIO2_PBM_ARB_CTRL_LANES_DIV 0U /* 4-4-2-2 lanes */
169 #define CIO2_PBM_ARB_CTRL_LANES_DIV_SHIFT 0U
170 #define CIO2_PBM_ARB_CTRL_LE_EN BIT(7)
171 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN 2U
172 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT 8U
173 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP 480U
174 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP_SHIFT 16U
175 #define CIO2_REG_PBM_WMCTRL1 0x1464
176 #define CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT 0U
177 #define CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT 8U
178 #define CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT 16U
179 #define CIO2_PBM_WMCTRL1_TS_COUNT_DISABLE BIT(31)
180 #define CIO2_PBM_WMCTRL1_MIN_2CK (4 << CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT)
181 #define CIO2_PBM_WMCTRL1_MID1_2CK (16 << CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT)
182 #define CIO2_PBM_WMCTRL1_MID2_2CK (21 << CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT)
183 #define CIO2_REG_PBM_WMCTRL2 0x1468
184 #define CIO2_PBM_WMCTRL2_HWM_2CK 40U
185 #define CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT 0U
186 #define CIO2_PBM_WMCTRL2_LWM_2CK 22U
187 #define CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT 8U
188 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK 2U
189 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK_SHIFT 16U
190 #define CIO2_PBM_WMCTRL2_TRANSDYN 1U
191 #define CIO2_PBM_WMCTRL2_TRANSDYN_SHIFT 24U
192 #define CIO2_PBM_WMCTRL2_DYNWMEN BIT(28)
193 #define CIO2_PBM_WMCTRL2_OBFF_MEM_EN BIT(29)
194 #define CIO2_PBM_WMCTRL2_OBFF_CPU_EN BIT(30)
195 #define CIO2_PBM_WMCTRL2_DRAINNOW BIT(31)
196 #define CIO2_REG_PBM_TS_COUNT 0x146c
197 #define CIO2_REG_PBM_FOPN_ABORT 0x1474
198 /* below n = 0..3 */
199 #define CIO2_PBM_FOPN_ABORT(n) (0x1 << 8U * (n))
200 #define CIO2_PBM_FOPN_FORCE_ABORT(n) (0x2 << 8U * (n))
201 #define CIO2_PBM_FOPN_FRAMEOPEN(n) (0x8 << 8U * (n))
202 #define CIO2_REG_LTRCTRL 0x1480
203 #define CIO2_LTRCTRL_LTRDYNEN BIT(16)
204 #define CIO2_LTRCTRL_LTRSTABLETIME_SHIFT 8U
205 #define CIO2_LTRCTRL_LTRSTABLETIME_MASK 0xff
206 #define CIO2_LTRCTRL_LTRSEL1S3 BIT(7)
207 #define CIO2_LTRCTRL_LTRSEL1S2 BIT(6)
208 #define CIO2_LTRCTRL_LTRSEL1S1 BIT(5)
209 #define CIO2_LTRCTRL_LTRSEL1S0 BIT(4)
210 #define CIO2_LTRCTRL_LTRSEL2S3 BIT(3)
211 #define CIO2_LTRCTRL_LTRSEL2S2 BIT(2)
212 #define CIO2_LTRCTRL_LTRSEL2S1 BIT(1)
213 #define CIO2_LTRCTRL_LTRSEL2S0 BIT(0)
214 #define CIO2_REG_LTRVAL23 0x1484
215 #define CIO2_REG_LTRVAL01 0x1488
216 #define CIO2_LTRVAL02_VAL_SHIFT 0U
217 #define CIO2_LTRVAL02_SCALE_SHIFT 10U
218 #define CIO2_LTRVAL13_VAL_SHIFT 16U
219 #define CIO2_LTRVAL13_SCALE_SHIFT 26U
220
221 #define CIO2_LTRVAL0_VAL 175U
222 /* Value times 1024 ns */
223 #define CIO2_LTRVAL0_SCALE 2U
224 #define CIO2_LTRVAL1_VAL 90U
225 #define CIO2_LTRVAL1_SCALE 2U
226 #define CIO2_LTRVAL2_VAL 90U
227 #define CIO2_LTRVAL2_SCALE 2U
228 #define CIO2_LTRVAL3_VAL 90U
229 #define CIO2_LTRVAL3_SCALE 2U
230
231 #define CIO2_REG_CDMABA(n) (0x1500 + 0x10 * (n)) /* n = 0..19 */
232 #define CIO2_REG_CDMARI(n) (0x1504 + 0x10 * (n))
233 #define CIO2_CDMARI_FBPT_RP_SHIFT 0U
234 #define CIO2_CDMARI_FBPT_RP_MASK 0xff
235 #define CIO2_REG_CDMAC0(n) (0x1508 + 0x10 * (n))
236 #define CIO2_CDMAC0_FBPT_LEN_SHIFT 0U
237 #define CIO2_CDMAC0_FBPT_WIDTH_SHIFT 8U
238 #define CIO2_CDMAC0_FBPT_NS BIT(25)
239 #define CIO2_CDMAC0_DMA_INTR_ON_FS BIT(26)
240 #define CIO2_CDMAC0_DMA_INTR_ON_FE BIT(27)
241 #define CIO2_CDMAC0_FBPT_UPDATE_FIFO_FULL BIT(28)
242 #define CIO2_CDMAC0_FBPT_FIFO_FULL_FIX_DIS BIT(29)
243 #define CIO2_CDMAC0_DMA_EN BIT(30)
244 #define CIO2_CDMAC0_DMA_HALTED BIT(31)
245 #define CIO2_REG_CDMAC1(n) (0x150c + 0x10 * (n))
246 #define CIO2_CDMAC1_LINENUMINT_SHIFT 0U
247 #define CIO2_CDMAC1_LINENUMUPDATE_SHIFT 16U
248 /* n = 0..3 */
249 #define CIO2_REG_PXM_PXF_FMT_CFG0(n) (0x1700 + 0x30 * (n))
250 #define CIO2_PXM_PXF_FMT_CFG_SID0_SHIFT 0U
251 #define CIO2_PXM_PXF_FMT_CFG_SID1_SHIFT 16U
252 #define CIO2_PXM_PXF_FMT_CFG_PCK_64B (0 << 0)
253 #define CIO2_PXM_PXF_FMT_CFG_PCK_32B (1 << 0)
254 #define CIO2_PXM_PXF_FMT_CFG_BPP_08 (0 << 2)
255 #define CIO2_PXM_PXF_FMT_CFG_BPP_10 (1 << 2)
256 #define CIO2_PXM_PXF_FMT_CFG_BPP_12 (2 << 2)
257 #define CIO2_PXM_PXF_FMT_CFG_BPP_14 (3 << 2)
258 #define CIO2_PXM_PXF_FMT_CFG_SPEC_4PPC (0 << 4)
259 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_RGBA (1 << 4)
260 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_ARGB (2 << 4)
261 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR2 (3 << 4)
262 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR3 (4 << 4)
263 #define CIO2_PXM_PXF_FMT_CFG_SPEC_NV16 (5 << 4)
264 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_AB (1 << 7)
265 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_CD (1 << 8)
266 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_AC (1 << 9)
267 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_BD (1 << 10)
268 #define CIO2_REG_INT_STS_EXT_IE 0x17e4
269 #define CIO2_REG_INT_EN_EXT_IE 0x17e8
270 #define CIO2_INT_EXT_IE_ECC_RE(n) (0x01 << (8U * (n)))
271 #define CIO2_INT_EXT_IE_DPHY_NR(n) (0x02 << (8U * (n)))
272 #define CIO2_INT_EXT_IE_ECC_NR(n) (0x04 << (8U * (n)))
273 #define CIO2_INT_EXT_IE_CRCERR(n) (0x08 << (8U * (n)))
274 #define CIO2_INT_EXT_IE_INTERFRAMEDATA(n) (0x10 << (8U * (n)))
275 #define CIO2_INT_EXT_IE_PKT2SHORT(n) (0x20 << (8U * (n)))
276 #define CIO2_INT_EXT_IE_PKT2LONG(n) (0x40 << (8U * (n)))
277 #define CIO2_INT_EXT_IE_IRQ(n) (0x80 << (8U * (n)))
278 #define CIO2_REG_PXM_FRF_CFG(n) (0x1720 + 0x30 * (n))
279 #define CIO2_PXM_FRF_CFG_FNSEL BIT(0)
280 #define CIO2_PXM_FRF_CFG_FN_RST BIT(1)
281 #define CIO2_PXM_FRF_CFG_ABORT BIT(2)
282 #define CIO2_PXM_FRF_CFG_CRC_TH_SHIFT 3U
283 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR BIT(8)
284 #define CIO2_PXM_FRF_CFG_MSK_ECC_RE BIT(9)
285 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE BIT(10)
286 #define CIO2_PXM_FRF_CFG_EVEN_ODD_MODE_SHIFT 11U
287 #define CIO2_PXM_FRF_CFG_MASK_CRC_THRES BIT(13)
288 #define CIO2_PXM_FRF_CFG_MASK_CSI_ACCEPT BIT(14)
289 #define CIO2_PXM_FRF_CFG_CIOHC_FS_MODE BIT(15)
290 #define CIO2_PXM_FRF_CFG_CIOHC_FRST_FRM_SHIFT 16U
291 #define CIO2_REG_PXM_SID2BID0(n) (0x1724 + 0x30 * (n))
292 #define CIO2_FB_HPLL_FREQ 0x2
293 #define CIO2_ISCLK_RATIO 0xc
294
295 #define CIO2_IRQCTRL_MASK 0x3ffff
296
297 #define CIO2_INT_EN_EXT_OE_MASK 0x8f0fffff
298
299 #define CIO2_CGC_CLKGATE_HOLDOFF 3U
300 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF 5U
301
302 #define CIO2_PXM_FRF_CFG_CRC_TH 16
303
304 #define CIO2_INT_EN_EXT_IE_MASK 0xffffffff
305
306 #define CIO2_DMA_CHAN 0U
307
308 #define CIO2_CSIRX_DLY_CNT_CLANE_IDX -1
309
310 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_A 0
311 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_B 0
312 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A 95
313 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_B -8
314
315 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_A 0
316 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_B 0
317 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_A 85
318 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_B -2
319
320 #define CIO2_CSIRX_DLY_CNT_TERMEN_DEFAULT 0x4
321 #define CIO2_CSIRX_DLY_CNT_SETTLE_DEFAULT 0x570
322
323 struct cio2_csi2_timing {
324 s32 clk_termen;
325 s32 clk_settle;
326 s32 dat_termen;
327 s32 dat_settle;
328 };
329
330 struct cio2_buffer {
331 struct vb2_v4l2_buffer vbb;
332 u32 *lop[CIO2_MAX_LOPS];
333 dma_addr_t lop_bus_addr[CIO2_MAX_LOPS];
334 unsigned int offset;
335 };
336
337 #define to_cio2_buffer(vb) container_of(vb, struct cio2_buffer, vbb.vb2_buf)
338
339 struct csi2_bus_info {
340 u32 port;
341 u32 lanes;
342 };
343
344 struct cio2_queue {
345 /* mutex to be used by vb2_queue */
346 struct mutex lock;
347 struct media_pipeline pipe;
348 struct csi2_bus_info csi2;
349 struct v4l2_subdev *sensor;
350 void __iomem *csi_rx_base;
351
352 /* Subdev, /dev/v4l-subdevX */
353 struct v4l2_subdev subdev;
354 struct mutex subdev_lock; /* Serialise acces to subdev_fmt field */
355 struct media_pad subdev_pads[CIO2_PADS];
356 struct v4l2_mbus_framefmt subdev_fmt;
357 atomic_t frame_sequence;
358
359 /* Video device, /dev/videoX */
360 struct video_device vdev;
361 struct media_pad vdev_pad;
362 struct v4l2_pix_format_mplane format;
363 struct vb2_queue vbq;
364
365 /* Buffer queue handling */
366 struct cio2_fbpt_entry *fbpt; /* Frame buffer pointer table */
367 dma_addr_t fbpt_bus_addr;
368 struct cio2_buffer *bufs[CIO2_MAX_BUFFERS];
369 unsigned int bufs_first; /* Index of the first used entry */
370 unsigned int bufs_next; /* Index of the first unused entry */
371 atomic_t bufs_queued;
372 };
373
374 struct cio2_device {
375 struct pci_dev *pci_dev;
376 void __iomem *base;
377 struct v4l2_device v4l2_dev;
378 struct cio2_queue queue[CIO2_QUEUES];
379 struct cio2_queue *cur_queue;
380 /* mutex to be used by video_device */
381 struct mutex lock;
382
383 bool streaming;
384 struct v4l2_async_notifier notifier;
385 struct media_device media_dev;
386
387 /*
388 * Safety net to catch DMA fetch ahead
389 * when reaching the end of LOP
390 */
391 void *dummy_page;
392 /* DMA handle of dummy_page */
393 dma_addr_t dummy_page_bus_addr;
394 /* single List of Pointers (LOP) page */
395 u32 *dummy_lop;
396 /* DMA handle of dummy_lop */
397 dma_addr_t dummy_lop_bus_addr;
398 };
399
400 #define to_cio2_device(n) container_of(n, struct cio2_device, notifier)
401
402 /**************** Virtual channel ****************/
403 /*
404 * This should come from sensor driver. No
405 * driver interface nor requirement yet.
406 */
407 #define SENSOR_VIR_CH_DFLT 0
408
409 /**************** FBPT operations ****************/
410 #define CIO2_FBPT_SIZE (CIO2_MAX_BUFFERS * CIO2_MAX_LOPS * \
411 sizeof(struct cio2_fbpt_entry))
412
413 #define CIO2_FBPT_SUBENTRY_UNIT 4
414
415 /* cio2 fbpt first_entry ctrl status */
416 #define CIO2_FBPT_CTRL_VALID BIT(0)
417 #define CIO2_FBPT_CTRL_IOC BIT(1)
418 #define CIO2_FBPT_CTRL_IOS BIT(2)
419 #define CIO2_FBPT_CTRL_SUCCXFAIL BIT(3)
420 #define CIO2_FBPT_CTRL_CMPLCODE_SHIFT 4
421
422 /*
423 * Frame Buffer Pointer Table(FBPT) entry
424 * each entry describe an output buffer and consists of
425 * several sub-entries
426 */
427 struct __packed cio2_fbpt_entry {
428 union {
429 struct __packed {
430 u32 ctrl; /* status ctrl */
431 u16 cur_line_num; /* current line # written to DDR */
432 u16 frame_num; /* updated by DMA upon FE */
433 u32 first_page_offset; /* offset for 1st page in LOP */
434 } first_entry;
435 /* Second entry per buffer */
436 struct __packed {
437 u32 timestamp;
438 u32 num_of_bytes;
439 /* the number of bytes for write on last page */
440 u16 last_page_available_bytes;
441 /* the number of pages allocated for this buf */
442 u16 num_of_pages;
443 } second_entry;
444 };
445 u32 lop_page_addr; /* Points to list of pointers (LOP) table */
446 };
447
file_to_cio2_queue(struct file * file)448 static inline struct cio2_queue *file_to_cio2_queue(struct file *file)
449 {
450 return container_of(video_devdata(file), struct cio2_queue, vdev);
451 }
452
vb2q_to_cio2_queue(struct vb2_queue * vq)453 static inline struct cio2_queue *vb2q_to_cio2_queue(struct vb2_queue *vq)
454 {
455 return container_of(vq, struct cio2_queue, vbq);
456 }
457
458 #endif
459