1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Renesas RZ/V2H(P) Clock Pulse Generator 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #ifndef __RENESAS_RZV2H_CPG_H__ 9 #define __RENESAS_RZV2H_CPG_H__ 10 11 #include <linux/bitfield.h> 12 #include <linux/types.h> 13 14 /** 15 * struct pll - Structure for PLL configuration 16 * 17 * @offset: STBY register offset 18 * @has_clkn: Flag to indicate if CLK1/2 are accessible or not 19 */ 20 struct pll { 21 unsigned int offset:9; 22 unsigned int has_clkn:1; 23 }; 24 25 #define PLL_PACK(_offset, _has_clkn) \ 26 ((struct pll){ \ 27 .offset = _offset, \ 28 .has_clkn = _has_clkn \ 29 }) 30 31 #define PLLCA55 PLL_PACK(0x60, 1) 32 #define PLLGPU PLL_PACK(0x120, 1) 33 34 /** 35 * struct ddiv - Structure for dynamic switching divider 36 * 37 * @offset: register offset 38 * @shift: position of the divider bit 39 * @width: width of the divider 40 * @monbit: monitor bit in CPG_CLKSTATUS0 register 41 * @no_rmw: flag to indicate if the register is read-modify-write 42 * (1: no RMW, 0: RMW) 43 */ 44 struct ddiv { 45 unsigned int offset:11; 46 unsigned int shift:4; 47 unsigned int width:4; 48 unsigned int monbit:5; 49 unsigned int no_rmw:1; 50 }; 51 52 /* 53 * On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits, 54 * while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value 55 * `0x1f` to indicate that monitor bits are not supported for static divider 56 * clocks. 57 */ 58 #define CSDIV_NO_MON (0x1f) 59 60 #define DDIV_PACK(_offset, _shift, _width, _monbit) \ 61 ((struct ddiv){ \ 62 .offset = _offset, \ 63 .shift = _shift, \ 64 .width = _width, \ 65 .monbit = _monbit \ 66 }) 67 68 #define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \ 69 ((struct ddiv){ \ 70 .offset = (_offset), \ 71 .shift = (_shift), \ 72 .width = (_width), \ 73 .monbit = (_monbit), \ 74 .no_rmw = 1 \ 75 }) 76 77 /** 78 * struct smuxed - Structure for static muxed clocks 79 * 80 * @offset: register offset 81 * @shift: position of the divider field 82 * @width: width of the divider field 83 */ 84 struct smuxed { 85 unsigned int offset:11; 86 unsigned int shift:4; 87 unsigned int width:4; 88 }; 89 90 #define SMUX_PACK(_offset, _shift, _width) \ 91 ((struct smuxed){ \ 92 .offset = (_offset), \ 93 .shift = (_shift), \ 94 .width = (_width), \ 95 }) 96 97 /** 98 * struct fixed_mod_conf - Structure for fixed module configuration 99 * 100 * @mon_index: monitor index 101 * @mon_bit: monitor bit 102 */ 103 struct fixed_mod_conf { 104 u8 mon_index; 105 u8 mon_bit; 106 }; 107 108 #define FIXED_MOD_CONF_PACK(_index, _bit) \ 109 ((struct fixed_mod_conf){ \ 110 .mon_index = (_index), \ 111 .mon_bit = (_bit), \ 112 }) 113 114 #define CPG_SSEL0 (0x300) 115 #define CPG_SSEL1 (0x304) 116 #define CPG_CDDIV0 (0x400) 117 #define CPG_CDDIV1 (0x404) 118 #define CPG_CDDIV3 (0x40C) 119 #define CPG_CDDIV4 (0x410) 120 #define CPG_CSDIV0 (0x500) 121 122 #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) 123 #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) 124 #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) 125 #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5) 126 #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6) 127 #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7) 128 #define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13) 129 #define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14) 130 #define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15) 131 #define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16) 132 #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) 133 #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) 134 135 #define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON) 136 #define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON) 137 #define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON) 138 139 #define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1) 140 #define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1) 141 #define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1) 142 #define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1) 143 #define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1) 144 #define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1) 145 146 #define BUS_MSTOP_IDX_MASK GENMASK(31, 16) 147 #define BUS_MSTOP_BITS_MASK GENMASK(15, 0) 148 #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \ 149 FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask))) 150 #define BUS_MSTOP_NONE GENMASK(31, 0) 151 152 #define FIXED_MOD_CONF_XSPI FIXED_MOD_CONF_PACK(5, 1) 153 154 /** 155 * Definitions of CPG Core Clocks 156 * 157 * These include: 158 * - Clock outputs exported to DT 159 * - External input clocks 160 * - Internal CPG clocks 161 */ 162 struct cpg_core_clk { 163 const char *name; 164 unsigned int id; 165 unsigned int parent; 166 unsigned int div; 167 unsigned int mult; 168 unsigned int type; 169 union { 170 unsigned int conf; 171 struct ddiv ddiv; 172 struct pll pll; 173 struct smuxed smux; 174 struct fixed_mod_conf fixed_mod; 175 } cfg; 176 const struct clk_div_table *dtable; 177 const char * const *parent_names; 178 unsigned int num_parents; 179 u8 mux_flags; 180 u32 flag; 181 }; 182 183 enum clk_types { 184 /* Generic */ 185 CLK_TYPE_IN, /* External Clock Input */ 186 CLK_TYPE_FF, /* Fixed Factor Clock */ 187 CLK_TYPE_FF_MOD_STATUS, /* Fixed Factor Clock which can report the status of module clock */ 188 CLK_TYPE_PLL, 189 CLK_TYPE_DDIV, /* Dynamic Switching Divider */ 190 CLK_TYPE_SMUX, /* Static Mux */ 191 }; 192 193 #define DEF_TYPE(_name, _id, _type...) \ 194 { .name = _name, .id = _id, .type = _type } 195 #define DEF_BASE(_name, _id, _type, _parent...) \ 196 DEF_TYPE(_name, _id, _type, .parent = _parent) 197 #define DEF_PLL(_name, _id, _parent, _pll_packed) \ 198 DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed) 199 #define DEF_INPUT(_name, _id) \ 200 DEF_TYPE(_name, _id, CLK_TYPE_IN) 201 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 202 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 203 #define DEF_FIXED_MOD_STATUS(_name, _id, _parent, _mult, _div, _gate) \ 204 DEF_BASE(_name, _id, CLK_TYPE_FF_MOD_STATUS, _parent, .div = _div, \ 205 .mult = _mult, .cfg.fixed_mod = _gate) 206 #define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ 207 DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \ 208 .cfg.ddiv = _ddiv_packed, \ 209 .parent = _parent, \ 210 .dtable = _dtable, \ 211 .flag = CLK_DIVIDER_HIWORD_MASK) 212 #define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ 213 DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) 214 #define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \ 215 DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \ 216 .cfg.smux = _smux_packed, \ 217 .parent_names = _parent_names, \ 218 .num_parents = ARRAY_SIZE(_parent_names), \ 219 .flag = CLK_SET_RATE_PARENT, \ 220 .mux_flags = CLK_MUX_HIWORD_MASK) 221 222 /** 223 * struct rzv2h_mod_clk - Module Clocks definitions 224 * 225 * @name: handle between common and hardware-specific interfaces 226 * @mstop_data: packed data mstop register offset and mask 227 * @parent: id of parent clock 228 * @critical: flag to indicate the clock is critical 229 * @no_pm: flag to indicate PM is not supported 230 * @on_index: control register index 231 * @on_bit: ON bit 232 * @mon_index: monitor register index 233 * @mon_bit: monitor bit 234 * @ext_clk_mux_index: mux index for external clock source, or -1 if internal 235 */ 236 struct rzv2h_mod_clk { 237 const char *name; 238 u32 mstop_data; 239 u16 parent; 240 bool critical; 241 bool no_pm; 242 u8 on_index; 243 u8 on_bit; 244 s8 mon_index; 245 u8 mon_bit; 246 s8 ext_clk_mux_index; 247 }; 248 249 #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \ 250 _onbit, _monindex, _monbit, _ext_clk_mux_index) \ 251 { \ 252 .name = (_name), \ 253 .mstop_data = (_mstop), \ 254 .parent = (_parent), \ 255 .critical = (_critical), \ 256 .no_pm = (_no_pm), \ 257 .on_index = (_onindex), \ 258 .on_bit = (_onbit), \ 259 .mon_index = (_monindex), \ 260 .mon_bit = (_monbit), \ 261 .ext_clk_mux_index = (_ext_clk_mux_index), \ 262 } 263 264 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 265 DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1) 266 267 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 268 DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1) 269 270 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 271 DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1) 272 273 #define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \ 274 _ext_clk_mux_index) \ 275 DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \ 276 _ext_clk_mux_index) 277 278 /** 279 * struct rzv2h_reset - Reset definitions 280 * 281 * @reset_index: reset register index 282 * @reset_bit: reset bit 283 * @mon_index: monitor register index 284 * @mon_bit: monitor bit 285 */ 286 struct rzv2h_reset { 287 u8 reset_index; 288 u8 reset_bit; 289 u8 mon_index; 290 u8 mon_bit; 291 }; 292 293 #define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) \ 294 { \ 295 .reset_index = (_resindex), \ 296 .reset_bit = (_resbit), \ 297 .mon_index = (_monindex), \ 298 .mon_bit = (_monbit), \ 299 } 300 301 #define DEF_RST(_resindex, _resbit, _monindex, _monbit) \ 302 DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) 303 304 /** 305 * struct rzv2h_cpg_info - SoC-specific CPG Description 306 * 307 * @core_clks: Array of Core Clock definitions 308 * @num_core_clks: Number of entries in core_clks[] 309 * @last_dt_core_clk: ID of the last Core Clock exported to DT 310 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 311 * 312 * @mod_clks: Array of Module Clock definitions 313 * @num_mod_clks: Number of entries in mod_clks[] 314 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 315 * 316 * @resets: Array of Module Reset definitions 317 * @num_resets: Number of entries in resets[] 318 * 319 * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the 320 * number of CPG_BUS_m_MSTOP registers multiplied by 16. 321 */ 322 struct rzv2h_cpg_info { 323 /* Core Clocks */ 324 const struct cpg_core_clk *core_clks; 325 unsigned int num_core_clks; 326 unsigned int last_dt_core_clk; 327 unsigned int num_total_core_clks; 328 329 /* Module Clocks */ 330 const struct rzv2h_mod_clk *mod_clks; 331 unsigned int num_mod_clks; 332 unsigned int num_hw_mod_clks; 333 334 /* Resets */ 335 const struct rzv2h_reset *resets; 336 unsigned int num_resets; 337 338 unsigned int num_mstop_bits; 339 }; 340 341 extern const struct rzv2h_cpg_info r9a09g047_cpg_info; 342 extern const struct rzv2h_cpg_info r9a09g056_cpg_info; 343 extern const struct rzv2h_cpg_info r9a09g057_cpg_info; 344 345 #endif /* __RENESAS_RZV2H_CPG_H__ */ 346