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Searched defs:CCR (Results 1 – 15 of 15) sorted by relevance

/linux-3.3/arch/sh/include/cpu-sh2/cpu/
Dcache.h21 #define CCR 0xffffffec macro
/linux-3.3/arch/sh/include/cpu-sh3/cpu/
Dcache.h20 #define CCR 0xffffffec /* Address of Cache Control Register */ macro
/linux-3.3/arch/sh/include/cpu-sh2a/cpu/
Dcache.h20 #define CCR 0xfffc1000 /* CCR1 */ macro
/linux-3.3/arch/sh/include/cpu-sh4/cpu/
Dcache.h20 #define CCR 0xff00001c /* Address of Cache Control Register */ macro
/linux-3.3/arch/arm/mach-ixp2000/include/mach/
Dplatform.h74 unsigned long CCR; /* Clock divide */ member
/linux-3.3/include/linux/
Dcd1400.h75 #define CCR 0x05 macro
/linux-3.3/drivers/dma/
Dtxx9dmac.h90 u32 CCR; member
/linux-3.3/arch/cris/arch-v10/kernel/
Dkgdb.c387 P4, CCR, P6, MOF, enumerator
/linux-3.3/arch/arm/plat-omap/include/plat/
Ddma.h330 CSDP, CCR, CICR, CSR, enumerator
/linux-3.3/arch/blackfin/include/asm/
Dbfin_can.h117 #define CCR 0x0080 /* CAN Configuration Mode Request */ macro
/linux-3.3/arch/arm/common/
Dpl330.c251 CCR, enumerator
/linux-3.3/arch/arm/mach-imx/
Dclock-imx6q.c65 #define CCR (CCM_BASE + 0x00) macro
/linux-3.3/drivers/tty/
Dsynclink_gt.c402 #define CCR 0x89 /* clock control */ macro
Dsynclink.c344 #define CCR 0x06 /* Channel Control Register */ macro
/linux-3.3/include/sound/
Demu10k1.h443 #define CCR 0x09 /* Cache control register */ macro